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9 results about "Sequential test" patented technology

Cost-effective tool for sequential testing

PCT designated stageWO2026149928A1Iterative methodologyCost effectiveness
The present invention relates to computer implemented adaptive and iterative methods to improve and accelerate a quality control decision or a performance test in a specific technical field while reducing the overall cost of the quality control or performance test process, respectively; the method comprising: constructing a sequential test; iterating the following steps using the sequential test until a decision is made, obtaining a set of samples, checking the decision of the criteria for the set of samples, determining in an adaptive way the optimal number of additional data samples required for the subsequent iterative step if no decision has been made in the current iteration.
Owner:HCEMM NONPROFIT KFT +1

Asphalt mixture creep fatigue interaction damage evaluation method

The invention discloses an asphalt mixture creep fatigue interaction damage evaluation method which comprises the following steps: S1, carrying out a direct tensile fatigue test and a static creep test on an asphalt mixture sample to obtain stress-strain data; s2, constructing a fatigue damage model of the asphalt mixture, and determining fitting parameters of the model; s3, establishing a creep damage constitutive model and a creep damage model, determining fitting parameters of the creep damage model, and calculating the creep critical damage degree of the asphalt mixture; s4, performing sequential tests of different loading sequences on the asphalt mixture test piece; s5, calculating damage corresponding to different sequential tests; s6, correcting the fatigue damage model and the creep damage model; and S7, establishing a creep fatigue interaction model. The method can be used for evaluating and identifying the relationship between damage accumulation and interaction of the asphalt mixture under the interaction of creep and fatigue.
Owner:CHANGSHA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Sequential test design method based on BDNN and key area density weighting

The invention relates to a sequential test design method based on BDNN and key area density weighting, and relates to the technical field of radars. The method comprises the steps of performing general feature extraction on an initial data set through a constructed dynamic adaptive BDNN model, and outputting a continuous prediction result and a classification prediction result; a multi-target chaotic particle swarm optimization algorithm is adopted to identify key areas in the multi-dimensional factor space, after an optimal solution set is obtained through iterative optimization, comprehensive scores are calculated and screened, and high-priority key areas are output; on the basis of the high-priority key area, density weighted sequential sampling is implemented to generate multi-source candidate points, the comprehensive weight of each candidate point is calculated, and final sampling points are screened out by maximizing the sum of the comprehensive weight and the spatial distance; and verifying the final sampling point, and fusing the verified sample with the initial data set for retraining the dynamic adaptive BDNN model until a preset convergence condition is met. The performance of the detection system can be improved.
Owner:NAT UNIV OF DEFENSE TECH

System and method for sample-efficient sequential comparative evaluation of robot policies

PendingUS20260208354A1Robot controlOperations research
A method for a robot control policy evaluation framework is described. The method includes selecting a first robot control policy and a second robot control policy from a plurality of robot control policies. The method also includes performing a sequential testing of the first robot control policy and the second robot control policy. The method further includes incrementally collecting statistical evidence during the performing of the sequential testing. The method also includes completing the sequential testing in response to the statistical evidence establishing a performance of the first robot control policy being greater than the performance of the second robot control policy or the performance of the second robot control policy being less than the performance of the first robot control policy.
Owner:TOYOTA RESEARCH INSTITUTE INC +1

BGA (Ball Grid Array) chip test frame

The invention relates to the technical field of chip testing, in particular to a BGA (ball grid array) chip testing frame which comprises a supporting mounting disc, a lifting mounting disc is arranged over the supporting mounting disc in an opposite manner, and the BGA chip testing frame further comprises a rotary displacement mechanism which is arranged on the lifting mounting disc and comprises a plurality of displacement combination detection modules; the chip positioning and clamping mechanisms are arranged on the lifting mounting disc at equal angles, and each chip positioning and clamping mechanism comprises a displacement adjusting module and an auxiliary clamping module. Automatic sequential testing is achieved through the rotary multi-station design, and the detection efficiency is greatly improved; a flexible linkage clamping and thermoplastic temperature control fixing technology is adopted, so that lossless self-adaptive clamping of a chip is realized; the modular detection unit supports rapid reloading and flexible layout; a multi-stage rotary conductive structure ensures continuous and stable power supply and signals in the test process; and a pneumatic pick-and-place device is integrated, manual intervention is reduced, and access to an automatic production line is easy.
Owner:HUAXINTU TECHNOLOGY (SHENZHEN) CO LTD

Parallel test method, module information conversion method and device and readable storage medium

The invention relates to a parallel test method, a module information conversion method and device and a readable storage medium, and the method comprises the steps: obtaining the module information of a plurality of test modules, building a module mapping table, and sorting the test modules in the module mapping table; combining the plurality of test modules into a plurality of module arrays by utilizing the module mapping table according to parallel test requirements; calculating a plurality of bonding pad values of the test module in the module array according to the number and the serial number of the bonding pads of the test module; and sequentially selecting the module array for parallel testing, and determining an external pin pricking distribution mode of the parallel testing equipment based on a plurality of bonding pad values of the testing modules in the module array. According to the technical scheme, module merging and pad information conversion can be automatically completed based on module information of sequential testing and parallel testing requirements, the module information conversion efficiency and accuracy are greatly improved, and then the chip testing efficiency is improved through parallel testing.
Owner:SEMITRONIX

Control motherboard testing method and device thereof

This application provides a method and apparatus for testing control motherboards. The method includes: retrieving cost-related attribute data and benefit-related attribute data for each test item of a first control motherboard, wherein each test item of the first control motherboard is tested in its original order; the larger the cost-related attribute data and benefit-related attribute data, the longer the total testing time for each test item; inputting the cost-related attribute data and benefit-related attribute data of each test item of the first control motherboard into a multi-attribute decision model to obtain a test decision for a target batch of control motherboards, wherein the target batch of control motherboards includes multiple second control motherboards, the second control motherboards being of the same model as the first control motherboards; and testing each of the second control motherboards in the target batch of control motherboards according to the test decision of the target batch of control motherboards. This method improves the efficiency of testing control motherboards.
Owner:QINGDAO ZHIDONG SEIKO INSTR CO LTD

A method for evaluating the effect of an AB test experiment based on a dynamic confidence interval

The application discloses a kind of based on dynamic confidence interval AB test test effect evaluation method, it is related to big data analysis technical field, including, to historical time series is carried out autoregression analysis, extraction autoregression coefficient, and according to time series analysis theory obtains dynamic variance inflation factor, uses dynamic variance inflation factor to correct posterior distribution variance, generates corrected posterior distribution variance;By the mean of posterior distribution and corrected posterior distribution variance Double optimization dynamic confidence interval is constructed, compares double optimization dynamic confidence interval with preset sequential test boundary and makes decision, generates evaluation decision;Based on evaluation decision, the mean of posterior distribution and corrected posterior distribution variance are used as recommended parameter, set the initialization parameter recommendation of next stage AB test test, and integration generates AB test test effect evaluation report.The application enhances the accuracy and robustness of confidence interval.
Owner:MOJI FENGYUN BEIJING SOFTWARE TECH DEV CO LTD

Multi-input remote heads for sequential testing

An input selector for electrically connecting one of a plurality of test signals from a device under test to a test and measurement instrument includes a multiplexer having multiple inputs, each of the multiple inputs coupled to a different one of the plurality of test signals from the device under test, and having an output of a selected one of the multiple inputs, and an amplifier coupled to the output of the multiplexer for amplifying the selected test signal of the device under test before being sent as an output of the input selector to the test and measurement instrument. In alternative architectures, two or more amplifiers are coupled to the plurality of test signals, and the multiplexer selects an output of one of the two amplifiers to pass to a measurement instrument for testing.
Owner:TEKTRONIX INC