83 results about "Sequential test" patented technology

For each phase of a controller, a pair of semiconductor switches comprises a high side switch and a low side switch. A direct current voltage bus provides electrical energy to the semiconductor switches at a test voltage level less than a full operational voltage level. A measuring circuit is adapted to measure the direct current bus voltage. A data processor determines that a deficiency in a tested, related semiconductor switch is present if the measured direct current bus voltage decreases or collapses upon activation of a particular semiconductor switch in the same phase of the controller, or if other sequential test results indicate a deficiency. If the deficiency in the related semiconductor switch is present the processor may prevent the voltage supply from providing the full operational voltage to the direct current data bus to prevent damage to the motor or the controller, for example.

A lipid bilayer with affinity to an analyte, which directly signals binding by a changes in the light absorption spectra. This novel assay means and method has special applications in the drug development and medical testing fields. Using a spectrometer, the system is easily automated, and a multiple well embodiment allows inexpensive screening and sequential testing. This invention also has applications in industry for feedstock and effluent monitoring.

The invention relates to a multicore communication cable comprehensive tester. The tester comprises a line-sequential test signal transmitter and a host. The tester is characterized in that the line-sequential test signal transmitter comprises a coding CPU and a code-sending circuit which is connected with the coding CPU and controlled by the coding CPU; the host comprises a decoding CPU, a code-receiving circuit, a fault range-finding signal transmitting/receiving circuit, a monitor and a keyboard; and the code-receiving circuit, the fault range-finding signal transmitting/receiving circuit, the monitor and the keyboard are separately connected with the decoding CPU, the code-receiving circuit adopts a low-speed AD chip, and the code-receiving circuit and the code-receiving circuit are provided with optocouplers which are separated from a cable to be tested. The tester of the invention has simple structure, low cost, high reliability and high anti-interference performance, and can be used to test long cables and be applicable to the connection and maintenance projects of various cables.

The invention relates to a network speed test method and a network speed test system. The method includes the following steps: a network speed test request is sent into a waiting queue of a server by a client to be queued; if the judgment result of the server is test starting, then the server judges the variety of a test mode; if the test mode is pressure test, then the server sends a speed-testing command to the client, and cooperates with the client to carry out a TCP (transfer control protocol) network speed test and/or an HTTP (hypertext transfer protocol) network speed test; if the test mode is sequence test, whether the TCP network speed test and/or the HTTP network speed test are/is executed by the current server is judged, if so, then a waiting command is sent to the client, and if not, then the server cooperates with the client to carry out the TCP network speed test and/or the HTTP network speed test. The invention can visually and objectively test the speed of all broadband networks to provide reliable technical support for users to obtain accurate bandwidth data of operators.

A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links. A method for testing a series of links having at least three alternating transmitter and receiver links of a plurality of transmitter and receiver links in a SerDes core including generating at least one test data signal; transmitting the at least one test data signal sequentially through the transmitter and receiver links of the series of links; receiving the at least one test data signal from a last link of the series of transmitter and receiver links; and checking the at least one test data signal received.

An automatic power supply testing system records a preset test order of first and second power supplies with a recording module. The automatic power supply testing system controls a first control unit to connect a first connector connected to the first power supply to a simulation load to test the first power supply according to the preset test order by a determination control module and obtains a first test result. The automatic power supply testing system controls a second control unit to connect a second connector connected to the second power supply to the simulation load to test the second power supply after determining that the first test result is displayed and obtain a second test result. A display module displays the electrical stability of the first and second power supplies.

The invention provides a hand-held cable continuity test device for a rail vehicle. The bus switch module (A) of the device is provided with a cable end. The contacts of A are connected with an idle bus and a test bus respectively. Each bus is connected with a grounding end through the contacts of grounding switch modules (B). Drive and grounding ports are arranged. Each switch module is providedwith an enable end and contacts. The slave device of the system comprises the hand-held cable continuity test device, control and communication modules, a power supply, a power supply switch module (C) and a voltage measurement circuit. The power supply is connected with the test bus through the contacts of C. The control module is connected with the drive. The enable end is connected with contacts and the drive. Short circuit and continuity test is carried out on a connected first cable. A master device determines a corresponding test result. Next cables on the same A are tested in reverse order until the last one. The test comprises the steps that the master device sends a test signal to the slave device; and the slave device controls the contact action of the slave device, and notifiesthe master device to control the contact action after switching. The test result is determined according to voltage. The volume is small, and the speed is fast.

A probe apparatus for sequentially testing electrical characteristics of chips includes an imaging unit for capturing images of the electrode pads of the inspection substrate, and a unit for calculating contact positions at which the probes are expected to contact with the electrode pads. The probe apparatus further includes a storage unit for storing correction data in which reference points on a reference substrate are associated with correction amounts corresponding to differences between actual and calculated contact positions of the reference points, and a unit for obtaining actual contact positions for the electrode pads by measuring relative positions of the electrode pads with respect to the reference points and correcting the calculated contact positions of the electrode pads based on the relative positions and the correction data.

The invention discloses a sequential test optimization method based on a multi-objective genetic programming algorithm. The method comprises the steps of firstly initializing to obtain a fault diagnostic tree population, using the multi-objective genetic programming method to select, cross and mutate a fault diagnostic tree, during the iteration of each generation, grouping the fault diagnosis tree individuals, wherein, the adaptability of each individual is calculated by using grouping adaptability and a crowding distance; after multiple iterations, selecting non-domination individuals from a final generation population as a non-domination fault diagnosis tree of the sequential test of the system. The sequential test optimization method based on the multi-objective genetic programming algorithm can be used for acquiring a Pareto optimum solution of the fault diagnosis tree of the sequential test for which multiple test indexes can be used as optimized targets, the optimum solutions can be selected by testers to provide guidance for system testers.

The present invention discloses a test method and a testing apparatus for type 3i receivers which use multicarrier operation in HSDPA. The method sequentially tests each carrier, one at a time. Applying multi-switches, channel emulators and efficient wirings, performance tests can be performed without any need for changing the User Equipment to be tested. In case a single carrier test is passed, the next carrier is selected for the test. All carriers are thus tested sequentially against a single carrier throughput requirement until all carriers have been processed.

The invention discloses a sequential-test dynamic adjustment method based on the AO* algorithm. The sequential-test dynamic adjustment method includes the steps that an optimal fault diagnosis tree of an electronic system is obtained through the AO* algorithm; then the testing cost of a test and the probability dynamic condition of a fault are monitored, and when the testing cost of the test is increased, a fault node selecting a test point is reevaluated; when the testing cost of the test is reduced, a fault node which does not select the test point is reevaluated, and the optimal fault diagnosis tree is adjusted; when the probability of the fault is changed, the optimal fault diagnosis tree is adjusted. According to changes of the testing cost and changes of the fault probability in the electronic system, the present optimal fault diagnosis tree is correspondingly adjusted, the new optimal fault diagnosis tree is rapidly obtained, and adaptive dynamic adjustment of the sequential test is achieved.

The invention belongs to the technical field of spacecraft structures, relates to a design verification test method applicable to a mild detonation fuse separation device, and specifically relates to the test piece state, test items, test boundary and the like of a mild detonation fuse separation device. The design verification test method is a reasonable, comprehensive and effective test method for verifying the correctness of design state. According to the method, design verification test of a mild detonation fuse separation device 7 is carried out by combining a 1:1 test piece and a flat-plate test piece. The 1:1 test piece simulates the environmental conditions in the flight process of a spacecraft, the test items include temperature cycle, half-sine shock, sine scanning and random vibration, and high-temperature 1 ignition, low-temperature ignition and room-temperature ignition are carried out after the completion of the tests. The flat-plate test piece simulates the other environmental conditions; test is carried out in multiple branches: (1) 2m drop; (2) high-temperature storage; (3) temperature-humidity-height, vibration and acceleration sequential test; and (4) 12m drop; and high-temperature 2 ignition, low-temperature ignition and room-temperature ignition are carried out in groups after the completion of the first three branch tests.

The invention provides a website service quality testing method and a device. The method comprises the following steps: receiving a plurality of tasks; pretesting each task in the plurality of tasks, and recording the first peak rate and first testing duration of each task; grouping the plurality of tasks according to the first peak rate and the first testing duration of each task and a testing thread; determining the implementing time of each group of tasks according to a task of which the first testing duration is longest in each group of tasks; testing multiple groups of tasks in sequence according to the implementing time of each group of tasks. According to the method in the embodiment of the invention, a detecting machine can be protected from being blocked in a testing process; moreover, a peak bandwidth is not over high, so that more tasks can be borne on the premise of ensuring the quality of a testing result, and more large and small file hybrid tasks can be borne on the other hand; the method is not only suitable for website service quality testing based on an http protocol, but can also be applied to various other similar website service quality testing.

The invention relates a method for testing the high pressure regulating valve steam inlet sequence, and particularly relates to a method for optimizing a steam turbine high pressure regulating valve steam inlet sequence testing experiment. The invention aims to solve a problem that a traditional high pressure regulating valve steam inlet sequence testing experiment method is too long in experimental time. According the test scheme which is designed and optimized according to nozzle set arrangement information of different numbers of high pressure regulating valves, repetitive steps in a traditional testing process are optimized and combined, and a process of unnecessary repeated opening or repeated closing existing in multiple groups of experiments is removed; then running parameters and control modes of a unit are regulated so as to meet experimental conditions, and a regulating valve on-off experiment is carried out. The method provided by the invention can effectively shorten the experimental time, and solves the problem that the traditional test method requires a very long time in allusion to a unit experiment. The method is applicable to the test field of steam turbine high pressure regulating valve steam inlet sequence optimization.

A continuous indicator strip having a multiplicity of separate individual sequential test sections along the surface thereof, wherein a plurality of test sections are impregnated with the same indicator enabling the utilization of the strip for sequential repetitive testing of samples, the strip being provided with at least 20 such test sections.

A testing system and method for testing integrated circuits with radio frequency (RF) antennas is disclosed. The system includes an alignment plate for receiving a device under test (DUT) having an RF transmitting antenna, an enclosure surrounding but separated from the transmitting antenna, a receiving antenna in a telescopic enclosure, and a conversion circuit connected to the receiving antenna. The conversion circuit is configured to convert an RF output from the DUT to a direct current (DC) voltage. The DC voltage is used as a proxy for the RF output to test the DUT. When testing chips with RF ports, the chip or ports are surrounded by the enclosure which is non-radio reflective and includes antennas for receiving RF outputs disbursed around the enclosure, or a single antenna. If multiple receiving antennas are used, sequential testing can also detect directional transmission patterns to confirm that the direction is correctly calibrated.