The invention, which relates to the field of FPGA and
machine learning, discloses a high-flow-degree MambaV2
hardware acceleration system with an optimized calculation sequence based on FPGA, comprising a preceding stage module, a
tensor expansion module, a
hidden layer state calculation module, an output state calculation module, a residual multiplication normalization module and an output
linear layer module. The calculation process of the MambaV2
algorithm is divided into a plurality of pipeline levels, and a
data stream is output in a pipeline form. According to the method, an original
algorithm structure is not changed, the operation sequence of a
hidden layer state equation in an original
algorithm is changed, an algorithm for optimizing the calculation sequence is provided, the number of times of operation is reduced, cache consumption is reduced, the MambaV2 model is deployed and reasoned on an FPGA, the edge scene deployment requirement is met, customized acceleration of the FPGA is utilized, and data streams are adjusted, so that the edge scene deployment efficiency is improved. The pipeline design of the whole algorithm is realized, the
utilization rate of computing resources is improved, the problem of data blocking is solved, and computing
delay and cache consumption are reduced.