Retention time sequence optimization method based on multiplexing of buffer unit

Abstract

The invention discloses a retention time sequence optimization method based on multiplexing of a buffer unit. The method comprises the steps: finding the buffer unit on a function data path, wherein the function data path has the same starting point with a scanning path violating the retention time sequence; determining the maximum output load capacitance of the buffer unit according to the current time sequence; determining the maximum length of an interconnection line according to the maximum output load capacitance of the buffer unit and the current wiring condition; analyzing whether a new unit is allowed to be inserted to reduce the output load capacitance of the buffer unit or not according to the local unit density of an area where the buffer unit is located if the multiplexing of the buffer unit will additionally build a time sequence violation path, and if yes, reducing the output load capacitance of the buffer unit by inserting the new unit; finally, determining the connection relationship of the scanning input end of a scanning register according to the time sequence and the physical information. The method optimizes the retention time sequence of the scanning path in design, decreases the insertion number of buffer units, and reduces the design density and power consumption.

Description

technical field [0001] The invention relates to the field of VLSI physical design, in particular to a method for optimizing hold time sequence based on buffer unit multiplexing. Background technique [0002] With the gradual reduction of the process size and the increasingly significant interconnect effect, the number of buffer cells (buffer buffer, inverter, delay cell) in the design continues to increase. Inserting buffer cells into the physical design is a common way to fix timing violations. Due to the low operating frequency in scan mode and the simple logic of the scan path, hold time timing violations usually occur in the scan path. Hold-time timing violation paths are usually repaired by inserting buffer cells. However, in the later stages of the design, some paths cannot be inserted into buffer cells due to too high local cell density, and further timing optimization of the design cannot be done. At the same time, in the current design process, repairing the timin...

AI Technical Summary

Problems solved by technology

Hold-time timing violation paths are usually fixed by inserting buffer cells, however, in the later stages of the design, some paths cannot be inserted into buffer cells due to too high local cell density, and further timing optimization of the design cannot be done

At the same time, in the current design process, repairing the timing violation of the scan path and the functional data path is performed independently, resulting in repeated insertion of buffer cells in the scan path and functional data path, which increases the cell density of the design. Excessive cell density will increase the design area and Power consumption brings hidden dangers of voltage drop (IR-drop)

Images