291 results about "Process deviations" patented technology

Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

A system and method for monitoring a condition of a monitored system. Estimates of monitored parameters from a model of the system provide residual values that can be analyzed using a sequential probability ratio test (“SPRT”). The invention employs empirically derived distributions in the SPRT to provide more accurate and sensitive alerts of impending faults, breakdowns and process deviations. The distributions can be generated from piecewise continuous approximation or spline functions based on the actual distribution of residual data to provide improved computational performance. The distributions can be provided before monitoring, or can be updated and determined during monitoring in an adaptive fashion.

A semiconductor device layout involving the following: arranging active regions of a plurality of transistors having at least more than one first and second electrodes disposed on a substrate; arranging a plurality of gates of transistors between more than one first and second electrodes of those active regions respectively by positioning at least more than one gates having predetermined width and length at a constant gap on the substrate; and arranging a plurality of dummy gates having predetermined width and length between a plurality of transistors (or between and outside transistors) at the same gap as that of the gates of transistors on the substrate, so that all the gates of transistors are arranged at a constant gap to minimize the variance of process deviations and accordingly reduce the difference of threshold voltage of transistors, thereby increasing reliability of the semiconductor device.

The invention belongs to the technical field of the memory, and relates to a one-time programming resistance random memory unit, an array, a memory and an operation method thereof. The one-time programming resistance random memory unit utilizes binary or multi-variant metal oxide which has the structural characteristic of 2T2R, and represents the memory state 1 and 0 through the state combination difference of a first memory resistance and a second memory resistance. The one-time programming resistance random memory unit, array and memory are not easy to be influenced by the process deviation, and have the advantages of fast reading speed, high read-write tolerance and nonvolatility.

The invention relates to a PCB (printed circuit board) back drilling method. The PCB back drilling method comprises the following steps: fixing a PCB on a machine table, and mounting a drill bit on a drilling machine; selecting a target layer, and determining an actual control depth h1 of the target layer; and determining a back drilling control depth h of the PCB according to the actual control depth h1 of the target layer and a preset safety length M of a stub and controlling the drill bit to drill a hole drilling machine control system. According to the PCB back drilling method, influence of thickness uniformity of the board, cone height of a drill tip and copper/ tin-plating process variation on the accuracy of the control depth can be reduced; and through introduction of the safety length M of the stub, the precision of the PCB back drilling control depth h can be effectively controlled, thus achieving precision control of the stub and eliminating adverse effects of the stub on a signal.

A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

The invention discloses a complementary metal oxide semiconductor (CMOS) automatic gain control amplifier for canceling direct current offset. The CMOS automatic gain control amplifier comprises a cascade amplification link, an automatic gain control feedback loop and a direct current offset canceling feedback loop. The cascade amplification link uses multistage variable gain amplification units for cascading and can achieve high gain and enlarge high gain dynamic ranges. The automatic gain control feedback loop uses a charge pump structure and has the advantages that the automatic gain control feedback loop is less influenced by process deviation and temperature deviation, is capable of accurately detecting narrow-band and wide-band signal amplitude and is suitable for achieving CMOS processes. The direct current offset canceling feedback loop uses two-stage negative feedback loops, and each of the two-stage negative feedback loops uses an integrator as low-pass negative feedback; an active device is used as an integrator input resistor, and an equivalent resistor is provided with characteristics of temperature compensation; and the automatic gain control amplifier for canceling the direct current offset is capable of effectively canceling the direct current offset superposed by a preceding stage circuit and the direct current offset of the amplification link and is provided with a lower high pass corner frequency and a higher integrated level, and the automatic gain control amplifier for canceling the direct current offset is small in low-frequency signal loss and requires no off-chip passive devices (high value resistors or capacitors and the like). The automatic gain control amplifier is applicable to wireless communication receivers with zero intermediate frequency structures in the CMOS processes.

The invention relates to a method and a device for analyzing the reliability of an integrated circuit. In the analytical method, a unit circuit delayed aging stochastic analysis reference model in consideration with both negative bias temperature instability (NBTI) effect and process parameter perturbation is established, a scaling function and an equivalent aging time concept are provided to solve the delayed statistical distribution of a unit circuit under the actual work environment quickly from the reference model, and the pre-clipping process of the circuit is provided to reduce the complexity of reliable analysis. The device of the invention comprises an input unit, an output unit, a program storage unit, an external bus, a memory, a storage administration unit, an input/output bridging unit, a system bus and a processor. In the method and the device, the effect of the process parameter perturbation, the NBTI effect and the work environment of the circuit on reliability are considered simultaneously, and the complexity of the reliable analysis can be reduced effectively by utilizing the scaling function, equivalent aging time and the pre-clipping technology so as to realize the quick analysis on the reliability of super-large-scale integrated circuits in consideration with process deviation.

The invention discloses a high-precision annular oscillator, and a frequency calibration circuit and method thereof. The high-precision annular oscillator comprises a band gap reference circuit, a reference current circuit, a current adjusting circuit, an annular oscillation circuit and an output buffer circuit. The frequency calibration circuit comprises a frequency divider, a counter, a comparator, a register and a nonvolatile memory. The frequency calibration circuit can rapidly position the adjusting current needed by the high-precision annular oscillator and store an adjustment arrangement in the nonvolatile memory. According to the invention, the high-precision annular oscillator cooperates with the frequency calibration circuit so that the effects of temperature deviations, voltage deviations and technology deviations on oscillation frequencies can be compensated, and thus the high precision of the oscillation frequencies can be realized. Through the cooperation between the high-precision annular oscillator and the frequency calibration circuit, high-precision oscillation frequencies are obtained, at the same time a complex circuit is avoided, the area and power consumption of a chip are reduced, the non-linearity, error and noise of a simulation comparison circuit are avoided, the frequency precision is improved, and the testing time and cost of the chip are saved.

The invention provides a layout design photoetching technology friendliness detection method based on regular figure filtering. According to the layout design photoetching technology friendliness detection method based on regular figure filtering, by adding a step of filtering original object figure data before steps of performing optical proximity effect correction and technological error figure simulation, the time consumption of layout design photoetching technology friendliness detection is shortened, the usage cost of software and hardware is reduced, and also the extremely good matching between a detection result and a method of prior art can be realized, and thus the rapid accurate search for technological hot-spot areas in layout design is realized.

The invention discloses a voltage adjuster circuit, which includes an operational amplifier. A positive direction inputting terminal of the operational amplifier receives input signal, an outputting terminal of the operational amplifier connects with a source follower composed of NMOS pipe, the operational amplifier also connect with a biasing circuit, the biasing circuit provides biasing signal to the operational amplifier. The invention also discloses a resistor tolerance compensation method, the circuit pole point is proportional to corresponding resistor, the resistor uses same technique variable direction resistor or same resistor, when resistor changes, the pole point moves towards to same direction on coordinate for compensating increase biasing and phase biasing caused by resistor variable. The circuit provided by the invention can reduce effect to the circuit increase and phase caused by factors such as technique biasing or temperature biasing efficiently, ensures the circuit property.

The invention discloses a frequency complex for fast locking phaselocked loop. The frequency complex comprises a mixed signal voltage-controlled oscillator, a bimodule preset frequency divider, a digital processing unit, a nonvolatile memory, a phase-frequency detector, a charge pump and a loop filter. By using the invention, the processing of correcting the phaselocked loop in every charging can be avoided, the presetting on the output frequency of the mixed signal voltage-controlled oscillator can be carried out precisely with small difference between the preset frequency and the target frequency under process variation, and the phaselocked loop can finish locking in an extremely short time. In addition, the modules comprising the nonvolatile memory can be manufactured by standard CMOS process and conveniently applied in fast frequency hopping communication systems.

The invention discloses a PUF (Physical Unclonable Functions) circuit based on threshold deviation delay. The PUF circuit comprises a data input module, a controller, a decision device and a PUF unit circuit, wherein external data is accessed into the input end of the data input module; the output end of the data input module is connected with the input end of the controller; the PUF unit circuit comprises an i-bit threshold deviation delay circuit; the threshold deviation delay circuit consists of two delay units; and the two delay units are respectively a first delay unit and a second delay unit. The PUF circuit has the advantages that the threshold deviation delay circuit is configured through control signals, so that a plurality of pieces of extractible process deviation exist in the PUF circuit; output signals (secret keys) of the PUF circuit can be reconstructed; and the output secret key change can be realized without replacing hardware.

The invention provides an input undervoltage protecting circuit of a switching power supply controller. The input undervoltage protecting circuit of the switching power supply controller comprises a current detection circuit, a reference voltage generating circuit, an undervoltage protecting signal generating circuit and a pulse outputting control circuit. The current detection circuit comprises a controller internal resistor R2 and a controller external resistor R1, and the resistance value of the R2 is far smaller than that of the R1. The reference voltage generating circuit comprises an internal resistor R3 and a reference current source Iref, and the R3 and the R2 are resistors of the same type in the controller. The undervoltage protecting signal generating circuit comprises a comparator comp. A protecting point input voltage Vin(p) meets the formula (please see the formula in the specification). When the input voltage Vin of a switching power supply drops to be lower than the protecting point input voltage Vin(p), the output end UVP of the comparator comp generates undervoltage protecting signals to control the pulse outputting control circuit to cut off pulse output of GATE pins of the controller. According to the input undervoltage protecting circuit of the switching power supply controller, the peripheral circuits of the controller are simplified, the loss is small, meanwhile, the precision of input undervoltage protecting is high, and process bias is small. The invention further provides an input undervoltage protecting circuit with feed-forward compensation, the feed-forward compensation current Icom is in proportion to input voltages, the precision is high, and the process bias is small.

The invention discloses a calibration system and a calibration method suitable for a current source array in a multichannel sectional type current steering DAC (digital to analog converter). The calibration method suitable for the current source array in the multichannel sectional type current steering DAC includes steps: firstly, calibrating a channel, and then sequentially calibrating other channels, and enabling output among all the channels to tend to be uniform, wherein when the channels are calibrated, switches in a current source switch array are by selectively closed and calibrated, and an output amplitude adjustment circuit is adjusted so as to sequentially calibrate a low data bit segment and a high data bit segment of the current source array segment by segment. The calibration method suitable for the current source array in the multichannel sectional type current steering DAC can calibrate each current source at the low data bit segment of the sectional type current steering DAC, and thereby achieves high calibration accuracy, remedies deviation and a mismatch, among the current sources in the current source array of the sectional type current steering DAC, improves linearity of the single DAC, and then improves performance indexes such as the significant number of digits of the DAC and a spurious free dynamic range, and improves linear performance of the multichannel sectional type current steering DAC and amplitude consistency among all the channels.

The invention provides a high-voltage side gate drive circuit capable of resisting noise interference. The high-voltage side gate drive circuit comprises a high-voltage level shift circuit, a differential-mode noise elimination circuit, an RS trigger and an output drive level circuit, wherein a low-side pulse signal is converted into a high-voltage pulse signal for output through the high-voltage level shift circuit; a common mode noise elimination circuit is connected between the output of the high-voltage level shift circuit and the input of the differential-mode noise elimination circuit; the common mode noise elimination circuit is used for eliminating a common mode noise signal generated in application; and the differential-mode noise elimination circuit eliminates the differential-mode noise introduced by process variations, outputs a normal pulse signal, reduces the normal pulse signal into a normal square signal through the RS trigger, outputs the square signal from the output drive level circuit and drives an external high-side power tube.

The invention relates to a radar monitoring method and device for the long-term security risk of chemical equipment. The method comprises that real-time operation state data of the chemical equipment is obtained, the risk and operability of each system of the chemical equipment are analyzed, technical deviation is determined, and data to be monitored is screened from the real time state data; fault identification is carried out on the data to be monitored to obtain alarming information; and fault diagnosis and tracing are carried out on the alarming information to obtain the reason and corresponding remedial measures of the fault.

Annular and linear contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

The invention discloses a method for detecting a state of a capacitive touch key, compares a current count value of a counter with a baseline value, and judges whether the capacitive touch key is effectively touched by analyzing the variable quantity of the current count value relative to the baseline value and time of duration. In addition, when the variable quantity of the current count value relative to the baseline value is larger than a baseline variation threshold and is smaller than a key response threshold, the baseline value needs to be updated, i.e., by setting the baseline variation threshold and the key response threshold, that environment temperature variation influences the baseline value is reflected, thereby updating the baseline value when environment temperature varies, improving a capability of being resistant to interference of environment temperature, and improving detection precision. In addition, the baseline value is not a numerical value set in a unified manner, but varies at any time according to the environment temperature, and thus influence of technological deviations of different chips on detection of the state of the capacitive touch key is also eliminated.

The present invention relates to a programmable device-based convolutional neural network acceleration method and system. The method comprises: designing a basic structure of a convolution neural network on the programmable device, and establishing the quantification model of the computing resource and the frequency about the parallelization parameter respectively; under different parallelization parameters, exploring the highest reachable clock frequency of the actual voltage, temperature, process deviation, establishing an analysis model of the actual highest reachable frequency and the parallelization parameter; and taking throughput calculation as an optimization purpose, according to the established quantitative model and analysis model, carrying out problem abstract on the convolutional neural network design space exploration, and using a certain search algorithm to solve the parallelization parameters with optimal performance. According to the method and system provided by the present invention, the delay margin reserved by the commercial design tools for the voltage, the temperature and the process deviation can be used while ensuring the stability and reliability of the accelerator, so that the performance of the convolutional neural network accelerator can be further improved.

This invention relates to a mixed digital pulse modulator used in digital supply controllers composed of an adaptive offset voltage generation circuit, a 8-stage voltage-controlled loop oscillator and a digital control part, in which, the adaptive offset voltage generation circuit generates an offset voltage compensated by temperature technology to control the loop oscillator and a 16-phase clock C0-C15 not influenced by outside temperature or technical offset, and the digital control part generates a modulated pulse with the resolution of n-bit according to the clock staggered for 1/16 period orderly and n-bit duty ratio input from outside d[n-1 :0].

The invention belongs to the ultra-wideband communication technical field, and in particular relates to a pulse ultra-wideband transmitter with adjustable amplitude and spectrum. The transmitter is composed of four-stage modules which are sequentially connected together, wherein, the former two-stage modules generate pulse signals modulated by BPSK, an intermediate RLC frequency-selective network realizes adjustment of amplitude, length and spectrum of pulse, and finally the pulse is output by an ultra-wideband output buffer. The transmitter is modulated by adopting the BPSK, and an RLC network is taken as a core module of the whole system to realize adjustment of pulse parameters and compensation of process variation. By virtue of the characteristics of low duty cycle of an IR-UWB transmission signal, the output buffer is switched off in the case of no pulse to lower power consumption. The transmitter has the advantage of adjustable pulse parameters, thus meeting the requirements of UWB standards in different countries for spectrum and transmission power.

The invention discloses a method for reducing mask board splicing errors. According to the result of a graph formed by etching an exposed graph after repeated exposure on a splicing area of two adjacent mask boards, the structural compensation is carried on the exposed graph on the splicing area on the mask boards reversely. By utilizing the method, the distortion treatment to the exposed graph at the splicing area caused by repeated exposure and process deviation can be eliminated through compensation design of the mask boards, the consistency of an etched graph at the splicing area and an etched graph at a non-splicing area is ensured, and the yield of products is increased.