Programmable device-based convolutional neural network acceleration method and system

Abstract

The present invention relates to a programmable device-based convolutional neural network acceleration method and system. The method comprises: designing a basic structure of a convolution neural network on the programmable device, and establishing the quantification model of the computing resource and the frequency about the parallelization parameter respectively; under different parallelization parameters, exploring the highest reachable clock frequency of the actual voltage, temperature, process deviation, establishing an analysis model of the actual highest reachable frequency and the parallelization parameter; and taking throughput calculation as an optimization purpose, according to the established quantitative model and analysis model, carrying out problem abstract on the convolutional neural network design space exploration, and using a certain search algorithm to solve the parallelization parameters with optimal performance. According to the method and system provided by the present invention, the delay margin reserved by the commercial design tools for the voltage, the temperature and the process deviation can be used while ensuring the stability and reliability of the accelerator, so that the performance of the convolutional neural network accelerator can be further improved.

Description

technical field [0001] The present invention relates to the field of integrated circuits and the field of deep learning, in particular to a convolutional neural network acceleration method and system based on programmable devices. Background technique [0002] Convolutional neural network is a multi-layer perceptron with good fault tolerance, parallel processing ability and self-learning ability. It has good robustness and computational efficiency in dealing with graphics problems, especially in identifying displacement, scaling and other forms of distortion invariance, so it is widely used in deep learning as a benchmark neural network architecture. [0003] Field Programmable Gate Array (Field Programmable GateArray, FPGA) is a programmable device, which has the advantages of abundant computing resources, flexible reconfiguration, short development cycle and low power consumption. Compared with CPU (Central Processing Unit) and GPU (Graphics Processing Unit), Field Progra...

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However, this assumed situation often has a large deviation from the actual situation

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