70 results about "Logic optimization" patented technology

The invention discloses an intelligent reclosing circuit breaker modular protection system, which relates to the technical field of circuit breaker intelligent management, and comprises an acquisition module, a judgment module, a reclosing control module and an optimization module. Voltage holes caused by fault tripping and non-fault disturbance are effectively distinguished, and false triggering of reclosing operation is avoided; meanwhile, the optimization module introduces a machine learning algorithm to carry out continuous filing and strategy updating on misjudgment events, and self-adaptive discrimination logic optimization is realized, so that reclosing judgment accuracy and power supply stability of the power grid system under a complex load condition are remarkably improved, and system impact and equipment damage are effectively prevented.

The invention provides a circuit logic synthesis method for FPGA mapping based on reinforcement learning, and aims at solving the problem that in a traditional netlist optimization method, a circuit is not seen in model optimization, and the capacity is insufficient. The method comprises the following steps: firstly, constructing a logic comprehensive data set, and then preprocessing the data set to obtain statistical characteristics and a graph structure of a circuit; then, a logic comprehensive model based on reinforcement learning and aiming at FPGA mapping is constructed, pre-training is conducted through the preprocessed data set, and finally logic optimization is conducted on a circuit through the pre-trained logic comprehensive model based on reinforcement learning and aiming at FPGA mapping. According to the circuit feature extraction module, a GNN module is adopted to analyze a logic circuit and a netlist structure to obtain graph embedding, statistical features of the logic circuit and the netlist are analyzed through an FCN module, the features of the two parts are spliced to obtain an accurate enhanced representation state of the circuit, and the understanding capacity of a reinforcement learning model on different circuits is improved.

The embodiment of the invention discloses a terminal application behavior data analysis method and computer equipment, and the method comprises the steps: obtaining an interaction behavior data set of an RPA terminal application in a preset time window, the interaction behavior data set comprising a plurality of interaction behavior sequences, each interactive behavior sequence comprises at least one user interface operation event and a corresponding system response event; performing behavior track analysis processing on the interactive behavior data set, and extracting an interface circulation feature and an operation intention feature of each interactive behavior sequence; generating an interface optimization strategy according to the relevance between the interface circulation feature and the operation intention feature, wherein the interface optimization strategy comprises an interface layout adjustment rule and an interface response logic optimization rule; and feeding back the interface optimization strategy to a background management system of the RPA terminal application. Therefore, the problem that an existing RPA application interaction interface is insufficient in design and optimization can be effectively solved, and the usability of the interface and the response capability of the system are improved.

The invention provides a circuit logic optimization method based on predictive feedback. The method comprises the following steps: firstly, constructing a data set for logic synthesis, and taking the area and delay after circuit logic synthesis as labels of the data set; then preprocessing the data set to obtain an optimized sequence and graph features of the circuit; constructing a prediction model, and pre-training the prediction model by using the preprocessed data set; a logic optimization model is constructed, and the preprocessed data set is used for training; and finally, performing logic optimization on the circuit by using the trained logic optimization model. According to the method, a result is predicted through a prediction model composed of a GNN, an RNN and a decoder, features of the prediction result are extracted through Transform, and finally, a next optimization strategy is selected by using a multi-head near-end strategy based on reinforcement learning, so that an optimization sequence with the best area and delay is rapidly obtained.

The invention discloses an Alliance tool chain logic synthesis method based on multiple logic domains. The method comprises the following steps that an intermediate representation structure of a target circuit is obtained; mapping a Boolean expression in the intermediate representation structure into an XMG network equivalent to the logic function of the target circuit; logic optimization with the optimization logic hierarchy as the target is executed on the XMG network obtained through mapping; converting the XMG network after logic hierarchy optimization into an AIG network; logic optimization with optimization of the number of nodes as a target is executed on the AIG network obtained through conversion, and the optimized AIG network is output as an aig file; and reading the aig file, analyzing the aig file, outputting the analyzed aig file as a VHDL file, inputting the VHDL file to the Alliance tool chain, and generating a gate-level netlist corresponding to the optimized target circuit. According to the method, the logic optimization efficiency and expandability can be greatly improved, the performance bottleneck of an existing Alliance tool chain is effectively solved, and the large-scale circuit design processing capacity of the Alliance tool chain is remarkably improved.

According to the technical scheme, the large-scale logic optimization multiplier verification method is characterized in that a four-stage pipeline processing mode is adopted, the first stage is a partial adder tree recovery stage, and the second stage is a partial adder tree recovery stage; the second stage is an architecture generation stage; the third stage is a function verification stage; and the fourth stage is an equivalence checking stage. The verification capability is improved in a breakthrough manner and is far better than that of an existing method; the innovative three-stage decomposition strategy significantly reduces the calculation complexity, the ILP algorithm optimizes resource allocation, the multi-stage scheduling balances the calculation load, and the QACO algorithm efficiently explores the design space, so that the RefSCAT-2.0 framework provided by the invention becomes the most effective solution for verifying a large-scale logic optimization multiplier at present. From the perspective of practice, the technical blank of large-scale logic optimization multiplier verification is filled up, and important tool support is provided for reliability guarantee of key computing systems such as artificial intelligence chips, high-performance CPUs and GPUs.

The invention discloses a multi-round dialogue logic optimization method in an intelligent question answering system based on a knowledge graph, and belongs to the technical field of artificial intelligence and natural language processing, and the method comprises the following steps: S1, constructing and dynamically updating a triple knowledge graph; s2, based on a graph neural network and a graph attention mechanism, performing time sequence and emotion perception modeling on cross-round semantic association in the triple knowledge graph, and outputting a dialogue context vector; s3, inputting a dialogue context vector and a current user input feature into the generative model, performing semantic mapping through an independent intention, entity and behavior embedding encoder, and generating a robot behavior in combination with logic constraint and emotion-driven weight adjustment from a triple knowledge graph; s4, optimizing the generative model based on a task-associated adversarial training mechanism; and S5, carrying out multi-modal emotion fusion and consistency verification. According to the method, dynamic, coherent and emotional intelligent multi-round dialogue logic optimization can be realized.

Certain aspects of the present disclosure are directed towards techniques for power management. The techniques provide an optimal staggering delay time between transmission of enable signals to power switches coupled (e.g., electrically coupled) to logic circuits and a power source. The optimal staggering delay time may allow enabling or turning on of the power switches in a staggered, sequential fashion while reducing power up latency of the logic circuits.

The invention discloses a data processing method and device based on minimum instruction mapping, equipment and a medium, and relates to the technical field of data processing and control. The method comprises the following steps: firstly, acquiring a control instruction of a sending end, then performing instruction analysis on the control instruction to obtain a minimum instruction set, and mapping the minimum instruction set to a physical position node of a parallel processing module to obtain a mapping result. Wherein the physical location node comprises a plurality of parallel nodes, different states of the parallel nodes represent different data codes, the states comprise a power-on state and a power-off state, and the states of the plurality of parallel nodes form a mapping result. And finally, transmitting a mapping result to a receiving end to execute the control instruction. On the premise of not depending on a complex decoding mechanism, a simplified instruction expression mode is adopted, an external input signal is mapped to the parallel processing module in a shortest path, instant response and state feedback are achieved, and the method is particularly suitable for scenes of simplifying control logic, optimizing a signal processing path and improving execution efficiency.

The application provides a method for generative heterogeneous logic optimization based on critical path partitioning. The method includes: converting a digital logic circuit into an And-Inverter Graph (AIG) format; partitioning the AIG using reinforcement learning based on critical path information of the circuit to obtain critical-path-aware partitions so as to reduce influence of critical path changes brought by the partitioning on timing performance; respectively and automatically exploring an optimized structure and synthesis flow suitable for each partition using the reinforcement learning method; selecting optimization operators for various structures using a reinforcement learning agent guided by area-delay metrics and optimizing each partition; and merging the optimized partitions in the AIG format. In the application, the digital logic circuit is partitioned based on critical paths, and reinforcement learning is used to explore and optimize structures and strategies based on area and delay.

The invention relates to the technical field of integrated circuits, in particular to a multiplexer logic optimization method, electronic equipment and a medium, and the method comprises the steps: C1, obtaining a selection signal set corresponding to a multiplexer to be optimized; c2, optimizing a selection signal; c3, acquiring a data signal set corresponding to the multiplexer to be optimized; c4, if all the data signals are driven by constant, or all the data signals are unsteady signals, or all the data signals are connected to the same signal source, the logic optimization process is ended, and otherwise, the step C5 is executed; step C5, decomposing the multiplexer to be optimized to generate a multiplexer tree, wherein each node of the multiplexer tree corresponds to one multiplexer; and C6, generating an optimized multiplexer based on the multiplexer tree. According to the invention, the logic optimization degree and optimization efficiency of the multiplexer are improved. According to the invention, the logic optimization degree and optimization efficiency of the multiplexer are improved.

The application discloses a kind of excitation regulator system grid-connected logic determination method, it is related to generator set excitation control and power system grid-connected control technical field, wherein the method includes: real-time acquisition includes three kinds of core signals of grid-connected switch combination signal, generator stator current signal, generator terminal voltage signal, and the three kinds of core signals collected are preprocessed;According to the operating characteristics of unit and test demand, set grid-connected state determination criterion parameter;Grid-connected state logic determination is executed to different scene;Based on the result of grid-connected state logic determination, logic optimization and abnormal alarm detection are carried out.The application uses the double core criterion of "combination signal + stator current", effectively resists the signal anomaly caused by contact jitter and loop looseness, avoids the no-load misjudgment when running with load, reduces the risk of reactive power fluctuation and protection misoperation.

The application discloses a flood scheduling gate operation logic anti-misoperation method and device based on rule self-learning, and particularly relates to the technical field of gate scheduling control systems. Trend results are generated by differentially determining the signs of the inflow and reservoir water level, consistency checking is performed in combination with the discharge variation direction and gate opening instruction to form an effective instruction sequence; the residual space amount of the downstream sensitive area is calculated, and the channel impact coefficient is generated in combination with the discharge impact amount and channel conditions; on this basis, the over-limit channel flow is reduced and distributed to the normal channel to form a rechecked sharing result. The application can realize trend dynamic judgment and instruction direction matching, guarantee discharge adjustment and hydrological condition consistency, and through the closed logic of reduction and distribution, the multi-channel flow sharing structure is optimized, the gate adjustment sequence logic is set according to the gate operation principle of the power station design, automatic matching of the discharge and gate adjustment is realized, and the situation of lower gate operation order is prevented.

The invention discloses an intelligent writing auxiliary method and system based on a knowledge graph. The intelligent writing auxiliary method comprises the following steps: S1, acquiring multi-modal original data in a writing scene and preprocessing the multi-modal original data; s2, constructing a cross-domain knowledge graph based on the preprocessed multi-modal data, wherein the knowledge graph comprises an entity layer, a relation layer and a multi-modal attribute layer; the invention relates to the technical field of intelligent writing assistance. According to the intelligent writing auxiliary method and system based on the knowledge graph, unified feature extraction and normalization processing are performed on multi-modal data such as texts, images, videos and audios, so that the system can effectively extract valuable information from different data sources, the knowledge depth and breadth of the writing auxiliary system are enhanced, and the writing auxiliary system is more intelligent. According to the comprehensive scores of the writing targets and the candidate entities, the system can generate multi-dimensional structured writing prompts, including content supplementation, logic optimization, innovation and the like, so that a user is helped to improve the writing quality from multiple angles.

The embodiment of the invention provides a hierarchical intelligent calculation power supply system, a model generation method, equipment and a medium, and the system comprises a model algorithm design module which is used for generating a target logic model according to the model demands of a user; the training simulation and verification module is used for generating a target model and a virtual resource demand of the target model based on the target logic module; and the computing power base layout module is used for carrying out resource scheduling on the target model according to the virtual resource demand. Through the embodiment of the invention, the logic optimization and deployment optimization work of the large model can be decoupled, the cross-platform portability of the user logic model is ensured, the service iteration upgrading speed is accelerated, the computing power supply quality of the intelligent computing cloud platform is improved, and the intelligent computing service experience of the user in a large model scene is improved.

This invention presents a power system risk assessment and reactive power optimization method and system based on Inductively Coupled Logic Optimization (IGDT). It establishes a deterministic reactive power optimization model with the objective of minimizing the linear weighted average of system network losses, voltage deviations, and operating costs, and solves this model to obtain a baseline optimal solution. For the uncertainty of renewable energy output and load power, IGDT is used for modeling, constructing a robust optimization model with the objective of maximizing the range of uncertainty fluctuations. Finally, the optimal solution is obtained by iteratively solving the IGDT robust optimization model using a bisection method. This invention effectively quantifies the voltage exceedance risk immunity level and system performance, providing dispatchers with clear and quantitative decision-making basis. It eliminates the need to rely on the probability distribution of uncertain variables, significantly reducing computational complexity. Simultaneously, it considers system economy and security, improves the robustness and flexibility of grid operation under high-proportion renewable energy integration, provides an optimal dispatch strategy to minimize risks, and achieves optimized operation under controllable risks.

The invention relates to the technical field of traffic early warning, in particular to a vehicle meeting early warning system for a mountain construction road. Comprising a vehicle meeting judgment module, a rule dynamic configuration module, a positioning module, an interaction module, an early warning module, a risk control module and a logic optimization module. Wherein the meeting judgment module is used for dynamically analyzing and predicting the meeting time and sequence of vehicles; the rule dynamic configuration module is used for flexibly configuring the way-giving logic of the meeting point according to different road section characteristics of the mountainous area construction road; the risk control module is used for analyzing the running time and track of the mine car, planning a reasonable route, managing and controlling the transport capacity state in real time and extracting experience afterwards for improvement; the logic optimization module is used for defining vehicle meeting logics in different scenes, through the above mode, intelligent, precise and safe management of vehicle meeting of mountain construction roads is achieved, the problem that traditional vehicle meeting depends on subjective judgment is solved, the system can adapt to a complex road environment, and vehicle meeting decision scientificity is improved.

The present technology includes performance-driven logic optimization for logic synthesis. A ground-truth dataset is generated based on technology mapping and static timing analysis of a set of gate-level netlists generated from a set of And-Inverter Graphs (AIGs). The ground-truth dataset is used to train a machine learning (ML) model to predict area and delay metrics. The trained ML model is used to predicted area and delay metrics for each AIG in another set of AIGs. A reward is calculated for each AIG in the other set of AIGs based on the predicted area and delay metrics. An AIG in the other set of AIGs having a smallest reward is selected as an optimal AIG. Technology mapping is performed on the optimal AIG to generate another gate-level netlist for use in one or more physical integrated circuit design processes.

The application discloses a high-speed spectral confocal signal processing system and method based on Zynq, which comprises the following steps: 1, collecting original linear array spectral images through a parallel multi-path source synchronous interface and decoding and receiving; 2, loading a pre-calibration dark signal to a hardware cache through a soft and hard collaborative mechanism to perform pixel-by-pixel operation to subtract the dark signal in real time; 3, extracting and counting electrical black reference pixel values in real time, and dynamically correcting the electronic background noise; 4, adopting a Savitzky-Golay filter with fixed-point solidification and logic optimization, random noise is smoothed under the premise of retaining spectral peak characteristics; 5, a sub-pixel peak searching method is deployed in hardware, which is a low-delay and high-precision sub-pixel peak searching method realized through dynamic adjustment of a local peak searching interval by cross-frame threshold prediction, based on first-order central difference and weighted linear fitting. According to the characteristics of high-speed spectral confocal measurement, the application efficiently adapts programmable logic resources, realizes pipeline processing in a soft and hard collaborative manner, and can meet the requirements of high-speed and high-precision and low-cost industrial measurement.

The invention discloses a multi-FPGA system circuit division-oriented rapid logic equivalence verification method, which comprises the following steps of: carrying out logic optimization on an original design to obtain a to-be-verified optimization design, and dividing the original design by utilizing a division tool to obtain a to-be-verified division design; performing logic equivalence verification on the to-be-verified optimization design and the original design to obtain a first verification result; when the first verification result is that the logic functions of the to-be-verified optimization design and the original design are consistent, black box module processing is carried out on modules which are not involved in the original design and the to-be-verified division design based on the division boundary information, and logic equivalence verification is carried out on the processed original design and the to-be-verified division design to obtain a second verification result; and when the second verification result is that the logic functions of the original design processed by the black box module and the to-be-verified division design are consistent, mapping the to-be-verified division design to a plurality of independent FPGAs. According to the invention, efficient verification of multi-FPGA system circuit division is realized.

The application discloses a multi-round dialogue logic optimization method in an intelligent question-answering system based on a knowledge graph, and belongs to the technical field of artificial intelligence and natural language processing, and comprises the following steps: S1, constructing and dynamically updating a triple knowledge graph; S2, based on a graph neural network and a graph attention mechanism, modeling time sequence and emotion perception of cross-round semantic association in the triple knowledge graph, and outputting a dialogue context vector; S3, inputting the dialogue context vector and current user input features into a generation model, performing semantic mapping through an independent intent, entity and behavior embedding encoder, and combining logical constraints and emotion-driven weight adjustment from the triple knowledge graph to generate a robot behavior; S4, optimizing the generation model based on a task-related adversarial training mechanism; and S5, performing multi-modal emotion fusion and consistency verification.The application can realize dynamic, coherent and emotion-intelligent multi-round dialogue logic optimization.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

This invention discloses a method for input independence analysis of large-scale digital circuits based on BDD. The method converts the circuit Verilog file into a NAND graph (AIG) and performs logic optimization to extract the sets of input and output variables. It then converts the AIG network into a global BDD representation and reduces the number of nodes. A multivariate product term cube is constructed with respect to input groups S and X. The Boolean derivative of Di with respect to each input variable in input group S is calculated, and the result is logically ORed to obtain the synthesis sensitivity function diff_or_i. The method then performs the logical inverse operation and full quantization, extracts the specific logical assignment vector of input group L, and determines the independence of Di with respect to input group S. This method avoids the computational bottleneck of exponential complexity and still possesses good computational performance and scalability in large-scale digital circuits. Its independence determination results are unique and reliable, and it can be widely applied in scenarios such as logic synthesis, formal verification, security and testability analysis.

The invention discloses a large-scale digital circuit input independence analysis method based on BDD, and the method comprises the steps: converting a circuit Verilog file into a NAND graph AIG, carrying out the logic optimization, and extracting an input and output variable set; converting the AIG network into global BDD representation and reducing the number of nodes; constructing a multivariable product term cube about the input groups S and X; and calculating Boolean differential of the Di about each input variable in the input group S, carrying out logic OR operation on the result to obtain a comprehensive sensitivity function diffori, taking logic inverse operation and executing full-scale quantization, extracting a specific logic assignment vector of the input group L, and judging the independence of the Di about the input group S. The method avoids the operation bottleneck of exponential complexity, and still has good calculation performance and expandability in a large-scale digital circuit; the independence judgment result is unique and reliable, and the method can be widely applied to scenes such as logic synthesis, form verification, safety and testability analysis and the like.

This invention provides a method for constructing a logic optimization generation system based on reinforcement learning. The method includes: step S1, obtaining a training dataset; step S2, constructing an initial generation model, which includes a graph encoder, an average pooling layer, a word segmenter, and a sequence decoder; step S3, using the training dataset to iteratively train the initial generation model multiple times until convergence; step S4, using the converged initial generation model as a reference network and initializing a policy network and a value network, and using a reinforcement learning mechanism with human feedback to fine-tune the policy network and the value network, and using the fine-tuned policy network as a logic optimization generation system. The fine-tuning process includes multiple rounds of iterative optimization. In each round of iterative optimization, the graph structure representation of the logic circuit in the training dataset is used as the initial state input reference network, the policy network optimized in the previous round, and the value network to perform multiple interactions.

The circuit generation method comprises the steps that function description information of a circuit is acquired, and the function description information comprises input and output information of the circuit; according to the function description information, matching structure parameters of the circuit generation network to determine the circuit generation network; the functional description information is input into the circuit generation network to generate a circuit. In the application, the final circuit is generated according to the circuit generation network. Furthermore, before the circuit generation network generates the circuit, the circuit generation network is determined according to the function description information and the structure parameters of the matching circuit generation network, so that the matching degree of the structure parameters of the circuit generation network and the function description information of the circuit is higher, the redundant nodes of the generated circuit are lower, and the generated circuit is more accurate; the logic circuit accords with the logic function and is excellent, the logic optimization effect is improved, and the pressure during logic optimization of the circuit is reduced.

The invention provides a matmul data reading logic optimization method based on simd (simd), which comprises the following steps of: S1, storing four rows of data in a feature1 in an I1 register, an I2 register, an I3 register and an I4 register so as to prepare for subsequent splicing operation; an mx512lao instruction is used for each row of the feature 1, and 256-bit data of each row are sequentially stored in a register I1, a register I2, a register I3 and a register I4; s2, splicing the data a and a1 of the register l1 and the data c and c1 of the register l3 into one register, splicing the data a2 and a3 of the I1 and the data c2 and c3 of the I3, and splicing the data of the registers I2 and I4 in the same way; two ilveq instructions and two ilvoq instructions are used for storing data of the four registers I1, I2, I3 and I4 into registers J1, J2, J3 and J4; s3, continuing to splice the data a and c in the register J1 with the data b and d in the register J3, splicing the data a1 and c1 in the register J1 with the data b1 and d1 in the register J3, and similarly splicing the register J2 and the register J4; and storing the data of the four registers J1, J2, J3 and J4 into the registers B1, B2, B3 and B4 by using two ilded instructions and two ilvod instructions. According to the method, the number of used simd instructions is reduced, and the speed is higher; and the time optimization efficiency is high.

The invention relates to the technical field of natural language processing and knowledge graph, in particular to a major language model and knowledge graph fused professional question-answering system and a construction method, and the system comprises a knowledge graph construction system and an LLM question-answering system. The knowledge graph construction system comprises a knowledge graph construction module, a JSON data import module and a cell tree import module. The LLM question-answering system comprises a question-answering module, a vector similarity calculation module, an intention recognition module, a named entity recognition module and a retrieval enhancement generation module. According to the method, the LLM and the knowledge graph are directly integrated through the bottom layer code, the embedding process of the knowledge graph and the large language model is simplified fundamentally, and the deep customization requirement of the system architecture level is reduced; modules capable of automatically processing a data interface, inquiring logic optimization and responding time control are designed in the integration process, so that developers can realize highly cooperative work of the LLM and the knowledge graph only through simple configuration during later use, and heavy system reconstruction or customized development is not needed.

The embodiment of the invention relates to the technical field of Internet, and discloses a spin lock design method and device, electronic equipment and a storage medium. According to the embodiment of the invention, at least the problems that the stability of write operation is poor, a timeout mechanism is not set, too long waiting is possibly caused, and the response speed of the system is influenced in an existing CP AUTOSAR OS system can be relieved; by adding the first preset parameter to check and judge whether the spin lock is configured with a lock method related to interruption or not, check whether lock obtaining is overtime or not, read and judge whether the state variable of the spin lock is an even number or not, and other design logics, the process of obtaining the lock through write operation is optimized, the stability of system write operation is improved, and the system response speed is increased.

The application discloses a V94.2 type gas turbine starting blow-off optimization method and system, and the system comprises a combustible gas detection preprocessing cabinet arranged at an exhaust diffusion section and a chimney inlet, wherein a pneumatic pump, a gas analysis instrument, a cooling device and the like are integrated in the cabinet, sampling and analysis are controlled through a TCS system, and combustible gas concentration (LEL) is monitored in real time. The method comprises the following steps: dynamically determining a blow-off time, establishing a blow-off time model based on multiple variables such as load, shutdown time length, flame signal disappearance event and combustible gas concentration threshold, and optimizing the blow-off time length by comparing the actual measured concentration with a safety threshold (25% LEL). Through hardware modification and logic optimization, the application reduces energy waste caused by fixed blow-off time, improves the starting efficiency of the gas turbine, and reduces the risk of deflagration.