10 results about "High speed serial link" patented technology

The application relates to the technical field of electronic information and machine vision, in particular to a real-time visual imaging device and method based on FPGA, which comprises a CMOS image sensor, a FPGA main controller, a display output interface circuit and a clock synchronization circuit. The CMOS image sensor is used for outputting original image data to the FPGA main controller through a high-speed serial link. The FPGA main controller is used for performing receiving analysis and pixel recombination on the original image data to obtain a display pixel stream. The display output interface circuit is used for generating an HDMI display signal according to the display pixel stream and outputting the HDMI display signal to a display device. The clock synchronization circuit is used for synchronizing at least three paths of clocks, so that collection, processing and output are in a homologous clock system. The implementation complexity and potential hidden dangers caused by cross-clock domain processing are significantly reduced.

The invention provides a remote upgrading system, method and device for a multi-FPGA device and a medium, and the remote upgrading system comprises a digital signal processor which is used for processing an upgrading mirror image file of a slave device to generate a data packet, verifying a state feedback signal sent by a master control FPGA, and sending the data packet to the master control FPGA after the verification is passed; and the master control FPGA is used for sending the data packet to the corresponding slave device through the high-speed serial link for upgrading processing, executing byte alignment processing, bit alignment processing and phase adjustment processing to complete recovery of the high-speed serial link when detecting that the high-speed serial link is abnormal, and resending state feedback information to the digital signal processor, and the digital signal processor continues to send subsequent data packets according to the wrong data packet serial number until the transmission of the upgrade mirror image file is completed. The self-adaptive synchronization problem of the high-speed serial link is solved, and the upgrading efficiency of the multiple slave devices is improved.

The invention discloses a receiving end equalization circuit applied to a SerDes communication system, and belongs to the field of integrated circuits and communication. The circuit comprises a CTLE equalizer and a variable gain amplifier VGA which are cascaded, wherein the output end of the CTLE equalizer is connected with the input end of the VGA; wherein the CTLE equalizer adopts a source follower, an active inductor and a negative capacitor structure, so that the power consumption is effectively reduced, the output common-mode level is matched, and the bandwidth is expanded; and the VGA adopts a transconductance enhancement structure and a source follower, so that the transconductance is improved, the output impedance is reduced, the linearity is enhanced, and the flexible control of low-frequency gain is realized. Compared with a traditional equalization circuit, on the premise that the structure is simpler and easy to implement, lower power consumption and smaller area are achieved, meanwhile, the system transmission rate is remarkably increased, the better equalization effect and good stability are shown, and an efficient and reliable solution is provided for solving the signal equalization problem of a SerDes high-speed serial link.

A link negotiation system includes a second device that determines a link configuration policy based on a status of a receiver of an interface of the second device, where the link configuration policy indicates an association relationship between a unidirectional logical lane and a unidirectional physical lane in a high-speed serial link between a first device and the second device, the unidirectional logical lane is a logical lane from the first device to the second device in the high-speed serial link, and the unidirectional physical lane is a physical lane from the first device to the second device in the high-speed serial link; and sends the link configuration policy to the first device.

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

This invention relates to the field of protocol conversion and transmission technology, specifically an FPGA-based AFDX to Aurora protocol transmission and conversion system. The system includes: an AXI-AFDX module responsible for parsing and encapsulating standard AFDX frame signals, and separating AFDX control signals from data signals; an AFDX over Aurora module that achieves cross-clock domain synchronization by storing control and data signals separately in dual FIFOs, extracting frame groups in an orderly manner based on virtual link static priority scheduling and same-priority polling mechanisms, and encapsulating them into IP frame format with extended fields to ensure that critical AFDX control information is not lost during Aurora transmission; and an Aurora protocol module that performs bidirectional conversion between IP frame signals and Aurora protocol high-speed serial signals, adapting to external GT high-speed interfaces. This invention achieves reliable transmission to high-speed serial links.

This invention discloses a low-latency data exchange method and related apparatus for real-time simulation systems, belonging to the field of data exchange technology. The method includes: initializing the real-time simulation system, which includes simulation nodes, exchange nodes, and a master control node; the simulation nodes construct dynamically long data packets based on the simulation results to be exchanged and send the dynamically long data packets via a high-speed serial link; the exchange nodes receive the dynamically long data packets and, based on the system-level physical topology, forward the dynamically long data packets using a small packet fast transmission mechanism and a bufferless direct-pass transmission mechanism; the target simulation node receives the dynamically long data packets and performs deterministic parsing on them. This method and related apparatus can reduce the latency of data exchange in real-time simulation systems and ensure the determinism of data transmission.

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

The invention relates to the technical field of electronic information and machine vision, in particular to a real-time vision imaging device and method based on an FPGA, and the device comprises a CMOS image sensor which is used for outputting original image data to an FPGA main controller through a high-speed serial link; the FPGA main controller is used for performing receiving analysis and pixel recombination on the original image data to obtain a display pixel flow; the display output interface circuit is used for generating an HDMI display signal according to the display pixel flow and outputting the HDMI display signal to display equipment; and the clock synchronization circuit is used for at least three paths of synchronous clocks, so that acquisition, processing and output are in a homologous clock system. And the implementation complexity and potential hazards caused by cross-clock domain processing are obviously reduced.

A first device includes training logic configured to autonomously train a link coupled between the first device and a second device without software intervention. The training logic transmits a message on a first portion of the link to the second device, the message associated with training a second portion of the link. The training logic receives training data on the second portion of the link from the second device in response to the message and trains the second portion of the link based on the training data. In some embodiments, a first device includes processing circuitry and a serializer / deserializer, wherein the processing circuitry trains a high-speed serial link in a first direction between the first device and a second device, and sends or receives a first sideband message on the high-speed serial link in a second direction that is opposite to the first direction.