Remote upgrading system, method and equipment for multi-FPGA (Field Programmable Gate Array) equipment and medium

Abstract

The invention provides a remote upgrading system, method and device for a multi-FPGA device and a medium, and the remote upgrading system comprises a digital signal processor which is used for processing an upgrading mirror image file of a slave device to generate a data packet, verifying a state feedback signal sent by a master control FPGA, and sending the data packet to the master control FPGA after the verification is passed; and the master control FPGA is used for sending the data packet to the corresponding slave device through the high-speed serial link for upgrading processing, executing byte alignment processing, bit alignment processing and phase adjustment processing to complete recovery of the high-speed serial link when detecting that the high-speed serial link is abnormal, and resending state feedback information to the digital signal processor, and the digital signal processor continues to send subsequent data packets according to the wrong data packet serial number until the transmission of the upgrade mirror image file is completed. The self-adaptive synchronization problem of the high-speed serial link is solved, and the upgrading efficiency of the multiple slave devices is improved.

Description

Technical Field

[0001] This application relates to the field of remote upgrade technology for semiconductor devices, and in particular to remote upgrade systems, methods, devices and media for multiple FPGA devices. Background Technology

[0002] With the rapid development of semiconductor manufacturing equipment towards higher integration and multi-functionality, the remote upgrade capability of the internal firmware has become one of the key functions to ensure system maintainability and continuous iteration. In modern semiconductor-specific equipment, Field-Programmable Gate Arrays (FPGAs), as core signal processing units, are widely used in key modules such as timing control, data acquisition, and high-speed communication. The integrity and upgrade reliability of their configuration firmware directly affect the overall operational stability of the machine. Currently, common FPGA remote upgrade solutions typically involve a host computer transmitting a firmware image to an embedded main processor (such as a Digital Signal Processor (DSP)) via Ethernet, USB, or a serial interface. The DSP then forwards the data to the main control FPGA chip via a parallel bus interface (such as an EMIF). The main control FPGA further cascades the data to downstream slave FPGA chips via a high-speed serial link (such as a high-speed serial link), and finally writes it into the configuration flash to complete the upgrade.

[0003] However, the aforementioned traditional solutions have several serious drawbacks: 1. Lack of cross-level flow control mechanisms: The DSP and the main control FPGA often adopt a stateless "data pumping" mode, meaning the DSP continuously sends data without being aware of the downstream link status. When the downstream high-speed serial link is interrupted or its speed decreases due to electromagnetic interference, loose connections, or temperature drift, the main control FPGA's receive buffer overflows rapidly, leading to data loss or even EMIF interface lockup, causing the entire upgrade process to fail. 2. Link recovery relies on manual intervention: Once the high-speed serial link is disconnected, the existing system does not have automatic reconnection capabilities. Operators must manually reset each level of equipment and restart the upgrade process, severely impacting equipment availability and making it difficult to meet the maintenance needs of continuous production environments. 3. Difficult fault location: After an upgrade failure, engineers need to use a logic analyzer to capture signals from each node of the PC→DSP→EMIF→high-speed serial link, which is time-consuming, technically challenging, and greatly increases maintenance costs. Therefore, there is an urgent need for an FPGA remote upgrade system that can achieve reliable end-to-end transmission in a multi-device cascaded system and has adaptive synchronization and automatic recovery capabilities, in order to solve the problems of poor reliability, weak fault tolerance and low maintenance efficiency in the existing technology. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a remote upgrade system, method, device and medium for multiple FPGA devices, which solves the adaptive synchronization problem of high-speed serial links, and establishes a data interaction response mechanism between chips at each level, enabling digital signal processors to sense the status of downstream links and intelligently mobilize data, thereby achieving fully automatic fault-tolerant recovery at the system level and improving the upgrade efficiency of multiple slave FPGA devices.

[0005] This application provides a remote upgrade system for multiple FPGA devices. The remote upgrade system includes a host computer, a digital signal processor, and a main control FPGA. Both the host computer and the main control FPGA are communicatively connected to the digital signal processor. The digital signal processor is used to receive upgrade image files of at least one slave FPGA device sent by the host computer, preprocess the upgrade image files to generate data packets, verify the status feedback signals sent by the master FPGA, and send the data packets to the master FPGA after the verification is successful. The master FPGA is used to buffer the data packets and send them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link. When an abnormality is detected in the high-speed serial link, byte alignment, bit alignment and phase adjustment are performed to complete the reconnection of the high-speed serial link. Status feedback information is resent to the digital signal processor so that the digital signal processor can continue to send subsequent data packets according to the sequence number of the erroneous data packets until the upgrade image file transmission is completed.

[0006] In one possible implementation, when the digital signal processor is used to verify the status feedback signal sent by the main control FPGA, the digital signal processor is specifically used for: Detect whether a ready state exists in the received status feedback signal; If so, proceed with the verification and send the next data packet; If not, then pause data packet transmission and wait for each level of the status feedback signal to be ready, and then initiate breakpoint resumption based on the error packet sequence number; wherein, the status feedback signal includes ready status, link status, buffer status, flash status, verification status and error packet sequence number.

[0007] In one possible implementation, the main control FPGA is further used for: When consecutive invalid codewords or IDLE code loss are detected, the system switches from the connected state to the reconnected state and returns to the linked state after the high-speed serial link is automatically restored.

[0008] In one possible implementation, when the main control FPGA performs byte alignment, bit alignment, and phase adjustment to reconnect the high-speed serial link upon detecting an anomaly, the main control FPGA is specifically used for: The start code is searched in the data stream of the high-speed serial link to determine the data byte boundaries in order to achieve the byte alignment process; The sampling point position is fine-tuned by adjusting the BitSlip port of the ISeDes module until the IDLE code is stably decoded to achieve bit alignment. The sampling clock phase is dynamically adjusted to find the optimal sampling position to achieve the phase adjustment process.

[0009] In one possible implementation, when the main control FPGA is used to find the optimal sampling position for dynamically adjusting the sampling clock phase to achieve the phase adjustment process, the main control FPGA is specifically used for: The input signal phase is sequentially delayed by a preset number of signal periods to determine the maximum and minimum phase delay values ​​for successful bit alignment. The average of the maximum phase delay value and the minimum phase delay value is used as the fixed phase delay.

[0010] In one possible implementation, when the digital signal processor is used to preprocess the upgraded image file to generate a data packet, the digital signal processor is specifically used to: The upgrade image file is encapsulated based on the instruction bit, the data packet sequence number bit, and the data area to determine the data packet; wherein, the instruction bit is used to indicate the operation type, the data packet sequence number bit is the sequence number of the current data packet, and the data area is a block of data that carries 24-bit aligned data.

[0011] This application embodiment also provides a remote upgrade method for multiple FPGA devices, the remote upgrade method comprising: The control digital signal processor receives upgrade image files of at least one slave FPGA device sent by the host computer, preprocesses the upgrade image files to generate data packets, verifies the status feedback signals sent by the master FPGA, and sends the data packets to the master FPGA after the verification is successful. The master FPGA is controlled to buffer the data packets and send them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link; When the main control FPGA detects an anomaly in the high-speed serial link, it performs byte alignment, bit alignment, and phase adjustment to reconnect the high-speed serial link. It then resends status feedback information to the digital signal processor so that the digital signal processor can continue sending subsequent data packets based on the erroneous data packet sequence number until the upgrade image file transfer is complete.

[0012] This application also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the remote upgrade method for multiple FPGA devices described above are performed.

[0013] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the remote upgrade method for multiple FPGA devices described above.

[0014] This application provides a remote upgrade system, method, device, and medium for multiple FPGA devices. The remote upgrade system includes a host computer, a digital signal processor (DSP), and a master FPGA. Both the host computer and the master FPGA are communicatively connected to the DSP. The DSP receives upgrade image files from at least one slave FPGA device sent by the host computer, preprocesses the upgrade image files to generate data packets, verifies the status feedback signal sent by the master FPGA, and sends the data packets to the master FPGA after successful verification. The master FPGA buffers the data packets and sends them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link. When an abnormality is detected in the high-speed serial link, byte alignment, bit alignment, and phase adjustment are performed to reconnect the high-speed serial link. The master FPGA then resends the status feedback information to the DSP so that the DSP continues to send subsequent data packets starting from the erroneous data packet sequence number until the upgrade image file transmission is complete. It solves the adaptive synchronization problem of high-speed serial links, and establishes a data interaction response mechanism between chips at each level, enabling digital signal processors to sense the status of downstream links and intelligently allocate data, thereby achieving fully automatic fault-tolerant recovery at the system level and improving the upgrade efficiency of multi-slave FPGA devices.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a remote upgrade system for multiple FPGA devices provided in an embodiment of this application; Figure 2 A flowchart illustrating the reconnection mechanism for a high-speed serial link provided in an embodiment of this application; Figure 3 A flowchart illustrating a remote upgrade method for multiple FPGA devices provided in this application embodiment; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0018] Icons: 100 - Remote upgrade system for multiple FPGA devices; 110 - Host computer; 120 - Digital signal processor; 130 - Main FPGA; 140 - Slave FPGA; 400 - Electronic device; 410 - Processor; 420 - Memory; 430 - Bus. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0020] First, the applicable application scenarios of this application will be introduced. This application can be applied to the field of remote upgrade technology for semiconductor equipment.

[0021] Research revealed several serious flaws in traditional solutions: 1. Lack of cross-level flow control mechanisms: The DSP and main control FPGA often employ a stateless "data pumping" mode, meaning the DSP continuously sends data without sensing the downstream link status. When the downstream high-speed serial link is interrupted or its speed decreases due to electromagnetic interference, loose connections, or temperature drift, the main control FPGA's receive buffer overflows rapidly, leading to data loss or even EMIF interface lockup, causing the entire upgrade process to fail. 2. Link recovery relies on manual intervention: Once the high-speed serial link is disconnected, the existing system lacks automatic reconnection capabilities. Operators must manually reset each level of equipment and restart the upgrade process, severely impacting equipment availability and failing to meet maintenance requirements in continuous production environments. 3. Difficult fault location: After an upgrade failure, engineers need to use a logic analyzer to capture signals from each node of the PC→DSP→EMIF→high-speed serial link, a time-consuming and technically demanding process that significantly increases maintenance costs. Therefore, there is an urgent need for an FPGA remote upgrade system that can achieve reliable end-to-end transmission in a multi-device cascaded system and has adaptive synchronization and automatic recovery capabilities, in order to solve the problems of poor reliability, weak fault tolerance and low maintenance efficiency in the existing technology.

[0022] Based on this, the embodiments of this application provide a remote upgrade system for multiple FPGA devices, which solves the adaptive synchronization problem of high-speed serial links, and there is a data interaction response mechanism between chips at each level, enabling digital signal processors to sense the status of downstream links and intelligently mobilize data, thereby realizing fully automatic fault-tolerant recovery at the system level and improving the upgrade efficiency of multiple slave FPGA devices.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a remote upgrade system 100 for multiple FPGA devices provided in an embodiment of this application. Figure 1 As shown in the figure, the remote upgrade system 100 for multiple FPGA devices provided in this application embodiment includes a host computer 110, a digital signal processor 120 and a main control FPGA 130, and the host computer 110 and the main control FPGA 130 are both communicatively connected to the digital signal processor 120.

[0024] Specifically, the digital signal processor 120 is used to receive upgrade image files of at least one slave FPGA 140 device sent by the host computer 110, preprocess the upgrade image file to generate data packets, verify the status feedback signal sent by the master FPGA 130, and send the data packets to the master FPGA 130 after successful verification. The master FPGA 130 is used to buffer the data packets and send them to the corresponding slave FPGA 140 device for upgrade processing via a high-speed serial link. When an abnormality is detected in the high-speed serial link, byte alignment processing, bit alignment processing, and phase adjustment processing are performed to complete the reconnection of the high-speed serial link. The status feedback information is resent to the digital signal processor 120 so that the digital signal processor 120 continues to send subsequent data packets according to the sequence number of the erroneous data packets until the upgrade image file transmission is completed.

[0025] It should be noted that the Digital Signal Processor (DSP) 120 processes data according to the EMIF firmware file transfer protocol and the EMIF interface's data flow control mechanism. The EMIF transfer protocol consists of instruction bits (bits 1-4), data packet sequence number bits (bits 5-8), and a data area (bits 9-32). When the DSP sends data packets to the main control FPGA 130 via the EMIF interface, it encapsulates the data according to the above protocol. The instruction bits inform the main control FPGA 130 of the operation to be performed on the current data packet, such as 0xD for writing EMIF data to the buffer and 0xE for clearing the buffer. The data packet sequence number bits indicate which data packet is being sent (modulo 16 to save bit width). The DSP splits the upgrade image file into 24-bit aligned data blocks and stores them in the data area specified in the protocol.

[0026] Here, before sending each data packet, the DSP will detect the status feedback signal sent by the main control FPGA130 through the GPIO bus. The status feedback signal includes the following information: "ready", "link status (high-speed serial link state)", "buffer state", "flash state", "parity state", and error number (errpkgNum).

[0027] The main control FPGA130 implements the bridging function from the EMIF interface to the high-speed serial link, including clock domain conversion and data buffering. The main control FPGA130 integrates the aforementioned adaptive synchronization module, which includes: a link state machine, clock data recovery (CDR) and phase interpolator control logic, and automatic alignment logic (bit alignment logic). Furthermore, the main control FPGA130 provides real-time feedback to the DSP on the status of its internal high-speed serial link (destiny-breast11 research startup engine status, upgrade status, etc.), as a prerequisite for implementing DSP-side flow control.

[0028] Here, the master FPGA130 performs the following actions: 1) Receives data from the EMIF interface, performs clock domain conversion, and buffers it in the internal FIFO. 2) Reads data from the FIFO, performs 8B / 10B encoding, and sends it through the high-speed serial link TX port. 3) Simultaneously, its adaptive synchronization module is in a "locked" state, continuously monitoring the IDLE code sent by the receiver to maintain synchronization. The slave FPGA140 obtains data through the high-speed serial link receiver, decodes it, pushes it into the FIFO for cross-clock domain processing, writes it to the configuration FLASH, and continuously feeds back the write and verification status through the high-speed serial link transmitter.

[0029] In existing technologies, when a DSP, acting as a data source, sends firmware to an FPGA, it lacks downstream status awareness, resulting in a "data pump"-style unidirectional transmission mode that is highly susceptible to buffer overflows or interface crashes. This application innovatively designs a status feedback channel carried by the GPIO bus, enabling the main control FPGA130 to provide real-time feedback to the upstream DSP on its link status, buffer state, flash write status, and error packet numbers. The DSP constructs a global upgrade state machine, only continuing to send the next data packet upon receiving a "ready" signal; when a link anomaly is detected, it actively pauses transmission and automatically resumes transmission after the link is restored. This closed-loop control mechanism of "perception-decision-execution" avoids data loss and resource congestion, improving the upgrade success rate from probabilistic to deterministic and controllable, greatly enhancing the system's robustness.

[0030] In one possible implementation, when the digital signal processor 120 is used to preprocess the upgrade image file to generate a data packet, the digital signal processor 120 is specifically used to: encapsulate the upgrade image file based on instruction bits, data packet sequence number bits, and data area to determine the data packet; wherein, the instruction is used to indicate the operation type, the data packet sequence number bit is the sequence number of the current data packet, and the data area is a data block carrying 24-bit aligned data.

[0031] In one possible implementation, when the digital signal processor 120 verifies the status feedback signal sent by the main control FPGA 130, the digital signal processor 120 is specifically configured to: detect whether there is a ready state in the received status feedback signal; if so, continue sending the next data packet through verification; if not, pause data packet sending and wait for each level of the status feedback signal to be ready, and then initiate breakpoint resume based on the error packet sequence number; wherein, the status feedback signal includes a ready state, a linked state, a buffer state, a flash state, a verification state, and an error packet sequence number.

[0032] Here, the DSP internally maintains a global upgrade state machine, sending the next data packet only when the "ready" state is detected. Otherwise, the DSP automatically pauses data transmission through the EMIF interface and suspends the upgrade process instead of blindly continuing to send data. If the "ready" state is not met, the DSP further checks the connection status of the high-speed serial link. If the high-speed serial link is disconnected at this time, the DSP waits for the high-speed serial link to be restored and triggers an automatic retransmission mechanism without intervention from the host computer.

[0033] In one possible implementation, the main control FPGA130 is further configured to: switch from a connected state to a reconnected state when a series of invalid codewords or IDLE codes are detected as lost, and return to a linked state after the high-speed serial link is automatically restored.

[0034] Here, the adaptive module of the main control FPGA130 immediately detects consecutive invalid codewords, and its internal state machine immediately jumps from the "locked" state to the "reconnect" state. The main control FPGA130 automatically sets its status feedback signal to the DSP as an interrupt and pulls TX_READY low. After the receive interrupt, the DSP checks its status register and immediately suspends the current data packet transmission, suspending the transmission process. The DSP can send a message to the host computer 110 to indicate the current status. Since the main control FIFO cannot send data downstream and the data buffer is quickly filled, the main control FPGA130 keeps the TX_READY signal low to lock the DSP's data entry point and prevent data accumulation and loss.

[0035] In one possible implementation, when the main control FPGA 130 performs byte alignment, bit alignment, and phase adjustment processing to reconnect the high-speed serial link upon detecting an anomaly, the main control FPGA 130 is specifically used for: A: Search for start codes in the data stream of the high-speed serial link to determine the data byte boundaries in order to achieve the byte alignment process.

[0036] Here, after the link is restored, the IDLE start code is first searched in the data stream to determine the byte boundaries.

[0037] B: Fine-tune the sampling point position by adjusting the BitSlip port of the ISeDes module until the IDLE code is stably decoded to achieve bit alignment.

[0038] Here, by controlling the BitSlip port of ISederDes, the data stream sampling points are fine-tuned until the IDLE code can be stably decoded.

[0039] It should be noted that the ISeDes module is a dedicated high-speed serial interface hard IP integrated within modern high-performance FPGAs. It is used to: efficiently convert between parallel and serial data; support various high-speed serial protocols (such as high-speed serial links, Aurora, PCIe, Gigabit Ethernet, JESD204B, etc.); and achieve high-speed point-to-point communication across chips, boards, or backplanes. BitSlip is a signal that can be triggered by user logic (usually a pulse input); each time BitSlip is triggered, the ISeDes receiver shifts the output data one bit to the right or left; it is used to search for byte boundaries (such as consecutive IDLE sequences K28.5) when there is no frame delimiter.

[0040] C: Dynamically adjust the sampling clock phase to find the optimal sampling position to achieve the phase adjustment process.

[0041] Here, the clock and data phases are dynamically adjusted through an algorithm to find the optimal sampling point at the center of the eye diagram until the bit error rate drops to 0.

[0042] In one possible implementation, when the main control FPGA 130 is used to find the optimal sampling position for dynamically adjusting the sampling clock phase to achieve the phase adjustment process, the main control FPGA 130 is specifically used for: The input signal phase is sequentially delayed by a preset number of signal periods to determine the maximum and minimum phase delay values ​​for successful bit alignment; the average of the maximum and minimum phase delay values ​​is used as the fixed phase delay.

[0043] Here, the input signal phase is delayed by 1 / 32 of the signal period. Each time the phase is adjusted, a new bit sliding attempt is made. The maximum and minimum phase delays that successfully align the bit sliding with the byte are found, and their average is taken as the fixed phase delay. If alignment is achieved after 16 phase adjustments, the 8th phase delay value is taken as the fixed phase delay. After continuously receiving complete IDLE codes (8 bytes) and confirming their validity and correctness, the adaptive module determines that the high-speed serial link is stable, locks the current data stream bit start point and phase relationship, and the state machine returns to the locked state.

[0044] In this application, the DSP not only receives status updates but also uploads detailed status reports from the main control FPGA to the host computer via the network, providing a user-friendly interface. This allows maintenance personnel to clearly see, for example, "Upgrade paused, reason: LVDS is automatically synchronizing, progress xx%" on the PC. By converting the invisible physical layer signals into visible and understandable status information at the upper layer, precise fault location and process transparency are achieved, significantly reducing the technical requirements for maintenance personnel and the time cost of troubleshooting.

[0045] In existing technologies, once the LVDS high-speed serial link is interrupted due to interference or connection abnormalities, the entire upgrade process fails and requires restarting via the host computer 110 or manual reset to begin again. This application, however, constructs a complete link state machine in both the master FPGA 130 and the slave FPGA 140. Upon detecting a link abnormality, it can automatically trigger a full hardware reconnection process, including byte alignment, bit sliding adjustment, and phase compensation, within microseconds. This process requires no software intervention, reducing recovery time from seconds or even minutes in traditional solutions to milliseconds, significantly reducing unplanned downtime and improving the system's continuous operation and overall availability. Traditional solutions typically employ one-time static phase calibration, which struggles to handle timing drift caused by temperature changes and power fluctuations during device operation, leading to increased long-term communication error rates. This application integrates a clock data recovery (CDR) unit and phase interpolator control logic within the FPGA to continuously monitor and dynamically adjust the phase relationship between the sampling clock and the data signal, ensuring it is always locked at the optimal sampling point in the "eye diagram." This mechanism effectively compensates for setup / hold time deviations caused by environmental changes, enabling the system to maintain an extremely low bit error rate (BER < 1e-12) even under complex operating conditions, significantly enhancing the long-term stability and integrity of data transmission.

[0046] For further details, please refer to Figure 2 , Figure 2 A flowchart illustrating the high-speed serial link reconnection mechanism provided in this application embodiment. Figure 2As shown, in step one, the link state machine enters the relink state: When the main control FPGA detects multiple consecutive invalid codewords (e.g., eight consecutive non-standard 8B / 10B encoded symbols), or when the number of consecutive IDLE start codes not received exceeds a preset threshold, its internal link state machine immediately switches from the "Locked" state to the "Relink" state. Simultaneously, the main control FPGA sets the `high-speed serial link state` in the GPIO feedback signal to "abnormal" and pulls the `TX_READY` signal low, notifying the digital signal processor to pause data transmission. In step two, byte alignment is initiated: In the initial stage of link recovery, the data stream may have phase shifts or boundary misalignments. The receiving end of the main control FPGA begins searching for standard IDLE start codes (e.g., K28.5 special characters) in the high-speed serial link data stream. Once two or more consecutive valid K28.5 codes are detected, the byte boundary positions are initially determined, and byte alignment is completed. In step three, bit alignment processing is performed: Due to potential metastable deviations between the sampling clock and data edges, further bit-level alignment is required. The main control FPGA controls the BitSlip port of the high-speed serial transceiver (ISerDes2) to slide the data sampling window bit by bit, moving 1 bit width at a time, attempting to decode subsequent data streams to see if it can continuously and stably parse valid 8B / 10B codewords. If at least N (e.g., N=16) IDLE codes or known training sequences can be correctly decoded continuously under the current BitSlip value, the bit offset is considered valid; otherwise, the BitSlip value continues to increase until all possible bit offsets (usually 8 cases) are traversed; after finding all valid BitSlip configurations, the set with the widest fault-tolerant window is selected as the optimal alignment point. Step four, dynamic phase adjustment and eye diagram center locking: To further improve link stability and prevent secondary loss of synchronization due to temperature drift or power fluctuations, this embodiment introduces a dynamic phase adjustment mechanism based on a phase interpolator. Step five, state synchronization and link locking: When the system can continuously receive and verify 8 complete and correct IDLE code packets under the selected BitSlip and phase offset, it is determined that the link has restored stable communication capability. At this point: the adaptive synchronization module switches the link state machine from "Relink" back to "Locked"; the main control FPGA updates the `high-speed serial link state` to "Ready" and pulls the `TX_READY` signal high; simultaneously, it writes the error packet sequence number `errpkgNum` into the status register for the digital signal processor to read for breakpoint resumption. Step six, triggering the digital signal processor's resumption process: after detecting an interrupt on the rising edge of `TX_READY`, the digital signal processor queries the main control FPGA's status register, obtains the `errpkgNum` field, and confirms the data packet number that should be retransmitted.The digital signal processor then retransmits the corresponding data packet from the point of interruption, achieving seamless continuation and avoiding the efficiency loss caused by overall rollback and retransmission.

[0047] This application provides a remote upgrade system for multiple FPGA devices. The remote upgrade system includes a host computer, a digital signal processor (DSP), and a master FPGA. Both the host computer and the master FPGA are communicatively connected to the DSP. The DSP receives upgrade image files from at least one slave FPGA device sent by the host computer, preprocesses the upgrade image files to generate data packets, verifies the status feedback signal sent by the master FPGA, and sends the data packets to the master FPGA after successful verification. The master FPGA buffers the data packets and sends them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link. When an abnormality is detected in the high-speed serial link, byte alignment, bit alignment, and phase adjustment are performed to reconnect the high-speed serial link. The master FPGA then resends the status feedback information to the DSP, enabling the DSP to continue sending subsequent data packets starting from the erroneous data packet sequence number until the upgrade image file transmission is complete. It solves the adaptive synchronization problem of high-speed serial links, and establishes a data interaction response mechanism between chips at each level, enabling digital signal processors to sense the status of downstream links and intelligently allocate data, thereby achieving fully automatic fault-tolerant recovery at the system level and improving the upgrade efficiency of multi-slave FPGA devices.

[0048] Please see Figure 3 , Figure 3 This is a flowchart illustrating a remote upgrade method for multiple FPGA devices provided in an embodiment of this application. Figure 3 As shown, the remote upgrade method includes: S301: Control the digital signal processor to receive upgrade image files of at least one slave FPGA device sent by the host computer, preprocess the upgrade image files to generate data packets, verify the status feedback signals sent by the master FPGA, and send the data packets to the master FPGA after the verification is successful.

[0049] In this step, the control digital signal processor receives upgrade image files of at least one slave FPGA device sent by the host computer, preprocesses the upgrade image files to generate data packets, and verifies the status feedback signals sent by the master FPGA. After the verification is successful, the data packets are sent to the master FPGA.

[0050] S302: Control the master FPGA to buffer the data packet and send the data packet to the corresponding slave FPGA device for upgrade processing via a high-speed serial link.

[0051] In this step, the master FPGA buffers the data packets and sends them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link.

[0052] S303: When the main control FPGA detects an abnormality in the high-speed serial link, it performs byte alignment processing, bit alignment processing, and phase adjustment processing to complete the reconnection of the high-speed serial link, and resends the status feedback information to the digital signal processor so that the digital signal processor continues to send subsequent data packets according to the error data packet sequence number until the upgrade image file transmission is completed.

[0053] In this step, when the main control FPGA detects an abnormality in the high-speed serial link, it performs byte alignment, bit alignment, and phase adjustment to complete the reconnection of the high-speed serial link. It then resends status feedback information to the digital signal processor so that the digital signal processor can continue to send subsequent data packets according to the sequence number of the erroneous data packet until the upgrade image file transfer is completed.

[0054] In one possible implementation, verifying the status feedback signal sent by the main control FPGA includes: Detect whether a ready state exists in the received status feedback signal; If so, proceed with the verification and send the next data packet; If not, then pause data packet transmission and wait for each level of the status feedback signal to be ready, and then initiate breakpoint resumption based on the error packet sequence number; wherein, the status feedback signal includes ready status, link status, buffer status, flash status, verification status and error packet sequence number.

[0055] In one possible implementation, the remote upgrade method further includes: When consecutive invalid codewords or IDLE code loss are detected, the system switches from the connected state to the reconnected state and returns to the linked state after the high-speed serial link is automatically restored.

[0056] In one possible implementation, the step of performing byte alignment, bit alignment, and phase adjustment processing to reconnect the high-speed serial link when an anomaly is detected includes: The start code is searched in the data stream of the high-speed serial link to determine the data byte boundaries in order to achieve the byte alignment process; The sampling point position is fine-tuned by adjusting the BitSlip port of the ISeDes module until the IDLE code is stably decoded to achieve bit alignment. The sampling clock phase is dynamically adjusted to find the optimal sampling position to achieve the phase adjustment process.

[0057] In one possible implementation, the dynamic adjustment of the sampling clock phase to find the optimal sampling position to achieve the phase adjustment process includes: The input signal phase is sequentially delayed by a preset number of signal periods to determine the maximum and minimum phase delay values ​​for successful bit alignment. The average of the maximum phase delay value and the minimum phase delay value is used as the fixed phase delay.

[0058] In one possible implementation, the preprocessing of the upgrade image file to generate the data package includes: The upgrade image file is encapsulated based on the instruction bit, the data packet sequence number bit, and the data area to determine the data packet; wherein, the instruction bit is used to indicate the operation type, the data packet sequence number bit is the sequence number of the current data packet, and the data area is a block of data that carries 24-bit aligned data.

[0059] This application provides a remote upgrade method for multiple FPGA devices. The remote upgrade method includes: controlling a digital signal processor (DSP) to receive an upgrade image file of at least one slave FPGA device sent by a host computer; preprocessing the upgrade image file to generate a data packet; verifying the status feedback signal sent by the master FPGA; and sending the data packet to the master FPGA after successful verification. The master FPGA is then controlled to buffer the data packet and send it to the corresponding slave FPGA device for upgrade processing via a high-speed serial link. When the master FPGA detects an anomaly in the high-speed serial link, it performs byte alignment, bit alignment, and phase adjustment to reconnect the high-speed serial link and resends the status feedback information to the DSP, enabling the DSP to continue sending subsequent data packets based on the erroneous data packet sequence number until the upgrade image file transmission is complete. This method solves the adaptive synchronization problem of the high-speed serial link and establishes a data interaction response mechanism between chips at each level, allowing the DSP to sense the downstream link status and intelligently adjust data, thereby achieving fully automatic fault-tolerant recovery at the system level and improving the upgrade efficiency of multiple slave FPGA devices.

[0060] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 4As shown, the electronic device 400 includes a processor 410, a memory 420, and a bus 430.

[0061] The memory 420 stores machine-readable instructions executable by the processor 410. When the electronic device 400 is running, the processor 410 communicates with the memory 420 via the bus 430. When the machine-readable instructions are executed by the processor 410, they can perform the operations described above. Figure 3 The steps of the remote upgrade method for multiple FPGA devices in the method embodiment shown are specifically implemented in the method embodiment and will not be repeated here.

[0062] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 3 The steps of the remote upgrade method for multiple FPGA devices in the method embodiment shown are specifically implemented in the method embodiment and will not be repeated here.

[0063] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0064] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0065] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0066] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0067] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A remote upgrade system for multiple FPGA devices, characterized in that, The remote upgrade system includes a host computer, a digital signal processor, and a main control FPGA, wherein both the host computer and the main control FPGA are communicatively connected to the digital signal processor; wherein... The digital signal processor is used to receive upgrade image files of at least one slave FPGA device sent by the host computer, preprocess the upgrade image files to generate data packets, verify the status feedback signals sent by the master FPGA, and send the data packets to the master FPGA after the verification is successful. The master FPGA is used to buffer the data packets and send them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link. When an abnormality is detected in the high-speed serial link, byte alignment, bit alignment and phase adjustment are performed to complete the reconnection of the high-speed serial link. Status feedback information is resent to the digital signal processor so that the digital signal processor can continue to send subsequent data packets according to the sequence number of the erroneous data packets until the upgrade image file transmission is completed.

2. The remote upgrade system according to claim 1, characterized in that, When the digital signal processor is used to verify the status feedback signal sent by the main control FPGA, the digital signal processor is specifically used for: Detect whether a ready state exists in the received status feedback signal; If so, proceed with the verification and send the next data packet; If not, then pause data packet transmission and wait for each level of the status feedback signal to be ready, and then initiate breakpoint resumption based on the error packet sequence number; wherein, the status feedback signal includes ready status, link status, buffer status, flash status, verification status and error packet sequence number.

3. The remote upgrade system according to claim 1, characterized in that, The main control FPGA is also used for: When consecutive invalid codewords or IDLE code loss are detected, the system switches from the connected state to the reconnected state and returns to the linked state after the high-speed serial link is automatically restored.

4. The remote upgrade system according to claim 1, characterized in that, When the main control FPGA is used to perform byte alignment, bit alignment, and phase adjustment processing to complete the reconnection of the high-speed serial link when an anomaly is detected, the main control FPGA is specifically used for: The start code is searched in the data stream of the high-speed serial link to determine the data byte boundaries in order to achieve the byte alignment process; The sampling point position is fine-tuned by adjusting the BitSlip port of the ISeDes module until the IDLE code is stably decoded to achieve bit alignment. The sampling clock phase is dynamically adjusted to find the optimal sampling position to achieve the phase adjustment process.

5. The remote upgrade system according to claim 4, characterized in that, When the main control FPGA is used to find the optimal sampling position by dynamically adjusting the sampling clock phase to achieve the phase adjustment process, the main control FPGA is specifically used for: The input signal phase is sequentially delayed by a preset number of signal periods to determine the maximum and minimum phase delay values ​​for successful bit alignment. The average of the maximum phase delay value and the minimum phase delay value is used as the fixed phase delay.

6. The remote upgrade system according to claim 1, characterized in that, When the digital signal processor is used to preprocess the upgraded image file to generate a data packet, the digital signal processor is specifically used for: The upgrade image file is encapsulated based on the instruction bit, the data packet sequence number bit, and the data area to determine the data packet; wherein, the instruction bit is used to indicate the operation type, the data packet sequence number bit is the sequence number of the current data packet, and the data area is a block of data that carries 24-bit aligned data.

7. A method for remotely upgrading multiple FPGA devices, characterized in that, The remote upgrade method is applied to the remote upgrade system for multiple FPGA devices as described in any one of claims 1-6, and the remote upgrade method includes: The control digital signal processor receives upgrade image files of at least one slave FPGA device sent by the host computer, preprocesses the upgrade image files to generate data packets, verifies the status feedback signals sent by the master FPGA, and sends the data packets to the master FPGA after the verification is successful. The master FPGA is controlled to buffer the data packets and send them to the corresponding slave FPGA device for upgrade processing via a high-speed serial link; When the main control FPGA detects an anomaly in the high-speed serial link, it performs byte alignment, bit alignment, and phase adjustment to reconnect the high-speed serial link. It then resends status feedback information to the digital signal processor so that the digital signal processor can continue sending subsequent data packets based on the erroneous data packet sequence number until the upgrade image file transfer is complete.

8. The remote upgrade method according to claim 7, characterized in that, The verification of the status feedback signal sent by the main control FPGA includes: Detect whether a ready state exists in the received status feedback signal; If so, proceed with the verification and send the next data packet; If not, then pause data packet transmission and wait for each level of the status feedback signal to be ready, and then initiate breakpoint resumption based on the error packet sequence number; wherein, the status feedback signal includes ready status, link status, buffer status, flash status, verification status and error packet sequence number.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the remote upgrade method for multiple FPGA devices as described in claim 7 or 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the remote upgrade method for multiple FPGA devices as described in claim 7 or 8.

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