A low-latency data exchange method for real-time simulation systems and related apparatus

Abstract

This invention discloses a low-latency data exchange method and related apparatus for real-time simulation systems, belonging to the field of data exchange technology. The method includes: initializing the real-time simulation system, which includes simulation nodes, exchange nodes, and a master control node; the simulation nodes construct dynamically long data packets based on the simulation results to be exchanged and send the dynamically long data packets via a high-speed serial link; the exchange nodes receive the dynamically long data packets and, based on the system-level physical topology, forward the dynamically long data packets using a small packet fast transmission mechanism and a bufferless direct-pass transmission mechanism; the target simulation node receives the dynamically long data packets and performs deterministic parsing on them. This method and related apparatus can reduce the latency of data exchange in real-time simulation systems and ensure the determinism of data transmission.

Description

Technical Field

[0001] This invention belongs to the field of data exchange technology, and relates to a low-latency data exchange method and related apparatus for real-time simulation systems. Background Technology

[0002] In high-end industrial fields such as aerospace and electrical engineering, real-time simulation systems, by establishing accurate mathematical models in a virtual environment to simulate the dynamic behavior of physical systems, have become indispensable and efficient tools in the design, testing, and verification of complex products such as aircraft motor control and multi-electric system simulation. With the continuous improvement of simulation model accuracy and the significant increase in system scale and complexity, real-time simulation systems place higher demands on the timeliness and determinism of cross-node data exchange, often requiring transmission delays at the microsecond or even sub-microsecond level.

[0003] However, existing general-purpose data exchange equipment (such as Ethernet-based switches) or traditional interconnection solutions are limited by the overhead of their communication protocol stacks, the uncertainties introduced by operating system scheduling, and the complexity of static topology configuration mechanisms. These limitations make it difficult to meet the deterministic low-latency requirements of millisecond- or even microsecond-level synchronous simulations. Especially in large-scale simulation clusters consisting of dozens to hundreds of heterogeneous simulation nodes (including heterogeneous computing units such as CPUs, GPUs, and FPGAs), traditional switching mechanisms often lead to increased data transmission latency jitter, strong path dependence, and difficulties in changing the topology, severely restricting the overall scalability of the system and the efficiency of practical engineering deployment. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-latency data exchange method and related apparatus for real-time simulation systems. This method and related apparatus can reduce the latency of data exchange in real-time simulation systems.

[0005] To achieve the above objectives, this invention discloses a low-latency data exchange method for real-time simulation systems, comprising: The real-time simulation system is initialized, and the real-time simulation system includes simulation nodes, switching nodes, and a master control node. The simulation node constructs a dynamic length data packet based on the simulation results to be exchanged, and sends the dynamic length data packet through a high-speed serial link; The switching node receives the dynamic length data packet and forwards it according to the system-level physical topology using a small packet fast transmission mechanism and a bufferless pass-through transmission mechanism. The target simulation node receives the dynamic length data packet and performs deterministic parsing on the dynamic length data packet.

[0006] Furthermore, the process of initializing the real-time simulation system is as follows: Configure local node identifiers for each simulation node and switching node in the real-time simulation system. A local adjacency table is constructed based on the bidirectional handshake mechanism of SYN-ACK packets at the link layer. Based on the local adjacency table, according to the preset topology determination rules, each exchange node is divided into a central exchange node and an edge exchange node. The master node constructs a system-level physical topology diagram based on the local node identifiers and local adjacency tables of each simulation node and switching node.

[0007] Furthermore, when the number of exchange nodes among the neighboring nodes of any exchange node is greater than or equal to a set threshold T, and all of its neighboring nodes are simulation nodes or exchange nodes, the exchange node is automatically determined to be a central exchange node; otherwise, the exchange node is automatically determined to be an edge exchange node.

[0008] Furthermore, the dynamic length data packet includes a frame header, source identifier, destination identifier, data length, sequence number, and simulation data.

[0009] Furthermore, the process by which the switching node receives the dynamic length data packet and, based on the system-level physical topology, forwards the dynamic length data packet using a small packet fast transmission mechanism and a bufferless pass-through transmission mechanism is as follows: The switching node receives the dynamic length data packet, extracts the destination identifier from the dynamic length data packet, and matches the destination identifier with the RID associated with each downlink port of the switching node. If the match is successful, the dynamic length data packet is forwarded to the corresponding downlink port; if the match fails, if the switching node is an edge switching node, the dynamic length data packet is forwarded to the cascade port; if the switching node is a central switching node, the dynamic length data packet is discarded and an alarm event is triggered. At the same time, the destination identifier, source identifier, timestamp, and error type of the dynamic length data packet are encoded and reported to the master control node through the management channel.

[0010] Furthermore, when multiple dynamic length data packets compete for the same output port, a first-in-first-out (FIFO) strategy and a round-robin arbitration strategy are used to send each dynamic length data packet.

[0011] Furthermore, the process of performing deterministic parsing on the dynamic length data packet is as follows: Parse the frame header in dynamic length data packets to complete physical layer synchronization and packet integrity verification; The source identifier field is extracted from the dynamic length data packet. The extracted source identifier field is compared with the local routing configuration table uniformly issued by the master node when the task is loaded. If the comparison fails, the dynamic length data packet is discarded. If the comparison succeeds, the sequence number in the dynamic length data packet is parsed to verify the packet sequence continuity. When the sequence number verification passes, the simulation data field in the dynamic length data packet is extracted and sent to the local simulation model calculation engine to complete cross-node state synchronization and joint simulation.

[0012] Furthermore, the real-time simulation system exhibits a star-shaped physical topology.

[0013] The present invention discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the low-latency data exchange method for a real-time simulation system.

[0014] The present invention discloses a computer-readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the low-latency data exchange method for a real-time simulation system.

[0015] The present invention has the following beneficial effects: In practical operation, the low-latency data exchange method and related apparatus for real-time simulation systems described in this invention construct dynamically long data packets based on the simulation results to be exchanged, and send these dynamically long data packets through a high-speed serial link. This eliminates the need for traditional network protocol stacks, achieving end-to-end hardware pipelined processing from encapsulation and routing to parsing. Simultaneously, a small packet fast transmission mechanism and a bufferless direct-pass transmission mechanism are used to forward the dynamically long data packets. Through the high-speed serial link and the bufferless direct-pass transmission mechanism, data packets can be forwarded without software intervention or complete buffering, thereby reducing the latency of data exchange in real-time simulation systems. This reduces the internal processing latency of the exchange node to the nanosecond level, laying the protocol and implementation foundation for end-to-end microsecond-level transmission and fundamentally solving the high latency problem caused by protocol stack overhead, system scheduling, and store-and-forward mode in general data exchange equipment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1This is a structural diagram of the real-time simulation system in this invention; Figure 2 This is an architecture diagram of the real-time simulation system in this invention; Figure 3 A schematic diagram of the system physical topology construction process; Figure 4 A schematic diagram of the synchronous response data packet format; Figure 5 The intention is to exchange data packet formats; Figure 6 This is a flowchart of the method of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0020] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0021] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0022] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0023] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0026] Example 1 The real-time simulation system described in this invention is built on a large-scale heterogeneous platform. The real-time simulation system includes a master control node, simulation nodes, and switching nodes, such as... Figure 1 As shown.

[0027] As the control center of the real-time simulation system, the master control node is responsible for system-level human-computer interaction, unified resource management, and the scheduling and execution of simulation tasks, ensuring the coordinated and stable operation of the system.

[0028] The simulation node consists of various heterogeneous computing resources, such as general-purpose CPUs (Central Processing Units), GPUs (Graphics Processing Units) that focus on parallel computing, and FPGAs (Field Programmable Gate Arrays) that have high parallelism and customizability. Together, they form a high-performance simulation computing cluster to undertake the real-time solution task of specific simulation models.

[0029] The switching nodes are implemented based on high-performance FPGA chips and adopt a lightweight "Micro-Packet Express" hardware forwarding mechanism. They abandon the traditional network protocol stack, support nanosecond-level packet parsing and bufferless pass-through switching, and provide a highly deterministic and low-latency communication path for data interaction between simulation nodes, thereby effectively supporting the stringent data transmission requirements of system-level real-time simulation.

[0030] The real-time simulation system provides a high-performance, low-latency integrated computing and communication foundation for large-scale real-time simulation through the collaboration of heterogeneous computing resources and a dedicated exchange mechanism.

[0031] Simulation nodes and switching nodes are interconnected via a high-speed serial bus (such as a SerDes link like Aurora), and the overall system presents a star physical topology, as shown below. Figure 2 As shown, the switching node supports up to three levels of cascading expansion. The real-time simulation system can flexibly increase or decrease the number of nodes according to the simulation scale, while maintaining the deterministic latency characteristics of the entire network, significantly reducing the number of hops in cross-node communication, and eliminating the cumulative delay and uncertainty introduced by multi-level forwarding.

[0032] Based on the above, refer to Figure 6 The low-latency data exchange method for a real-time simulation system described in this invention includes an initialization phase and a system simulation operation phase. The specific operations during the initialization phase are as follows: 11) Configure local identifiers for each simulation node and switching node; Before the initial deployment of the real-time simulation system, the master node pre-configures globally unique Local Node Identifiers (LIDs) for each simulation node and switching node. These LIDs are stored in the non-volatile memory of each simulation node and switching node in fixed-length binary code. The LIDs are uniformly allocated and managed by the master node, serving as the fundamental identity credential for identifying connection relationships and cross-node addressing throughout the entire system, and are used throughout subsequent link handshakes, data routing, and state management processes.

[0033] 12) Construct a local adjacency table; Between the simulation node and each switching node, all physically directly connected adjacent nodes (including simulation node–switching node and switching node–switching node) synchronously enter the link layer handshake state. Each node periodically sends a lightweight synchronization (SYN) message to its peer node, wherein the payload area of ​​the message contains the LID field of the corresponding node. After successfully receiving and verifying the integrity of the SYN message, the peer node immediately returns an ACK message to the corresponding node. The payload area of ​​the ACK message carries its own LID as the remote node identifier (RID). By parsing the message payload, both communicating parties obtain the local node identifier of the peer node, thereby uniquely determining an adjacent edge and constructing a local adjacency table to complete the automatic identification of the "point-to-point" physical connection relationship.

[0034] When the physical connection between any nodes changes, such as due to physical connection alteration or online hot-plugging, the neighboring nodes of that node will attempt to re-establish the link-layer handshake. After the SYN-ACK packet is responded to again, the local adjacency table is automatically updated to achieve dynamic reconstruction or online recovery. The format of the SYN-ACK packet is as follows: Figure 4 As shown, its frame structure satisfies deterministic timing constraints, and the delay of a single handshake does not exceed 1 microsecond.

[0035] 13) Determine the central exchange node; Based on the adjacency table, each switching node automatically performs the election of a Central Switch Node (CSN) according to the preset topology determination rules.

[0036] For example, if the number of adjacent nodes of any switching node is greater than or equal to a set threshold T (T>1), and all of its adjacent nodes are simulation nodes or switching nodes, then the switching node is automatically determined to be a central switching node, responsible for data routing and scheduling across nodes within the real-time simulation system; otherwise, the switching node is automatically determined to be an edge switching node (ESN), responsible for edge switching or cascading relay functions of the real-time simulation system. This election mechanism is dynamically executed by the local logic of the switching node without the intervention of the master node.

[0037] 14) Construct a system-level physical topology diagram through the master control node; Each switching node and simulation node uploads its own LID and all identified RIDs to the master node through the management channel. The master node performs deduplication, association, and graph theory modeling on the received information to construct an undirected connected graph with LIDs as vertices and adjacent edges connecting them. This undirected connected graph serves as the system-level physical topology graph. The system-level physical topology graph can accurately reflect the actual physical connection relationships, cascading levels, and central radiation structure between all nodes, providing a deterministic topology basis for subsequent low-latency routing planning and dynamic load balancing.

[0038] The working process during the system simulation operation phase is as follows: 21) Dynamic encapsulation and transmission of small data packets; Each simulation node encapsulates data in its local logic according to the routing configuration table issued by the master node. The simulation results to be exchanged (such as state variables, control commands, sensor sample values, etc.) are organized into payloads, and then assembled into dynamic-length data packets according to a fixed structure. The total length L of the dynamic-length data packets does not exceed 128 data units to adapt to the transmission characteristics of high-speed serial links and the FPGA hardware parsing bandwidth. The format of the dynamic-length data packets is as follows: Figure 5 As shown, the dynamic length data packet includes a frame header, source identifier, destination identifier, data length, sequence number, and simulation data, specifically: Frame Header: Used for physical layer frame synchronization and packet boundary identification; Source ID: The LID of this node, identifying the data sender; Destination ID: The target simulation node's LID, serving as the unique addressing basis for hardware routing; Payload Length: The number of bytes of payload, ranging from 1 to 127 data units; Sequence Number: A monotonically increasing unsigned integer used for packet order verification and packet loss detection at the receiving end; Simulation data: The effective load output by the actual simulation model; After the dynamic length data packet is encapsulated, it is sent to the adjacent switching node through a high-speed serial bus. The fixed short frame structure effectively reduces transmission latency and avoids latency jitter caused by long frame blocking.

[0039] 22) Hardware routing and cacheless forwarding; Within the first clock cycle of a dynamically sized data packet arriving at a port, the switching node initiates a hardware parsing pipeline. First, it extracts the destination identifier and performs parallel table lookups to match it with the RID associated with each downlink port of the node. If a match is successful, the dynamically sized data packet is forwarded to the corresponding downlink port. If a match fails, the dynamically sized data packet is processed differently based on the switching node type. Specifically, edge switching nodes forward the dynamically sized data packet to cascaded ports for further routing by the upstream node; central switching nodes determine it as an illegal address, discard the dynamically sized data packet, trigger an alarm event, and simultaneously report the destination identifier, source identifier, timestamp, and error type code to the master control node via the management channel.

[0040] The entire process employs a bufferless, direct-through transmission mechanism. Dynamically long data packets do not need to enter the storage device buffer, and parsing and forwarding are pipelined within a single clock domain. When multiple data packets compete for the same output port, a composite arbitration strategy is activated: a First-In-First-Out (FIFO) strategy, which strictly queues and forwards consecutive data packets from the same input port according to their arrival order, preventing out-of-order delivery and priority reversal; and a Round-Robin strategy, where the arbitrator periodically grants output permissions to data packets from different input ports, with each input port forwarding only one data packet at a time, ensuring fair allocation of bandwidth across links.

[0041] 23) Data reception and parsing; Upon arrival of a dynamically sized data packet, the target simulation node executes a deterministic parsing process, specifically: first, it parses the frame header to complete physical layer synchronization and packet integrity verification; then, it extracts the source identifier field and compares it with the local routing configuration table uniformly issued by the master node during task loading. If the comparison fails, the dynamically sized data packet is discarded; if the comparison succeeds, it continues to parse the sequence number to verify packet sequence continuity. Once the sequence number verification passes, it extracts the simulation data field and sends it to the local simulation model calculation engine to complete cross-node state synchronization and joint simulation.

[0042] It should be noted that the present invention has the following characteristics: a1) This invention can achieve microsecond-level end-to-end switching latency, fundamentally solving the high latency problem caused by protocol stack overhead, system scheduling and store-and-forward mode in general data exchange equipment.

[0043] The real-time simulation system uses high-speed serial links with low latency and high reliability data transmission design to interconnect the nodes. It abandons the traditional network protocol stack and realizes full-link hardware pipelined processing from encapsulation, routing to parsing. Combined with "small packet fast transmission" and a bufferless pass-through switching mechanism, data packets can be forwarded without software participation or complete caching, reducing the internal processing latency of the switching node to the nanosecond level, laying the protocol and implementation foundation for end-to-end microsecond-level transmission.

[0044] a2) This invention can guarantee the determinism of data transmission. Starting from the topology and scheduling strategy, this invention ensures the predictability of data transmission behavior.

[0045] By adopting a star topology and limiting the number of cascaded switching nodes to a maximum of three levels, the maximum number of hops in the data exchange path is significantly reduced, effectively controlling the cumulative latency of data transmission and minimizing the cumulative latency and path uncertainty in the network structure.

[0046] Within the switching nodes, a composite arbitration strategy combining FIFO and Round-Robin is employed. This ensures orderly forwarding of data packets from the same source and fair bandwidth allocation for data packets from multiple sources. This architectural approach eliminates unpredictable latency jitter caused by "long streams blocking short streams," meeting the stringent timing deterministic requirements of simulation stepping.

[0047] a3) This invention supports flexible system deployment and expansion. Through automated topology management, this invention overcomes the problems of poor scalability and low deployment efficiency caused by traditional solutions relying on static manual configuration.

[0048] Each node is pre-configured with a globally unique Local Node Identifier (LID), decoupling its identity from its physical connection. The real-time simulation system can flexibly add or remove nodes according to the simulation scale without having to replan network addresses.

[0049] Simulation nodes and switching nodes automatically identify adjacency relationships through a two-way handshake mechanism using SYN-ACK messages at the link layer, assisting the master node in generating a system-level physical topology map, avoiding dependence on external topology description files, and supporting dynamic reconstruction and online recovery, achieving "plug and play".

[0050] The switching nodes can automatically elect central and edge switching nodes based on the adjacency table and preset rules. This process requires no manual intervention, and the system can intelligently adapt to topology changes, providing self-organizing capabilities for efficient routing of large-scale clusters.

[0051] a4) This invention addresses the high reliability and compatibility of heterogeneous simulation platforms. It designs a multi-layered verification and fault-tolerance mechanism to improve system robustness in complex heterogeneous environments.

[0052] The data packet uses the source identifier and destination identifier as the sole basis for cross-node addressing and verification, and is completely decoupled from the computing unit type (CPU / GPU / FPGA) within the node, enabling heterogeneous computing resources to be transparently accessed and uniformly addressed.

[0053] At the receiving end, the legality of the data source is verified by matching the source identifier to prevent illegal injection; hardware-level packet sequence verification and packet loss detection are achieved through sequence number verification to ensure the integrity and correctness of data transmission.

[0054] During the routing process, packets that cannot match the destination address are processed differently, and detailed error information is reported to the master control node. This mechanism enables rapid error location and isolation, greatly enhancing the efficiency of system debugging, operation and maintenance, and overall reliability.

[0055] This invention comprises a complete solution based on innovations such as hardware-based simplified pathways, automated topology management, intelligent routing scheduling, and multi-layered reliability design. It provides crucial underlying communication support for achieving higher precision, greater reliability, and larger-scale real-time simulation of aerospace power systems, significantly improving the overall performance and practicality of the simulation system.

[0056] Example 2 A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a low-latency data exchange method for a real-time simulation system. For example, the method includes: initializing the real-time simulation system, which includes simulation nodes, exchange nodes, and a master node; the simulation nodes constructing dynamically long data packets based on the simulation results to be exchanged and sending the dynamically long data packets via a high-speed serial bus; the exchange nodes receiving the dynamically long data packets and forwarding them using a small-packet fast transmission mechanism and a bufferless pass-through transmission mechanism according to the system-level physical topology; and the target simulation node receiving the dynamically long data packets and performing deterministic parsing on them. The memory may include main memory, such as high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device. The processor, network interface, and memory are interconnected via an internal bus, which may be an industry-standard architecture bus, a peripheral component interconnection standard bus, an extended industry-standard architecture bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory stores the program; specifically, the program may include program code, which includes computer operation instructions. Memory can include main memory and non-volatile memory, and provides instructions and data to the processor.

[0057] Example 3 A computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of a low-latency data exchange method for a real-time simulation system. For example, the method includes: initializing a real-time simulation system, which includes simulation nodes, exchange nodes, and a master node; the exchange nodes receiving dynamically long data packets and forwarding them using a small-packet fast transmission mechanism and a bufferless pass-through transmission mechanism according to a system-level physical topology; the target simulation node receiving the dynamically long data packets and performing deterministic parsing on them. Specifically, the computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. The volatile memory may include random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0058] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0059] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0063] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0064] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A low-latency data exchange method for a real-time simulation system, characterized in that, include: The real-time simulation system is initialized, and the real-time simulation system includes simulation nodes, switching nodes, and a master control node. The simulation node constructs a dynamic length data packet based on the simulation results to be exchanged, and sends the dynamic length data packet through a high-speed serial link; The switching node receives the dynamic length data packet and forwards it according to the system-level physical topology using a small packet fast transmission mechanism and a bufferless pass-through transmission mechanism. The target simulation node receives the dynamic length data packet and performs deterministic parsing on the dynamic length data packet.

2. The low-latency data exchange method for a real-time simulation system according to claim 1, characterized in that, The process of initializing the real-time simulation system is as follows: Configure local node identifiers for each simulation node and switching node in the real-time simulation system. A local adjacency table is constructed based on the bidirectional handshake mechanism of SYN-ACK packets at the link layer. Based on the local adjacency table, according to the preset topology determination rules, each exchange node is divided into a central exchange node and an edge exchange node. The master node constructs a system-level physical topology diagram based on the local node identifiers and local adjacency tables of each simulation node and switching node.

3. The low-latency data exchange method for a real-time simulation system according to claim 2, characterized in that, If the number of exchange nodes among the neighboring nodes of any exchange node is greater than or equal to a set threshold T, and all of its neighboring nodes are either simulation nodes or exchange nodes, then the exchange node is automatically determined to be a central exchange node; otherwise, the exchange node is automatically determined to be an edge exchange node.

4. The low-latency data exchange method for a real-time simulation system according to claim 2, characterized in that, The dynamic length data packet includes a frame header, source identifier, destination identifier, data length, sequence number, and simulation data.

5. The low-latency data exchange method for a real-time simulation system according to claim 4, characterized in that, The process by which the switching node receives the dynamic length data packet and forwards it using a small packet fast transmission mechanism and a bufferless pass-through transmission mechanism, based on the system-level physical topology, is as follows: The switching node receives the dynamic length data packet, extracts the destination identifier from the dynamic length data packet, and matches the destination identifier with the RID associated with each downlink port of the switching node. If the match is successful, the dynamic length data packet is forwarded to the corresponding downlink port; if the match fails, if the switching node is an edge switching node, the dynamic length data packet is forwarded to the cascade port; if the switching node is a central switching node, the dynamic length data packet is discarded and an alarm event is triggered. At the same time, the destination identifier, source identifier, timestamp, and error type of the dynamic length data packet are encoded and reported to the master control node through the management channel.

6. The low-latency data exchange method for a real-time simulation system according to claim 5, characterized in that, When multiple dynamic length data packets compete for the same output port, a first-in-first-out (FIFO) strategy and a round-robin arbitration strategy are used to send each dynamic length data packet.

7. The low-latency data exchange method for a real-time simulation system according to claim 4, characterized in that, The process of performing deterministic parsing on the dynamic length data packet is as follows: Parse the frame header in dynamic length data packets to complete physical layer synchronization and packet integrity verification; The source identifier field is extracted from the dynamic length data packet. The extracted source identifier field is compared with the local routing configuration table uniformly issued by the master node when the task is loaded. If the comparison fails, the dynamic length data packet is discarded. If the comparison succeeds, the sequence number in the dynamic length data packet is parsed to verify the packet sequence continuity. When the sequence number verification passes, the simulation data field in the dynamic length data packet is extracted and sent to the local simulation model calculation engine to complete cross-node state synchronization and joint simulation.

8. The low-latency data exchange method for a real-time simulation system according to claim 1, characterized in that, The real-time simulation system presents a star-shaped physical topology.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the low-latency data exchange method for a real-time simulation system as described in any one of claims 1-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the low-latency data exchange method for a real-time simulation system as described in any one of claims 1-8.

Images