564results about "Pulse shaping" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The invention discloses a power supply output control method and system based on adaptive pulse width adjustment, and relates to the technical field of power supply control, and the method comprises the steps: collecting an analog envelope signal for preprocessing, and generating a probability that an amplitude falls into an interval; establishing a shortest undistorted pulse width reference model, calculating the shortest undistorted pulse width in combination with the probability that the amplitude falls into the interval, correcting the shortest undistorted pulse width, obtaining an adaptive reference pulse width, carrying out pulse edge detection, calculating an integer frequency reduction multiple and a fractional multiple correction factor, and carrying out fractional multiple frequency reduction on effective pulses to obtain a target output frequency; on the basis of the target output frequency, allocation division and allocation verification of the pulse edge are executed, and on the basis of an allocation verification result, weighting operation is executed to generate a voltage value of a step waveform; according to the invention, the distortion rate of the output waveform is reduced, and the frequency division precision and the balance of pulse distribution are remarkably improved, so that the overall energy efficiency and reliability of power supply output control are improved.

The invention discloses a high-precision clock taming and signal shaping method and device for a satellite timing system. The method comprises the following steps of: counting and measuring a reference pulse per second received in real time by using a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to obtain a phase counting deviation sequence of the local high-frequency clock signal relative to the reference pulse per second; inputting the phase counting deviation sequence into the frequency control closed-loop model, analyzing the historical state characteristics of the phase counting deviation sequence, and calculating a frequency adjustment instruction for the local voltage-controlled crystal oscillator; the frequency adjusting instruction is converted into an analog voltage signal, a local voltage-controlled crystal oscillator is driven to adjust the output frequency, and a tamed local high-frequency clock signal is obtained; the tamed local high frequency clock signal is utilized to drive phase warping logic to generate a local pulse per second synchronized with the reference pulse per second. According to the invention, through adaptive closed-loop control and phase regulation, precise taming of crystal oscillator frequency and high-precision shaping of output signals are realized.

The invention provides a driving circuit, a fast charge protocol chip and electronic equipment, and relates to the technical field of power management chips, the circuit comprises a ramp voltage generation circuit and a class AB operational amplifier circuit, the ramp voltage generation circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, and the controllable current source circuit comprises a current branch; the controllable current source circuit obtains a first current and a second current according to the first digital signal, and the magnitude of the first current and the magnitude of the second current are in positive correlation with the number of the current branches; the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal; the clamping circuit clamps the ramp voltage signal according to the first digital signal and the reference voltage to enable the ramp voltage signal to be lower than the reference voltage; the class AB operational amplifier circuit amplifies the ramp voltage signal to obtain a second digital signal. Therefore, the circuit is suitable for wide-range load capacitance, and has a high power supply rejection ratio.

A power converter includes a timing control circuit, an interface, one or more switching circuits and a monitoring circuit. The one or more switching circuits generate one or more pulses in response to one or more timing signals generated by the timing control circuit. The monitoring circuit measures a delay between at least one of the one or more timing signals and at least one of the one or more pulses, and generates an output signal based on the delay. The timing control circuit adjusts the delay obtained by monitoring the output signal.

The invention relates to a buffer and an integrated circuit. The buffer includes: an operational amplifier; the first end of the voltage-voltage feedback network is coupled to the positive phase / negative phase input end of the operational amplifier; the first end of the isolation resistor is coupled to the output end of the buffer; the first group of switches and the second group of switches are controlled to be closed when the first capacitive load is driven, the second group of switches are disconnected when the second capacitive load is driven, and the first group of switches are disconnected and the second group of switches are closed when the second capacitive load is driven; in the first load, the output end of the operational amplifier is coupled to the output end of the buffer through at least one switch in the first group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the buffer through at least one switch in the first group of switches. In the second load, the output end of the operational amplifier is coupled to the second end of the isolation resistor through at least one switch in the second group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the operational amplifier through at least one switch in the second group of switches.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:Mc≥β−γ / β+γ×Mr Mr≤√{square root over (1 / 2πftαβ)}  [Math. 1]where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

A level shifter includes a first buffer circuit, a first capacitor, a second capacitor, a cross-coupled inverter, and a second buffer circuit. The first buffer circuit is configured to drive a first input signal and a second input signal with a first high power supply voltage and a first low power supply voltage to generate a first main driving signal and a second main driving signal. The first capacitor, the second capacitor, and the cross-coupled inverter are configured to generate signals of a first node and a second node based on the first and second main driving signals. The second buffer circuit is configured to drive the signals of the first and second nodes with a second high power supply voltage and a second low power supply voltage to generate a first output signal and a second output signal.

The integrated circuit includes a delay monitor that monitors a delay of the data signal from the digital circuitry by generating a pulse having a width determined by the delay. In some embodiments, a delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal for clocking the data signal. The pulse generator generates a pulse according to the received data signal and the clock signal, wherein a width of the pulse is determined by a delay of the data signal relative to the clock signal. The event generator generates events that are temporally distributed with respect to the clock signal. As a result, the delay may be estimated based on an overlap between the event and the pulse.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.

The utility model belongs to servo driver technical field especially relates to a kind of servo driver non-polarity pulse input filter circuit, the circuit is by pulse input module, isolation and level conversion module, primary pulse shaping logic flip module, primary filter module, secondary controllable filter module, secondary pulse shaping logic flip module and MCU pulse collection and filter control module constitute, the utility model is by being arranged bridge rectifier circuit to make circuit not limit the polarity of signal input, reach the effect of arbitrary polarity input.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

The invention provides a clock signal correction apparatus, a semiconductor apparatus, and a computing system. The clock signal correction apparatus includes: a first clock signal generator configured to generate an internal clock signal in a first mode; a frequency divider configured to generate a plurality of first clock signals having different phases based on the internal clock signal; a calibration circuit configured to generate a first skew code corresponding to a skew between a first clock signal and a second clock signal of the plurality of first clock signals and a second skew code corresponding to a skew between a third clock signal and a fourth clock signal of the plurality of first clock signals; and a skew adjustment circuit configured to adjust phases of a plurality of second clock signals having different phases generated using a clock signal received from an external source based on the first skew code and the second skew code in a second mode different from the first mode.

The invention relates to the technical field of electronics, and discloses a dead time setting circuit, a PCB and a chip, and the dead time setting circuit comprises a high-side input unit, a low-side input unit and a shaping unit; the high-side input unit, the low-side input unit and the shaping unit are electrically connected with one another; the high-side input unit and the low-side input unit carry out delay and logic operation processing on input signals, the input signals can be integrated and optimized in the logic level while dead zone time is set, and a foundation is laid for generating stable pre-drive signals; and then, the shaping unit shapes the pre-drive signal obtained after processing of the two units, so that the instantaneous error level in the pre-drive signal can be effectively eliminated, a stable drive signal is output, and the stability of the drive signal is ensured.

A semiconductor device includes a first and a second output transistor on a high and a low side respectively, a first terminal connected to the connection node between the first and second output transistors, and a second terminal configured to be connected via a bootstrap capacitor to the first terminal. The first output transistor is driven based on a voltage between the first and second terminals. A switching circuit is provided between a terminal fed with a predetermined control supply voltage and the second terminal. The switching circuit includes a first and a second switching element, which are N-channel MOSFETs connected in series. According to the voltage at the first terminal, the first and second switching elements are turned on or off.

An apparatus includes a first D flip-flop including a first data output, a first negative edge-triggered clock input, and a first reset input, and a second D flip-flop including a second data output, a second negative edge-triggered clock input, and a second reset input. The apparatus includes a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output, and the second input of the logic gate coupled to the second data output, in which the output of the logic gate is configured to be a first clock output of the apparatus. A delay circuit of the apparatus includes an output and input, the output of the delay circuit coupled to the first and second reset inputs, and the input of the delay circuit coupled to the output of the logic gate.

The application discloses a time-to-digital converter based on pulse stretching. The time-to-digital converter structure combines frequency multiplication delay locked loop, pulse stretching circuit and calibration circuit, guarantees high resolution, effectively increases the range of the time-to-digital converter, and can reduce the influence of PVT. The calibration circuit has simple structure, low calibration cost, and is suitable for the calibration of the pulse stretching circuit. In addition, the calibration algorithm for the static phase error of the frequency multiplication delay locked loop only needs to increase a 1bit counter, the additional circuit cost is very small, and the influence of the static phase error of the frequency multiplication delay locked loop can be overcome.

An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.

A signal driver circuit includes a pre-driving circuit, a driving signal generating circuit, a main driving circuit, and an output control circuit. The pre-driving circuit is configured to generate a first pre-driving signal and a second pre-driving signal based on an input signal and a clock signal. The driving signal generating circuit is configured to generate a pull-up driving signal and a pull-down driving signal based on the first pre-driving signal, the second pre-driving signal, and a complementary delayed output signal. The main driving circuit is configured to generate an output signal based on the pull-up driving signal and the pull-down driving signal. The complementary delayed output signal is generated by delaying the output signal. The output control circuit is configured to latch the output signal and configured to delay the output signal to generate a delayed output signal and the complementary delayed output signal.

The same mask can be used to create operational amplifiers and comparators, reducing costs. [Solution] The differential circuit (5) comprises a differential input stage (1) configured to receive a differential voltage between an inverting input terminal (Tn) and a non-inverting input terminal (Tp), a gain stage (2) configured to amplify the output of the differential input stage, an output stage (3) configured to receive the signal from the gain stage and output an output signal (OUT), and a first switching circuit (SW11, SW12, SW13) configured to switch the enabled and disabled states of phase compensation elements (C1, C2) included in the output stage based on a switching signal (SW).

An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

The circuit device includes an output terminal, an output transistor, and a gate voltage control circuit. The output transistor is disposed between the first power supply node and the output terminal. After the input signal (TX) transitions from a first logic level to a second logic level, the gate voltage control circuit causes the gate voltage of the output transistor to change at a first time-voltage change rate. After the gate voltage reaches a first determination voltage, the circuit causes the gate voltage to change at a second time-voltage change rate that is smaller than the first time-voltage change rate. After the gate voltage reaches a second determination voltage, the circuit causes the gate voltage to change at a third time-voltage change rate that is larger than the second time-voltage change rate.

To provide a circuit capable of detecting signal level in high accuracy.SOLUTION: A signal detection circuit SD1 includes a signal input circuit SG, a bias circuit BA connected to the signal input circuit SG, a reference voltage generation circuit BL, and a comparing circuit CP connected to the signal input circuit SG and the reference voltage generation circuit BL. The bias circuit BA includes a first constant current source A1 connected to a first power supply P1, and a first diode D1 arranged between the first constant current source A1 and a reference voltage. The signal input circuit SG includes capacitors C1A, C1B and second diodes D2A, D2B. The first diode D1 is diode-matched with the second diodes D2A, D2B. The reference voltage generation circuit BL includes a second constant current source A2 connected to a second power supply P2. The comparing circuit CP detects an AC signal based on level comparison between a signal level VFDC generated by the signal input circuit SG and a reference level VREF generated by the reference voltage generation circuit BL.SELECTED DRAWING: Figure 2

The driving circuit generates a first control signal and a second control signal and outputs the first control signal and the second control signal to respective control electrodes of the first power semiconductor element and the second power semiconductor element which are connected in parallel. The range of the safe operation area of the first power semiconductor element is larger than the range of the safe operation area of the second power semiconductor element. The driving circuit comprises a time delay circuit, a control logic circuit and a buffer. The time delay circuit compares a voltage level of the second control signal with a first reference voltage or compares a drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage according to a comparison result. The first and second reference voltages are associated with temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal according to the first voltage. The buffer generates a first or second control signal according to a logic signal. According to the invention, a relatively large range of a safe working area can be realized.