928results about "Pulse shaping" patented technology

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and / or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

The invention discloses a power supply output control method and system based on adaptive pulse width adjustment, and relates to the technical field of power supply control, and the method comprises the steps: collecting an analog envelope signal for preprocessing, and generating a probability that an amplitude falls into an interval; establishing a shortest undistorted pulse width reference model, calculating the shortest undistorted pulse width in combination with the probability that the amplitude falls into the interval, correcting the shortest undistorted pulse width, obtaining an adaptive reference pulse width, carrying out pulse edge detection, calculating an integer frequency reduction multiple and a fractional multiple correction factor, and carrying out fractional multiple frequency reduction on effective pulses to obtain a target output frequency; on the basis of the target output frequency, allocation division and allocation verification of the pulse edge are executed, and on the basis of an allocation verification result, weighting operation is executed to generate a voltage value of a step waveform; according to the invention, the distortion rate of the output waveform is reduced, and the frequency division precision and the balance of pulse distribution are remarkably improved, so that the overall energy efficiency and reliability of power supply output control are improved.

A control method of a hybrid power switch having at least a first switching device connected in parallel with a second switching device is provided. A first gate signal is provided to the first switching device for turning on and turning off the first switching device. A second gate signal is provided to the second switching device for turning on and turning off the second switching device. A first delay time is stablished between the turning on of the first switching device and the turning on of the second switching device, and a second delay time is established between the turning off of the first switching device and the turning off of the second switching device. The temperature of the first switching device is determined, and at least one of the first and second delay times is modified depending on such temperature.

The invention provides a high-integration-level signal reading module for a neutron proportional counter tube, and belongs to the technical field of neutron detection, the high-integration-level signal reading module comprises stacked double-layer circuit boards, and the upper circuit board and the lower circuit board are connected through pin interfaces; the upper circuit board is provided with a signal processing circuit which is used for reading, amplifying, discriminating and shaping signals of the neutron proportional counter tube. The lower-layer circuit board is provided with a positive and negative dual-power-supply support circuit which provides + / -3.3 V power supply support for the signal processing circuit of the upper-layer circuit board. The module supplies power through the lower-layer power panel, and the lower-layer circuit board supplies positive and negative power to the upper-layer circuit board after completing power conversion. Signals are input through the IPX interface of the upper-layer circuit board and are output through the other IPX interface after being processed. The charge sensitive pre-amplifier, the broadband voltage amplifier, the pulse discriminator circuit, the pulse shaping circuit and the power management module are integrated in the same module, so that the real integrated design is realized.

The invention discloses a high-precision clock taming and signal shaping method and device for a satellite timing system. The method comprises the following steps of: counting and measuring a reference pulse per second received in real time by using a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to obtain a phase counting deviation sequence of the local high-frequency clock signal relative to the reference pulse per second; inputting the phase counting deviation sequence into the frequency control closed-loop model, analyzing the historical state characteristics of the phase counting deviation sequence, and calculating a frequency adjustment instruction for the local voltage-controlled crystal oscillator; the frequency adjusting instruction is converted into an analog voltage signal, a local voltage-controlled crystal oscillator is driven to adjust the output frequency, and a tamed local high-frequency clock signal is obtained; the tamed local high frequency clock signal is utilized to drive phase warping logic to generate a local pulse per second synchronized with the reference pulse per second. According to the invention, through adaptive closed-loop control and phase regulation, precise taming of crystal oscillator frequency and high-precision shaping of output signals are realized.

The invention provides a driving circuit, a fast charge protocol chip and electronic equipment, and relates to the technical field of power management chips, the circuit comprises a ramp voltage generation circuit and a class AB operational amplifier circuit, the ramp voltage generation circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, and the controllable current source circuit comprises a current branch; the controllable current source circuit obtains a first current and a second current according to the first digital signal, and the magnitude of the first current and the magnitude of the second current are in positive correlation with the number of the current branches; the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal; the clamping circuit clamps the ramp voltage signal according to the first digital signal and the reference voltage to enable the ramp voltage signal to be lower than the reference voltage; the class AB operational amplifier circuit amplifies the ramp voltage signal to obtain a second digital signal. Therefore, the circuit is suitable for wide-range load capacitance, and has a high power supply rejection ratio.

A power converter includes a timing control circuit, an interface, one or more switching circuits and a monitoring circuit. The one or more switching circuits generate one or more pulses in response to one or more timing signals generated by the timing control circuit. The monitoring circuit measures a delay between at least one of the one or more timing signals and at least one of the one or more pulses, and generates an output signal based on the delay. The timing control circuit adjusts the delay obtained by monitoring the output signal.

An active eye open monitor calibration apparatus and method for active eye open monitor calibration are provided. A reference clock signal and an eye open monitor clock signal are received and a calibration selecting signal is used to control whether the reference clock signal samples the eye open monitor clock signal. An indicator signal is output and received by a phase indicating determination circuit for performing a calibration flow and accordingly calculating a phase offset signal. The eye open monitor clock is corrected based on the phase offset signal, such that a calibrated eye open monitor clock signal is synchronously in phase with the reference clock signal. By employing the proposed eye open monitor calibration apparatus and method thereof, the invention is effective in achieving phase synchronization for an eye open monitor clock signal in related to its reference clock signal, solving the phase mismatch in the related arts.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

The invention relates to a buffer and an integrated circuit. The buffer includes: an operational amplifier; the first end of the voltage-voltage feedback network is coupled to the positive phase / negative phase input end of the operational amplifier; the first end of the isolation resistor is coupled to the output end of the buffer; the first group of switches and the second group of switches are controlled to be closed when the first capacitive load is driven, the second group of switches are disconnected when the second capacitive load is driven, and the first group of switches are disconnected and the second group of switches are closed when the second capacitive load is driven; in the first load, the output end of the operational amplifier is coupled to the output end of the buffer through at least one switch in the first group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the buffer through at least one switch in the first group of switches. In the second load, the output end of the operational amplifier is coupled to the second end of the isolation resistor through at least one switch in the second group of switches, and the second end of the voltage-voltage feedback network is coupled to the output end of the operational amplifier through at least one switch in the second group of switches.

A ramp driver includes a ramp generator for generating a reference ramp signal, and a ramp delayer for sequentially outputting ramp signals based on the reference ramp signal, and including delay blocks including k output terminals, k being an integer greater than or equal to 2, wherein the delay blocks include k delay circuits sequentially connected to each other, respectively connected to the output terminals, and configured to receive an input ramp signal from a previous one of the delay circuits, receive an input gate clock signal from a previous delay circuit, output an output ramp signal by delaying the input ramp signal, and output an output gate clock signal by inverting the input gate clock signal.

Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; a ground reference; a transformer having a first transformer ratio, the first transformer comprising: a primary winding coupled to the first voltage source and the ground reference; and a secondary winding having a first end and a second end, wherein the first end is coupled to the ground reference, and the second end is configured to be coupled to a load through a common node; and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator generally also includes one or more additional voltage stages coupled to a load through the common node.

The invention discloses a digital signal controlled phase interpolator, which comprises a digital control module, a phase rotator, a mirror image phase rotator and a clock selection module, and is characterized in that the digital control module receives a phase discrimination result from a phase discriminator and obtains a control signal, and the phase discrimination result comprises a high-level Early signal and a low-level Late signal; the phase rotator receives the four-phase orthogonal clock signal and generates a first clock signal with a fixed phase according to the control signal, and the mirror image phase rotator receives the four-phase orthogonal clock signal and generates a second clock signal with a fixed phase according to the control signal; the clock selection module selectively outputs the first clock signal or the second clock signal. The digital control module is adopted to control the phase interpolator, the octagonal phase rotator is adopted to realize high linearity of phase interpolation, and the mirror image phase rotator is adopted to effectively eliminate clock jitter generated during conversion of a phase interpolation quadrant.

The invention discloses a nanosecond steep pulse excitation system and a nanosecond steep pulse excitation method. The nanosecond steep pulse excitation system comprises a high-voltage pulse generation module, a controller, an impedance detection module and a treatment electrode, the high-voltage pulse generation module is used for receiving a control signal monitored by the controller and outputting a high-voltage pulse to the treatment electrode; the impedance detection module comprises a measuring electrode, tissue impedance data are collected through the measuring electrode, and the impedance data are dynamically fed back to the controller; the controller dynamically adjusts parameters of the high-voltage pulse generation module according to impedance data to form closed-loop control, the Marx circuit is optimized, the high-voltage pulse generation efficiency is high, nanosecond-level accurate triggering is achieved through embedded control, effective deposition of high-frequency energy is ensured, transient voltage spikes are reduced, impedance changes are detected in real time through the impedance detection module, and the control precision is improved. The pulse width or amplitude is dynamically adjusted, pulse parameters are adjusted in real time based on impedance changes, and excessive ablation or insufficient treatment is avoided.

The present application relates to the technical field of radio frequency. Provided are an operating frequency adjustment method for a radio-frequency circuit, and an operating frequency control circuit and a radio-frequency power supply device. The operating frequency adjustment method for a radio-frequency circuit comprises: controlling a radio-frequency circuit to provide output at different operating frequencies to a load; measuring circuit parameters of the radio-frequency circuit during output at each operating frequency; on the basis of the circuit parameters of the radio-frequency circuit during output at each operating frequency, performing calculation to obtain a resonant frequency of the radio-frequency circuit; and adjusting an operating frequency of the radio-frequency circuit to the resonant frequency. The present application can quickly determine a resonant frequency of a radio-frequency circuit, and adjust an operating frequency of the radio-frequency circuit to the resonant frequency.

An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

The invention discloses a clock duty ratio adjusting circuit. The clock duty ratio adjusting circuit comprises an integrator, an adjusting control unit, a charging and discharging unit, a first shaping unit and a phase detection unit. The integrator is used for generating a control signal based on a clock output signal and a reference signal; the adjusting control unit is used for generating an adjusting signal based on power supply voltage and a control signal; the charging and discharging unit is used for generating a charging and discharging signal based on the clock input signal and adjusting the charging and discharging signal based on the adjusting signal; the first shaping unit is used for shaping the charging and discharging signal to generate a shaped signal; the phase detection unit is used for performing phase detection on the clock input signal and the shaping signal to generate a clock output signal. According to the clock duty ratio adjusting circuit, clock signals which are stable in duty ratio and can be well subjected to self-adaptive adjustment can be obtained.

A power integrated circuit comprising at least one III-nitride high voltage high-electron-mobility transistor (power HEMT), the power HEMT comprising a heterojunction formed between a GaN layer and an AlGaN layer, and a slew rate protection circuit. The slew rate protection circuit comprising a clamping transistor electrically connected between a gate terminal and a source terminal of the power HEMT, and a detection circuit electrically connected between a drain terminal and the source terminal of the power HEMT, wherein an output of the detection circuit is electrically connected to a gate terminal of the clamping transistor. The detection circuit is configured to output a signal to turn-on the clamping transistor when a transient voltage greater than a threshold transient voltage is observed across the drain and the source terminals of the power HEMT.

The present invention relates to the technical field of signal analysis, and specifically discloses an automatic digital pole-zero cancellation method; on the host computer operation software, a default threshold is set for pulse signal acquisition, and a default starting pole-zero parameter value is set; the host computer operation software sends a command to the digital pulse amplitude analyzer to collect the pulse waveform after pole-zero once; it is judged whether the pulse tail of the received waveform is lower than the baseline value; if the pulse tail is lower than the baseline value, the pole-zero parameter value is adjusted; if the pulse tail is not lower than the baseline value, it is judged whether the current adjustment is the minimum number of digits of the pole-zero parameter; if the current adjustment is not the minimum number of digits of the pole-zero parameter, the current adjustment digit is changed, and then the pole-zero parameter value is adjusted; if the current adjustment is the minimum number of digits of the pole-zero parameter, the optimal pole-zero parameter value is obtained, and the automatic pole-zero process ends; compared with the traditional manual operation and discrimination, the present invention has multiple advantages: fast, good consistency, low requirements for personnel, and realization of automatic linkage.

A receiver circuit is configured to generate, based on a clock signal, a first output signal by differentially amplifying an input signal and a reference voltage and to generate, based on a complementary clock signal, a second output signal by differentially amplifying the input signal and the reference voltage. The receiver circuit is configured to generate a first delay output signal and a second delay output signal by delaying the first output signal and the second output signal. The receiver circuit is configured to variably delay the first output signal based on the first output signal and the reference voltage and to variably delay the second output signal based on the second output signal and the reference voltage.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:Mc≥β−γ / β+γ×Mr Mr≤√{square root over (1 / 2πftαβ)}  [Math. 1]where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.