1652results about "Pulse shaping" patented technology

An image sensor, a level shifter circuit, and an operation method thereof are provided. The image sensor includes a pixel circuit and a pixel driving circuit. The pixel driving circuit includes first, second, third, fourth, fifth, and sixth transistors. A first terminal of the first transistor is coupled to a first voltage. A first terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to a control terminal of the first transistor and a second terminal of the first transistor. A first terminal of the third transistor is coupled to the second terminal of the first transistor, and a second terminal of the third transistor is coupled to a ground voltage. A first terminal of the fourth transistor is coupled to a second terminal of the second transistor and an output terminal.

Disclosed are a method and an apparatus of digital feedback based adaptive delay time control for a high efficiency active rectifier. According to the present invention, provided is an apparatus for digital feedback based adaptive delay time control, which adaptively compensates a driving delay of a switch by controlling a time of a delay circuit through a digital feedback-based compensation technique, and operate the switch at an appropriate timing in spite of changes in operation environments such as an input voltage and a load to increase the efficiency of an AC-DC rectifier.

Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.

A circuit includes a high-side driver having a high-side slew control input, a high-side drive input and a high-side drive output. A low-side driver has a low-side slew control input, a low-side drive input and a low-side drive output. Drive control circuitry has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuitry is configured to provide a slew control signal at the slew control output. The high-side and / or low-side driver is configured to modulate a slew rate of a drive signal at a respective drive output thereof based on the slew control signal.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

The invention provides a programmable pulse generation device and method, the device comprises a clock generator, a pulse synthesizer and a pattern generator, the pulse synthesizer comprises a multi-path pulse generator, a gating signal adjuster, a switch controller and an arbitrary pulse generator; the clock generator is used for generating M paths of high-frequency clock signals and N paths of low-frequency clock signals; the multi-path pulse generator is used for generating two groups of pulse signals with the same quantity at a set interval; the pattern generator is used for storing enabling control data corresponding to the two groups of pulse signals; the gating signal adjuster is used for generating M paths of gating control signals; the switch controller is used for generating X switch control signal sources; and the arbitrary pulse generator is used for respectively selecting one or more paths of required pulse signals from the two groups of pulse signals for enabling control, and generating high-speed and high-resolution pulse waveforms through exclusive-OR operation. According to the invention, high-speed and high-resolution pulse waveforms with flexibly adjustable pulse widths can be output.

The invention relates to a quarter-rate architecture SerDes clock path and a serialization circuit. The quarter-rate architecture SerDes clock path comprises a PLL (Phase Locked Loop) used for generating a differential clock signal consisting of two signals with opposite phases; the four-phase clock signal generation module is used for generating four four-phase clock signals with the phase difference of 90 degrees in sequence according to the differential clock signal; the retiming module is used for performing delay processing on the input four-way parallel data according to the four-phase clock signal, so that the delay interval among the input four-way parallel data is 1UI; the 1UI PULSE generation module is used for synthesizing clock signals of two adjacent phases in four-phase clock signals of which the phase difference is 90 degrees in sequence into clock signals with 1UI pulse width; and 4, the 1MUX module is used for synthesizing the four paths of delayed parallel data into one path of serial data according to the clock signal of the 1UI pulse width synthesized by the 1UI PULSE generation module.

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

A PUF circuit based on the threshold loss of MOSFETs comprises N stages of delay units and an arbiter. Each stage of delay unit comprises six inverters and four MOS transistors, wherein the four MOS transistors are all PMOS transistors or NMOS transistors. Each path in each stage of delay unit uses only one PMOS or NMOS transistor and does not use a transmission gate formed by a PMOS transistor and an NMOS transistor. Therefore, it reduces hardware cost. Each MOS transistor on the transmission path has a threshold loss, PMOS and NMOS transistors in a third inverter and a sixth inverter are in an on-state, and output terminals of the third inverter and the sixth inverter will be charged to a high level or discharged to a low level, thus greatly increasing a delay difference between two square signals and enhancing randomness.

A disclosed switching apparatus, such as a circuit breaker, includes a transistor switch circuit connected between a power input terminal and a load terminal, and, connected to the power input terminal and bypassing the transistor switch circuit, a switchable bypass leg that is optically switched by a series-connected photoconductive semiconductor switch (PCSS). The transistor switch circuit includes at least one cascade of three or more series-connected transistors, and at least one resistor network configured to divide a voltage from a voltage source across a cascade of series-connected transistors. Operating the switch apparatus includes detecting whether a sensed electric current is in a fault condition, opening the transistor switch circuit upon detecting a fault condition, and then closing the PCSS so that the electric current is diverted onto a switchable bypass path. The opening of the transistor switch circuit comprises turning OFF a normally-ON transistor switch circuit.

The invention provides a dynamic latch, comprising an input terminal for inputting a first data; an output terminal for outputting a second data; a clock signal terminal for supplying a clock signal; a data transmission unit for transmitting the first data under control of the clock signal; and a data output unit for converting the first data into the second data. The data transmission unit and the data output unit are sequentially connected in series between the input terminal and the output terminal, and a node is provided between the data transmission unit and the data output unit. The dynamic latch further comprises a data retention unit electrically connected to the node. The retention time of data can be effectively extended, thereby improving data security and accuracy.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

A phase adjustment circuit includes a clock generation unit (1) which generates a sinusoidal differential clock signal; a variable amplifier (2) which receives a differential clock signal output from the clock generation unit (1) as an input, outputs an amplitude-adjusted differential clock signal, and simultaneously outputs an amplitude-adjusted in-phase signal; an adding unit (3) which adds an in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier (2); a differential transmission line (4) which transmits the differential signal output from the adding unit (3); and a terminal circuit (5) which terminates the differential transmission line (4).

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

A comparator operating by receiving a supply of a first voltage (VDD / VSS) and a second voltage (VSS / VDD), the comparator comprising: a differential amplifier circuit (110) connected to a first power supply node (Np / Ns) that supplies the first voltage via a first and a second node (N1, N2), and which generates a first current (I1) and a second current (I2) in the first node and in the second node, respectively, wherein the first current and the second current have a current difference obtained by amplifying a voltage difference between an input voltage (Vin) and a reference voltage (VREF) predetermined between the first and the second voltage; a current source circuit (130) connected to the differential amplifier circuit via a third node (N3) between the first power supply node and a second power supply node (Np / Ns) that supplies the second voltage.connected in series and generating a third current (I3) which is a sum of the first and second currents at the third node; an output stage (170) connected between an output node (N6) and the first power supply node and having a current driving force to generate a first output current (I6p) proportional to the first current between the first power supply node and the output node; a current conversion circuit (140) having a current driving force to generate a second output current (I4n) proportional to the second current between the second power supply node and the output node; a minimum selection circuit (150) connected between a complementary output node (N5) and the first power supply node and causing the complementary output node to generate a current (I5) proportional to a minimum current of the first and second currents (I6p,I4n); and a latching circuit (160) connected between the output node and the complementary output node and the second power supply node, wherein the latching circuit performs a reset operation in which both the output node and the complementary output node are electrically connected to the second power supply node in response to a reset signal (RST), and performs a latching operation with positive feedback in which a change generated in the output node is amplified from the second voltage to the first voltage when a high-low relationship between the input voltage and the reference voltage is reversed from a reset cancellation time, while the output node and the complementary output node are electrically disconnected from the second power supply node during circuit operation after the reset cancellation.and sets the voltage at the output node to the first voltage, while the voltage at the complementary output node is set to the second voltage until the reset signal is next input.

The invention provides an impedance matcher and a radio frequency power supply system. The impedance matcher comprises a first inductor and a first capacitor module. The first inductor and the first capacitor module are both used for being connected with an output path of a radio frequency power supply, and the first inductor and the first capacitor module respectively have a first matching value and a second matching value; the first capacitor module at least comprises a first capacitor and a compensation inductor, the first capacitor is connected with an output path of the radio frequency power supply, the compensation inductor is connected with the first capacitor, the compensation inductor is an inductor with an adjustable length, and the compensation inductor has an adjustable compensation inductance value by adjusting the length of the compensation inductor; the second matching value is at least an overall matching value of the compensation inductance value and the capacitance value of the first capacitor; the second matching value is capacitive and is different at least according to different compensation inductance values; wherein the first matching value of the first inductor and the second matching value of the first capacitor module are used for performing impedance matching on the radio frequency power supply and the load. According to the invention, impedance matching can be rapidly realized.

A reference system is provided for generating a clock signal with a tunable noise pedestal for driving a signal generator. The reference system includes a reference source configured to generate a reference signal and a multiplier chain, including a noise pedestal generator. The noise pedestal generator includes a noise pedestal attenuator configured to attenuate the reference signal to degrade a noise floor of the reference signal, a VGA configured to adjust the attenuated reference signal to a desired signal level, a bandpass filter configured to filter out excess noise from the adjusted reference signal to form a noise pedestal, and a switch arrangement configured to selectively input the reference signal to a first path including the noise pedestal attenuator and the VGA, and a second path bypassing the noise pedestal attenuator and the VGA. The clock signal includes the noise pedestal when the first path is selected.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The present disclosure provides an approach that determines a pulse frequency modulation (PFM) period of a buck regulator. The PFM period comprises a first charging stage and a first discharging stage, and wherein the buck regulator switches from the first discharging stage to the first charging stage based on comparing a feedback voltage to a low threshold voltage. The approach generates a pseudo random pulse at a pseudo random period, wherein the pseudo random period is independent from the low threshold voltage. Then, the approach initiates a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND / OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

The invention provides a detector signal processing circuit and a detector signal processing method, which are applied to the field of nuclear technology application, and the detector signal processing circuit comprises a detector used for generating a detection signal; the pulse mode circuit is connected with the detector and is used for performing pulse shaping on the detection signal to obtain a pulse signal; the high-order mode circuit comprises a plurality of Campbell modules connected in parallel, the input ends of the Campbell modules are connected with the detector, and the Campbell modules are used for converting detection signals into first-order signals; the current mode circuit is connected with the detector; the current module is used for converting a detection signal into a current signal; the control module is connected with the pulse mode circuit, the current mode circuit and the output end of each Campbell module. According to the embodiment of the invention, the accuracy of a neutron flux detection result can be improved, and the measurement range of the detector is expanded.

Techniques are provided for calibrating a signal current in a radio frequency signal generator system, such as an arbitrary waveform generator system. An apparatus includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and / or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

The invention discloses a pulse switch parameter updating method, electronic equipment and a medium. The pulse switch parameter updating method comprises the following steps: setting a switch period reference value; obtaining a current switching period, a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal; respectively judging a first action and a second action according to a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal, and setting a first mark position; when the first flag bit is detected, the switching period, the duty ratio of the first PWM signal, the duty ratio of the second PWM signal, the first action corresponding to the first PWM signal and the second action corresponding to the second PWM signal are updated at the next target time point through timing of a cycle timer; wherein the target time point is a time point corresponding to the trough of the triangular carrier of the carrier counter of the PWM wave in the current switching period; and after updating is completed, the first flag bit is set, and the cycle timer is reset.

A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.

The invention discloses a pulse generation circuit, a driving chip and electronic equipment, and belongs to the technical field of electronic equipment. The pulse generation circuit comprises a square wave input end, a first pulse unit and a second pulse unit. The first pulse unit comprises a first delay module and a first logic processing module; the first delay module is used for performing delay processing on the falling edge of the square wave signal to generate a first delay signal; the first logic processing module is used for outputting a first pulse signal according to the first delay signal; the second pulse unit comprises a second delay module and a second logic processing module; the second delay module is used for performing delay processing on the rising edge of the square wave signal to generate a second delay signal; the second logic processing module is used for outputting a second pulse signal according to the second delay signal. The pulse width of the first pulse signal and the pulse width of the second pulse signal are narrower than the pulse width of the square wave signal, and conversion from the square wave signal to the pulse signal with the narrower pulse width is achieved.

The invention discloses a power supply output control method and system based on adaptive pulse width adjustment, and relates to the technical field of power supply control, and the method comprises the steps: collecting an analog envelope signal for preprocessing, and generating a probability that an amplitude falls into an interval; establishing a shortest undistorted pulse width reference model, calculating the shortest undistorted pulse width in combination with the probability that the amplitude falls into the interval, correcting the shortest undistorted pulse width, obtaining an adaptive reference pulse width, carrying out pulse edge detection, calculating an integer frequency reduction multiple and a fractional multiple correction factor, and carrying out fractional multiple frequency reduction on effective pulses to obtain a target output frequency; on the basis of the target output frequency, allocation division and allocation verification of the pulse edge are executed, and on the basis of an allocation verification result, weighting operation is executed to generate a voltage value of a step waveform; according to the invention, the distortion rate of the output waveform is reduced, and the frequency division precision and the balance of pulse distribution are remarkably improved, so that the overall energy efficiency and reliability of power supply output control are improved.