1196results about "Pulse shaping" patented technology

Disclosed are a method and an apparatus of digital feedback based adaptive delay time control for a high efficiency active rectifier. According to the present invention, provided is an apparatus for digital feedback based adaptive delay time control, which adaptively compensates a driving delay of a switch by controlling a time of a delay circuit through a digital feedback-based compensation technique, and operate the switch at an appropriate timing in spite of changes in operation environments such as an input voltage and a load to increase the efficiency of an AC-DC rectifier.

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

Systems and methods for optimizing a pipeline are described. A system can generate at least one pair of single flux quantum (SFQ) clock signals based on a stream of SFQ pulses. Each pair of SFQ clock signals can include a first SFQ clock signal and a second SFQ clock signal that is out of phase with the first SFQ clock signal. The second SFQ clock signal can have the same frequency as the first SFQ clock signal. The system can define, for each pair of SFQ clock signals, a first clock cycle and a second clock cycle based on the first SFQ clock signal and the second SFQ clock signal. The second clock cycle can be greater than the first clock cycle. The system can assign the first and second clock cycles to different stages of a pipeline based on delays by the different stages.

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

The invention provides a dynamic latch, comprising an input terminal for inputting a first data; an output terminal for outputting a second data; a clock signal terminal for supplying a clock signal; a data transmission unit for transmitting the first data under control of the clock signal; and a data output unit for converting the first data into the second data. The data transmission unit and the data output unit are sequentially connected in series between the input terminal and the output terminal, and a node is provided between the data transmission unit and the data output unit. The dynamic latch further comprises a data retention unit electrically connected to the node. The retention time of data can be effectively extended, thereby improving data security and accuracy.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

A phase adjustment circuit includes a clock generation unit (1) which generates a sinusoidal differential clock signal; a variable amplifier (2) which receives a differential clock signal output from the clock generation unit (1) as an input, outputs an amplitude-adjusted differential clock signal, and simultaneously outputs an amplitude-adjusted in-phase signal; an adding unit (3) which adds an in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier (2); a differential transmission line (4) which transmits the differential signal output from the adding unit (3); and a terminal circuit (5) which terminates the differential transmission line (4).

A current comparator includes: a first capacitor having a first end coupled to a first input signal; a second capacitor having a first end coupled to a second input signal; a first transistor having a control electrode coupled to the second end of the first capacitor; and a third transistor having a control electrode coupled to the second end of the second capacitor. The first current electrodes of the first and second transistors are coupled, and the second current electrodes of the first and second transistors are coupled to the first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled to the second circuit node via a third capacitor. A set of auto-zero switches selectively shorts the control electrode of the first transistor and the second current electrode in response to an auto-zero control signal, and selectively shorts the control electrode of the second transistor and the second current electrode.

A reference system is provided for generating a clock signal with a tunable noise pedestal for driving a signal generator. The reference system includes a reference source configured to generate a reference signal and a multiplier chain, including a noise pedestal generator. The noise pedestal generator includes a noise pedestal attenuator configured to attenuate the reference signal to degrade a noise floor of the reference signal, a VGA configured to adjust the attenuated reference signal to a desired signal level, a bandpass filter configured to filter out excess noise from the adjusted reference signal to form a noise pedestal, and a switch arrangement configured to selectively input the reference signal to a first path including the noise pedestal attenuator and the VGA, and a second path bypassing the noise pedestal attenuator and the VGA. The clock signal includes the noise pedestal when the first path is selected.

A reconfigurable, for example with time, network switch matrix coupling switch charge circuits representing multiply and add circuits (MACs) and neurons (MACs with activations) capable of accepting and outputting proportional to charge pulses through crossbars within said network, said crossbars controlled by local controllers and higher level controllers to setup said crossbar communications.

The present disclosure provides an approach that determines a pulse frequency modulation (PFM) period of a buck regulator. The PFM period comprises a first charging stage and a first discharging stage, and wherein the buck regulator switches from the first discharging stage to the first charging stage based on comparing a feedback voltage to a low threshold voltage. The approach generates a pseudo random pulse at a pseudo random period, wherein the pseudo random period is independent from the low threshold voltage. Then, the approach initiates a transition from a second discharging stage to a second charging stage based on the pseudo random pulse.

A circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

The invention provides a detector signal processing circuit and a detector signal processing method, which are applied to the field of nuclear technology application, and the detector signal processing circuit comprises a detector used for generating a detection signal; the pulse mode circuit is connected with the detector and is used for performing pulse shaping on the detection signal to obtain a pulse signal; the high-order mode circuit comprises a plurality of Campbell modules connected in parallel, the input ends of the Campbell modules are connected with the detector, and the Campbell modules are used for converting detection signals into first-order signals; the current mode circuit is connected with the detector; the current module is used for converting a detection signal into a current signal; the control module is connected with the pulse mode circuit, the current mode circuit and the output end of each Campbell module. According to the embodiment of the invention, the accuracy of a neutron flux detection result can be improved, and the measurement range of the detector is expanded.

Techniques are provided for calibrating a signal current in a radio frequency signal generator system, such as an arbitrary waveform generator system. An apparatus includes a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured to measure a first current in a first signal path of the radio frequency signal generator and to measure a second current in a second signal path of the radio frequency signal generator during a calibration process. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct an imbalance between the measured first current and the measured second current.

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and / or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

The invention discloses a pulse switch parameter updating method, electronic equipment and a medium. The pulse switch parameter updating method comprises the following steps: setting a switch period reference value; obtaining a current switching period, a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal; respectively judging a first action and a second action according to a first duty ratio of the first PWM signal and a second duty ratio of the second PWM signal, and setting a first mark position; when the first flag bit is detected, the switching period, the duty ratio of the first PWM signal, the duty ratio of the second PWM signal, the first action corresponding to the first PWM signal and the second action corresponding to the second PWM signal are updated at the next target time point through timing of a cycle timer; wherein the target time point is a time point corresponding to the trough of the triangular carrier of the carrier counter of the PWM wave in the current switching period; and after updating is completed, the first flag bit is set, and the cycle timer is reset.

The invention discloses a power supply output control method and system based on adaptive pulse width adjustment, and relates to the technical field of power supply control, and the method comprises the steps: collecting an analog envelope signal for preprocessing, and generating a probability that an amplitude falls into an interval; establishing a shortest undistorted pulse width reference model, calculating the shortest undistorted pulse width in combination with the probability that the amplitude falls into the interval, correcting the shortest undistorted pulse width, obtaining an adaptive reference pulse width, carrying out pulse edge detection, calculating an integer frequency reduction multiple and a fractional multiple correction factor, and carrying out fractional multiple frequency reduction on effective pulses to obtain a target output frequency; on the basis of the target output frequency, allocation division and allocation verification of the pulse edge are executed, and on the basis of an allocation verification result, weighting operation is executed to generate a voltage value of a step waveform; according to the invention, the distortion rate of the output waveform is reduced, and the frequency division precision and the balance of pulse distribution are remarkably improved, so that the overall energy efficiency and reliability of power supply output control are improved.

A control method of a hybrid power switch having at least a first switching device connected in parallel with a second switching device is provided. A first gate signal is provided to the first switching device for turning on and turning off the first switching device. A second gate signal is provided to the second switching device for turning on and turning off the second switching device. A first delay time is stablished between the turning on of the first switching device and the turning on of the second switching device, and a second delay time is established between the turning off of the first switching device and the turning off of the second switching device. The temperature of the first switching device is determined, and at least one of the first and second delay times is modified depending on such temperature.

The invention belongs to the technical field of photon counting imaging, and particularly relates to a quasi-Gaussian pulse forming method based on cubic spline interpolation. Comprising the following steps: S1, performing pole-zero processing on an exponential decay signal to obtain a pole-zero cancellation signal; s2, fitting the pole zero cancellation signal to obtain a fitting parameter; solving the pole-zero cancellation signal based on a deconvolution recursion formula to obtain a deconvolution signal; s3, cubic spline interpolation fitting calculation is carried out on the standard Gaussian window, and an interpolation curve formula set of the Gaussian pulse shape is designed; s4, calculating the interpolation curve formula group to obtain a forming transfer function recursion formula; and S5, inputting the deconvolution signal into a forming transfer function recursion formula, and outputting a quasi-Gaussian forming signal. The method is high in universality, high in stability, adjustable in parameter and flexible in design.

An integrated circuit (IC) includes a tristatable output buffer having a control input. The IC includes an input buffer having a buffer output. The IC further includes a delay circuit having a delay circuit input, a first delay circuit output, and a second delay circuit output. The delay circuit input is coupled to the buffer output. The IC also includes a tristate circuit coupled to the first delay circuit output and to the second delay circuit output. The tristate circuit having a tristate circuit output coupled to the control input.

The invention provides a high-integration-level signal reading module for a neutron proportional counter tube, and belongs to the technical field of neutron detection, the high-integration-level signal reading module comprises stacked double-layer circuit boards, and the upper circuit board and the lower circuit board are connected through pin interfaces; the upper circuit board is provided with a signal processing circuit which is used for reading, amplifying, discriminating and shaping signals of the neutron proportional counter tube. The lower-layer circuit board is provided with a positive and negative dual-power-supply support circuit which provides + / -3.3 V power supply support for the signal processing circuit of the upper-layer circuit board. The module supplies power through the lower-layer power panel, and the lower-layer circuit board supplies positive and negative power to the upper-layer circuit board after completing power conversion. Signals are input through the IPX interface of the upper-layer circuit board and are output through the other IPX interface after being processed. The charge sensitive pre-amplifier, the broadband voltage amplifier, the pulse discriminator circuit, the pulse shaping circuit and the power management module are integrated in the same module, so that the real integrated design is realized.

The invention discloses a high-precision clock taming and signal shaping method and device for a satellite timing system. The method comprises the following steps of: counting and measuring a reference pulse per second received in real time by using a local high-frequency clock signal output by a local voltage-controlled crystal oscillator to obtain a phase counting deviation sequence of the local high-frequency clock signal relative to the reference pulse per second; inputting the phase counting deviation sequence into the frequency control closed-loop model, analyzing the historical state characteristics of the phase counting deviation sequence, and calculating a frequency adjustment instruction for the local voltage-controlled crystal oscillator; the frequency adjusting instruction is converted into an analog voltage signal, a local voltage-controlled crystal oscillator is driven to adjust the output frequency, and a tamed local high-frequency clock signal is obtained; the tamed local high frequency clock signal is utilized to drive phase warping logic to generate a local pulse per second synchronized with the reference pulse per second. According to the invention, through adaptive closed-loop control and phase regulation, precise taming of crystal oscillator frequency and high-precision shaping of output signals are realized.

A high frequency amplifier includes an asymmetrical Doherty amplifier having a carrier amplifier, a peak amplifier, a branch circuit, and a phase adjusting circuit, a driver amplifier, and a base member mounting a first circuit board mounting the driver amplifier, the carrier amplifier, and the peak amplifier and a second circuit board mounting the circuits. The branch circuit divides a path of a RF signal into input paths of the peak and carrier amplifiers. The driver amplifier, the carrier amplifier, and the peak amplifier have rear surfaces in contact with the base member. The electrical length from the output terminal of the driver amplifier to the input terminal of the peak amplifier, when converted based on a phase of the signal, is from (2n+1)×π−π / 4 to (2n+1)×π+π / 4, where n is an integer greater than or equal to zero.

This disclosure describes systems, methods, and apparatus for generating a control signal for one or more actuators that is adjusted from a control signal dictated by setpoints, where the adjustment accounts for predicted delays and amplitude errors. More specifically, cross correlation between measurements of the actuator(s) outputs and time-shifted setpoints can be optimized for a time-shift that minimizes the cross correlation. The time-shifted setpoints along with the measurements can then be used to determine an amplitude difference and to remove noise from the amplitude difference. Dynamic uncertainty can then be found from this denoised data set and further optionally used to find the noise that was removed. The time delay, noise, and dynamic uncertainty can be used to preemptively adjust the control signal.

A circuit for signal transmission, memory, and method for signal transmission are provided. The circuit includes: a signal processing circuit, configured to receive an input first signal, obtain a second signal by processing the first signal in a preset processing manner, and take the second signal as an output signal of the signal processing circuit; and a selection circuit, configured to receive the input first signal, the second signal and a control signal, and take the first signal or the second signal as an output signal of the selection circuit according to the control signal.

A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

The invention provides a driving circuit, a fast charge protocol chip and electronic equipment, and relates to the technical field of power management chips, the circuit comprises a ramp voltage generation circuit and a class AB operational amplifier circuit, the ramp voltage generation circuit comprises a controllable current source circuit, a first capacitor and a clamping circuit, and the controllable current source circuit comprises a current branch; the controllable current source circuit obtains a first current and a second current according to the first digital signal, and the magnitude of the first current and the magnitude of the second current are in positive correlation with the number of the current branches; the first capacitor charges itself according to the first current and discharges itself according to the second current to obtain a ramp voltage signal; the clamping circuit clamps the ramp voltage signal according to the first digital signal and the reference voltage to enable the ramp voltage signal to be lower than the reference voltage; the class AB operational amplifier circuit amplifies the ramp voltage signal to obtain a second digital signal. Therefore, the circuit is suitable for wide-range load capacitance, and has a high power supply rejection ratio.

A power converter includes a timing control circuit, an interface, one or more switching circuits and a monitoring circuit. The one or more switching circuits generate one or more pulses in response to one or more timing signals generated by the timing control circuit. The monitoring circuit measures a delay between at least one of the one or more timing signals and at least one of the one or more pulses, and generates an output signal based on the delay. The timing control circuit adjusts the delay obtained by monitoring the output signal.

An active eye open monitor calibration apparatus and method for active eye open monitor calibration are provided. A reference clock signal and an eye open monitor clock signal are received and a calibration selecting signal is used to control whether the reference clock signal samples the eye open monitor clock signal. An indicator signal is output and received by a phase indicating determination circuit for performing a calibration flow and accordingly calculating a phase offset signal. The eye open monitor clock is corrected based on the phase offset signal, such that a calibrated eye open monitor clock signal is synchronously in phase with the reference clock signal. By employing the proposed eye open monitor calibration apparatus and method thereof, the invention is effective in achieving phase synchronization for an eye open monitor clock signal in related to its reference clock signal, solving the phase mismatch in the related arts.