84results about "Pulse shaping" patented technology

An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.

To provide a comparator which has improved response characteristics without increasing a circuit current.SOLUTION: A transistor M3 is connected to a differential transistor M1 in the manner of a folded-cascode connection. A transistor M4 is connected to a differential transistor M2 in the manner of a folded-cascode connection. When the transistor M4 is in its on-state, a transistor M7 controls reduction in a drain potential of the transistor M4.SELECTED DRAWING: Figure 1

A kind of control loop pulse width adjustable timer locking circuit and method, the circuit includes working power supply, first, second 555 timer chip U1, U2, three input or gate chip U3 and button switch S1;The power supply pin of working power supply VCC is connected to two 555 timers and three input or gate chip, the 2 number trigger pin of U1, U2 is connected;The 3 number output pin of U1, U2 and the pin of button switch S1 are respectively connected to the input end of U3, the output end of U3 is connected to the 2 number trigger pin of U1, U2, and is connected to VCC with a pull-up resistor R1, the other end of S1 is grounded;And the pulse width of U1 is less than U2.The control loop pulse width adjustable timer locking circuit and method of the present application can accurately modulate the test jump pulse width of control loop, and can only trigger once within a certain time, to avoid multiple triggers leading to undesirable consequences, effectively guarantee the stability of load control system.

Embodiments herein relate to optimizing the operation of multiple integrated circuits (ICs) operating in parallel. In one aspect, the ICs are arranged in a voltage-stacked configuration, and an operating frequency of each IC is controlled using a tunable replica circuit to stabilize its voltage drop. The tunable replica circuit mimics a critical path on the IC. In another aspect, an IC is divided into top and bottom portions which are in respective voltage domains on a substrate. The substrate include a deep n-well region for the higher voltage domain. In another aspect, a physically unclonable function (PUF) is used to generate identifiers for each IC among a multiple ICs on a board. Entropy sources of the PUF generate bits of the identifiers. Unstable entropy sources are identified and their bits are masked out.

This invention discloses a high-precision PWM pulse generation circuit and chip. The PWM pulse generation circuit includes a PWM pulse group unit, an output logic unit, and a precision control unit. A set of delayed clock signal input ports are connected to a set of input terminals of the PWM pulse group unit; a first control signal input port is connected to the control terminal of the PWM pulse group unit; and a set of output terminals of the PWM pulse group unit are connected to a first set of input terminals of the output logic unit. A second control signal input port is connected to the input terminal of the precision control unit; and a set of output terminals of the precision control unit are connected to a second set of input terminals of the output logic unit. The output terminal of the output logic unit is connected to the output terminal of the PWM pulse generation circuit. This PWM pulse generation circuit realizes the generation and adjustable output of a set of high-precision PWM pulse signals.

The application provides a universal low-power signal generator device, belonging to the technical field of signal generation and industrial control, which comprises a mode control module, an industrial control module and a power amplification module; the mode control module is used for switching control modes and outputting control signals; the industrial control module receives the control signals and converts them into basic analog signals; the power amplification module adjusts the basic analog signals into bipolar signals through a level shifting circuit, amplifies the bipolar signals into output analog signals through a power amplification circuit, improves the load driving capability, and detects feedback to the industrial control module through an output voltage detection circuit and an output current detection circuit. The application integrates multiple control modes and closed-loop detection functions, has strong universality, stable and reliable output, high safety and control precision, and is suitable for low-power signal driving scenes.

A debouncing logic circuit for processing an asynchronous input signal (din) and provide a debounced signal (dout), including a clock edge (ck), a first stage of flip-flops (q0; q1) driven by the clock edge, a multiplexer (MUX1) and coupled to the first stage of flip-flops, a second stage of flip-flops (q2; q3), a counter logic module (cnt) driven by the clock edge, a comparator module, a second multiplexer (MUX2) operable to select between the processed output signal and the debounced signal based on the control signal from the comparator, the internal state being the selected signal and an output stage (q4) driven by the clock edge and configured to provide the debounced signal (dout).

An attenuator includes passgates for providing attenuation of received signals at desired frequencies. The passgates are controlled by source followers implemented with transistors that receive the differential signals at their control terminals. Current provided to the source follower transistors can be set to provide an attenuation level at a desired frequency to offset the effects of the communications channel and parasitics of the receiver. In some embodiments, the current provided to the source follower transistors maybe programmable.

Provided are a pulse signal generation circuit and generation method, and a memory. The pulse signal generation circuit comprises a clock frequency-division unit, a time delay circuit and a selection unit, wherein the clock frequency-division unit is configured to perform frequency division on a clock signal, so as to generate a clock frequency-division signal; the time delay circuit is configured to generate a time delay signal on the basis of the clock frequency-division signal; and the selection unit is configured to receive the clock frequency-division signal and the time delay signal at the same time, and perform selection according to a preset condition so as to generate a pulse signal. The effective level width of a pulse signal generated in the disclosure can be controlled on the basis of both multiplies of an external clock period and a delay time, and the period of the pulse signal is established using the period of a clock signal as the basis. Insofar as both the period and the width of a pulse signal can meet requirements, the effective level width of the pulse signal of the present disclosure is more controllable, such that a memory has good access performance.

The present application provides an integrated circuit capable of reducing noise effects and operating with appropriate driving capability. It includes: a signal output circuit outputting a timing signal; a first holding circuit inputting a first voltage corresponding to the temperature of a first switching element and the timing signal, holding the first voltage for a first period after the timing signal is input, and outputting the first voltage after the first period; a second holding circuit inputting a second voltage corresponding to the temperature of a second switching element and the timing signal, holding the second voltage for a second period after the timing signal is input, and outputting the second voltage after the second period; a first control circuit controlling the switching of the first switching element based on the first voltage and a first driving signal with a first driving capability corresponding to the temperature of the first switching element; and a second control circuit controlling the switching of the second switching element based on the second voltage and a second driving signal with a second driving capability corresponding to the temperature of the second switching element.

The embodiment of the present application provides a kind of probability bit circuit and the control method of probability bit circuit.It includes at least two probability bits and at least one coupling module, the coupling module is connected between two probability bits;The coupling module includes adjustable response time unit, the adjustable response time unit is used to the output signal of the first probability bit in the two probability bits is time shaping and then input the second probability bit in the two probability bits, or, the output signal of the second probability bit is time shaping and then input the first probability bit.In the premise that additional storage array is not needed, the continuous dynamic adjustable of weight is realized.

A method including, during time period A, in a computer storage element having first and second power inputs separated by an array of transistors configured for storing a computer bit of data, moving an input of the array of transistors a logic value "1" or "0" a master latch, during time period B, recovering at least a portion of energy comprising the input with a first clock, during a time period C, moving the input in the master latch to an isolation stage, during time period D, recovering at least a portion of energy comprising the input from the isolation stage with a second clock, during time period E, recovering at least a portion of energy comprising the input from a follower latch with a third clock, and during time period F, moving at least a portion of the input from the isolation stage to the follower latch.

The present application discloses a source follower circuit, arranged for generating output signal according to input signal. The circuit includes: a first transistor having a drain coupled to a first reference voltage; a second transistor having a drain coupled to a source of the first transistor, and the first transistor and the second transistor both have polarization of a first type; a first capacitor, coupled between a gate of the first transistor and the input signal; and a first resistor, coupled between the gate of the first transistor and a first bias voltage; wherein a gate of the second transistor is coupled to the input signal, and a source of the second transistor outputs the output signal.

The present invention provides an electronic circuit capable of generating a pulse train containing multiple pulses in response to an input pulse signal. [Solution] The electronic circuit of this embodiment includes a reference circuit that generates a reference pulse signal synchronized with a clock signal based on an input pulse signal, a delay circuit that generates a delayed pulse signal by delaying the reference pulse signal, and an output circuit that outputs a pulse train including a plurality of pulses synchronized with a clock signal based on the reference pulse signal, the delayed pulse signal, and the clock signal.

This application relates to the field of integrated optoelectronic technology, and more specifically, to a pulse drive optimization circuit, including a rising edge detection circuit, a subtraction circuit, a monostable trigger circuit, and a signal superposition circuit. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under the reference voltage through the subtraction circuit, triggers the monostable trigger circuit to generate a high-amplitude short pulse, and finally the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuning optoelectronic integrated chip. This can significantly improve the thermo-optical tuning response speed of the chip without significantly increasing the average power consumption.

This invention discloses a high-voltage nanosecond pulse shaping device and method based on magnetic devices. The device includes: a first magnetic transmission line and a second magnetic transmission line, with their input ends connected in parallel and connected to an initial pulse source; the output end of the first magnetic transmission line is connected to a load terminal; the output end of the second magnetic transmission line is short-circuited to ground; the first magnetic transmission line includes a first magnetic ring arranged along the axial direction and an outer magnetic field coil; the second magnetic transmission line includes a second magnetic ring arranged along the axial direction. Based on the current-dependent nonlinear permeability effect of the magnetic ring, this device simultaneously achieves pulse rise time compression, fall time truncation, pulse width shortening, and suppression of pre-pulse and tail oscillations through the rising sharpening effect of the first magnetic transmission line and the falling truncation effect of the second magnetic transmission line. This overcomes the limitation of single nonlinear transmission line or magnetic switching technology, which can only optimize single pulse parameters, and can obtain high-quality pulse waveforms at the load terminal.

An operating frequency regulation method for a radio frequency (RF) circuit, an operating frequency control circuit, and an RF power supply device are provided. The operating frequency regulation method for the RF circuit includes the following. The RF circuit is controlled to output to a load at different operating frequencies. A circuit parameter of the RF circuit during output of the RF circuit at each of the different operating frequencies is detected. A resonant frequency of the RF circuit is calculated based on the detected circuit parameter of the RF circuit during the output of the RF circuit at each of the different operating frequencies. An operating frequency of the RF circuit is regulated to the resonant frequency.

The application discloses a filtering method for pulse width measurement, which firstly determines whether the pulse signal frequency in a first specified time period is stable, if stable, corrects the pulse width value according to the real-time cycle width, real-time high level width and real-time low level width obtained by real-time measurement, and determines whether the signal state of the current measurement pulse is full high, full low or normal according to the corrected pulse width value, then determines the number of the three signal states in a second specified time period, and determines the real-time signal state as the state with the largest number; if unstable, determines the real-time signal state according to the level for capturing the input pin in a third specified time period; finally, determines the output pulse width value according to the real-time signal state.

An apparatus including a comparator and a plurality of replica current sources. The comparator outputs a control voltage onto an output line upon comparing a midpoint voltage with a feedback voltage. The control voltage indicates whether the feedback voltage is higher or lower than the midpoint voltage. Each of the replica current sources draws a supply voltage from a supply line. A replica current source enters into an inactive state in response to an enable signal being in a deactivating state. Upon entering the inactive state, the replica current source ceases drawing the control voltage from the output line.

The application provides a control circuit and a control device. The control circuit comprises: a current sampling module, which is connected to both ends of a shunt to collect a first voltage signal on the shunt; an amplification module, which is used for amplifying the first voltage signal to obtain a second voltage signal and transmitting the second voltage signal to a signal processing module; the signal processing module is used for generating a corresponding first target control signal or a second target control signal according to the second voltage signal and a first reference voltage signal or a second reference voltage signal, and outputting the first target control signal or the second target control signal to a driving module; the driving module is used for generating a driving signal according to the first target control signal or the second target control signal, and outputting the driving signal to an ignition device, wherein the driving signal is used for driving the ignition device to ignite an explosion device in an intelligent fuse. In this way, the control mode for the ignition device is increased, so that the intelligent fuse can adapt to complex environments.

A signal transmission device includes a transmission circuit, a reception circuit, and an isolating element that transmits a pulse signal between the transmission circuit and the reception circuit while isolating between them. The transmission circuit includes an input terminal that receives an analogue signal, a comparison circuit that compares the analogue signal with each of a plurality of threshold values to generate a plurality of comparison signals, and a pulse signal generation circuit that generates the pulse signal according to the plurality of comparison signals.

A continuous time comparator, comprising a first Field Effect Transistor, FET, (Mn1) arranged for receiving a first input signal, and a second FET (Mn2) arranged for receiving a second input signal, two branches, a first of said two branches comprises a first transistor (Mp1) and a second of said two branches comprises a second transistor (Mp2), wherein said first of said two branches is connected to said first FET (Mn1) and wherein said second of said two branches is connected to said second FET (Mn2), a first dynamic clamp circuitry connected in parallel over said first branch, wherein said first dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a first output transistor (Mp4), and a second dynamic clamp circuitry connected in parallel over said second branch, wherein said second dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a second output transistor (Mp3), said first and second output transistors (Mp3, Mp4) for providing an output of said comparator and for providing an inverting output of said comparator.

This invention provides a rising-edge trigger, a trigger module, and a low-noise amplifier. The rising-edge trigger includes a first inverting circuit, a first field-effect transistor, a first inverter, an RC charging circuit, a second inverting circuit, a Schmitt trigger, and a third inverting circuit. The first inverting circuit shapes the input excitation signal. The RC charging circuit charges and gradually increases the charging voltage. The second inverting circuit generates a delay signal with a preset time width. The Schmitt trigger shapes the delay signal generated by the second inverting circuit with the preset time width. The third inverting circuit shapes the delay signal after it has been shaped by the Schmitt trigger. This invention reduces the number of rising-edge triggers in the trigger module, thereby reducing the overall area of ​​the trigger module, while also improving the power-on and switching response speed of the low-noise amplifier.

The application provides a conversion device for converting lightning electric energy into kinetic energy, and relates to the technical field of electric energy conversion devices.The device comprises an artificial lightning attraction system, which is used for inducing lightning in a thunderstorm environment and leading out the generated lightning current; a pulse energy storage and conversion system, which is connected with the artificial lightning attraction system, is used for receiving the lightning current led out by the artificial lightning attraction system and storing energy, and outputs the energy after pulse shaping and power amplification as pulse electric energy; and an electromagnetic track launching system, which is connected with the pulse energy storage and conversion system, is used for receiving the pulse electric energy for pulse discharge to generate an electromagnetic field to provide electromagnetic propulsion force, so as to launch a load.The application solves the problems that the existing technology causes the loss of artificial lightning attraction energy directly led into the ground, and the electromagnetic track launching device highly depends on a conventional power grid, thereby causing the great power supply pressure of the power grid.

A phase shifter for a millimeter wave (mmW) communication system including an in phase variable gain amplifier (I VGA) and a quadrature VGA (Q VGA) configured to receive radio frequency (RF) signals, the I VGA and the Q VGA configured to provide a selectable output to primary sides of first and second electromagnetic (EM) elements, respectively, the first EM element configured to provide a single-ended I output and the second EM element configured to provide a single-ended Q output, and a hybrid quadrature generator (HQG) configured to receive the single-ended I output of the first EM element and the single-ended Q output of the second EM element, the HQG configured to provide a combined signal at a desired phase.

An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

The application relates to a signal smoothing processing method, a circuit and an integrated circuit. The method comprises the following steps: in response to a gear change of an input electrical signal, controlling an electrical signal state machine to switch from a standby state to a target gear state; during the target gear state, a look-up table coding counter with a configurable counting step is used to accumulate counting according to a preset counting step, and a corresponding coding value is output; based on the coding value, a prestored smoothing mapping relationship is queried, and a corresponding smoothing electrical signal value is output; the electrical signal state machine superimposes the smoothing electrical signal value on a reference electrical signal maintained by the electrical signal state machine before the change according to an adjustment rule corresponding to the gear change direction, to generate an output electrical signal with a smooth transition, and resets itself to the standby state. In this way, efficient, flexible and configurable smoothing processing of a multi-gear signal can be realized, so that electromagnetic radiation of a signal edge can be effectively inhibited.