Retiming circuit applied to ultra-high-speed and high-precision DAC

Abstract

The invention relates to a retiming circuit applied to an ultra-high-speed and high-precision DAC (Digital-to-Analog Converter), which comprises an alignment module, a cross point adjusting module, a coding module, a phase detection module and a digital module, the coding module is connected with the alignment module, the phase detection module is connected with the cross point adjusting module and the coding module, and the digital module is connected with the phase detection module and the alignment module. According to the circuit structure provided by the invention, the sampling clock can be accurately aligned to the center of a data eye pattern, so that the delay difference between a clock tree and a data path caused by process deviation and the like is effectively reduced, the high-frequency spurious suppression performance is improved by eliminating nonlinear distortion caused by time sequence errors, the SFDR is greatly improved, and compared with a traditional scheme, the SNR is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a retiming circuit applied to an ultra-high-speed, high-precision DAC. Background Technology

[0002] In cutting-edge fields such as quantum computing, wireless communication, radar detection, and high-speed data centers, the performance of ultra-high-speed, high-precision digital-to-analog converters (DACs) is facing severe challenges from process variations, power supply noise, and non-ideal effects. At advanced process nodes (such as below 28nm), random fluctuations in transistor threshold voltage, channel length, and oxide thickness cause delay mismatches between the clock tree and data path, leading to setup / hold time violations and increasing output transient noise and harmonic distortion. Simultaneously, transient voltage drops in the power network and high-frequency resonant noise caused by high-speed switching activities introduce sampling clock jitter (Tj) and excite voltage-sensitive jitter in the data path, directly degrading the signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR). Furthermore, interconnect parasitic effects (such as RC delay and crosstalk) and substrate coupling noise further amplify timing uncertainties, forming multi-dimensional performance bottlenecks.

[0003] In ultra-high-speed applications, the above problems are amplified exponentially. When the data rate exceeds GSPS (gigasamples per second) or even tens of GSPS, the effective data window narrows to the picosecond level. Traditional global clock trees cannot compensate for process / voltage / temperature (PVT) drift in local paths, causing the sampling phase to deviate from the center of the data eye diagram, reducing the time difference with the data edge, and thus reducing the timing margin. Switching noise from the front-end digital logic (such as encoders) is coupled to the DAC analog core through long paths, generating high-frequency spurious noise in the output spectrum that is difficult to suppress. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a retiming circuit for ultra-high-speed, high-precision DACs. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a retiming circuit for an ultra-high-speed, high-precision DAC, comprising: The alignment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and select and adjust the phase of the first four-phase clock signal according to the control signals CLKI_S and CLKQ_S to obtain the second four-phase clock signal. The crosspoint adjustment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and to adjust the crosspoint of the first four-phase clock signal to obtain the third four-phase clock signal. The encoding module, connected to the alignment module, uses the second four-phase clock signal to encode the input data of the encoding module to obtain the encoded four-channel data; The phase detection module, connected to the crosspoint adjustment module and the encoding module, is used to detect the phase between the third four-phase clock signal and the encoded four-channel data, and output the detection result of the phase difference between the data and the clock. The digital module, connected to the phase detection module and the alignment module, is used to update the current optimal control signal based on the detection result of the phase difference between the data and the clock, and generate control signals CLKI_S, CLKQ_S and phase interpolation weight adjustment signals for phase selection. The control signals CLKI_S, CLKQ_S and phase interpolation weight adjustment signals are output to the alignment module, and the final optimal control signal is locked after the adjustment is completed.

[0005] In one embodiment of the present invention, the alignment module includes two identical first phase interpolation circuits and a second phase interpolation circuit. In one embodiment of the present invention, both the first phase interpolation circuit and the second phase interpolation circuit include: A 4-to-2 phase selector is used to select, based on the control signals CLKI_S and CLKQ_S output by the digital module, two orthogonal phases of a first clock signal and a second clock signal from the first four-phase clock signal. The first integrating phase interpolator is connected to the four-to-two phase selector and is used to perform interpolation processing using the first clock signal to obtain the first interpolated clock signal. The second integral phase interpolator is connected to the four-to-two phase selector and is used to perform interpolation processing using the second clock signal to obtain the second interpolated clock signal. The CML2CMOS module and capacitor C1 are connected to the first integrating phase interpolator, the second integrating phase interpolator, and the CML2CMOS module. The first interpolation clock signal and the second interpolation clock signal charge and discharge the capacitor C1, forming a non-full-swing clock signal on the capacitor C1. The CML2CMOS module then shapes the non-full-swing clock signal into a full-swing single-ended clock signal. A single-ended to differential converter module, connected to the CML2CMOS module, is used to convert the full-swing single-ended clock signal into a differential two-phase clock signal. In one embodiment of the present invention, the first integrating phase interpolator includes a first phase interpolation unit and a second phase interpolation unit. The first phase interpolation unit includes four parallel first phase interpolation sub-units, and the second phase interpolation unit includes eight parallel first phase interpolation sub-units. The first phase interpolation sub-unit includes transistors M1, M2, M3, and M4, resistors R2 and R3, wherein: The source of transistor M1 is connected to the power supply terminal, the drain of transistor M1 is connected to the source of transistor M2, the drain of transistor M2, resistor R2, resistor R3 and the drain of transistor M3 are connected in sequence, the source of transistor M3 is connected to the drain of transistor M4, and the source of transistor M4 is connected to the ground terminal. The gates of all transistors M1 and M4 are connected to the PHASE_I signal output of the 4-to-2 phase selector. The nodes connected to all resistors R2 and R3 are connected to capacitor C1. The gates of all transistors M2 in the first phase interpolation unit are connected to the SI signal terminal, and the gates of all transistors M3 are connected to the SIB signal terminal. The gates of all transistors M2 in the second phase interpolation unit are connected to the SIQ_P signal terminal, and the gates of all transistors M3 are connected to the SIQ_PB signal terminal. Here, signals SI and SIB are complementary, and signals SIQ_P and SIQ_PB are complementary. In one embodiment of the present invention, transistors M1 and M2 are PMOS, and transistors M3 and M4 are NMOS. In one embodiment of the present invention, the second integrating phase interpolator includes a third phase interpolation unit and a fourth phase interpolation unit. The third phase interpolation unit includes four parallel second phase interpolation sub-units, and the fourth phase interpolation unit includes eight parallel second phase interpolation sub-units. Each second phase interpolation sub-unit includes transistors M5, M6, M7, and M8, resistor R4, and resistor R5, wherein: The source of transistor M5 is connected to the power supply terminal, the drain of transistor M5 is connected to the source of transistor M6, the drain of transistor M6, resistor R3, resistor R4 and the drain of transistor M7 are connected in sequence, the source of transistor M7 is connected to the drain of transistor M8, and the source of transistor M8 is connected to the ground terminal. The gates of all transistors M5 and M8 are connected to the PHASE_Q signal output of the 4-to-2 phase selector. The nodes connected to all resistors R4 and R5 are connected to capacitor C1. The gates of all transistors M6 in the third phase interpolation unit are connected to the SQ signal terminal, and the gates of all transistors M7 are connected to the SQB signal terminal. The gates of all transistors M6 in the fourth phase interpolation unit are connected to the SIQ_N signal terminal, and the gates of all transistors M3 are connected to the SIQ_NB signal terminal. Here, signals SQ and SQB are complementary, and signals SIQ_N and SIQ_NB are complementary. In one embodiment of the present invention, transistors M5 and M6 are PMOS, and transistors M7 and M8 are NMOS. In one embodiment of the present invention, the phase detection module includes mixer circuits H1, H2, H3, and H4, a first RC filter circuit, a second RC filter circuit, and a clock comparator. The first RC filter circuit includes a resistor R6 and a capacitor C3, and the second RC filter circuit includes a resistor R7 and a capacitor C4. The output terminals of mixer circuits H1 and H2 are connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of capacitor C3 and the positive input terminal of the clock comparator. The other end of capacitor C3 is connected to ground. The output terminals of mixer circuits H3 and H4 are connected to one end of resistor R7, and the other end of resistor R7 is connected to one end of capacitor C4 and the negative input terminal of the clock comparator. The other end of capacitor C4 is connected to ground. The output terminal of the clock comparator is connected to a digital module, wherein: The mixing circuit H1 is used to receive the IN clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data. After mixing, it outputs a first mixing signal carrying duty cycle information. The mixer circuit H2 is used to receive the IP clock signal in the third four-phase clock signal and the IN data signal of the encoded four-channel data. After mixing, it outputs a first mixer signal carrying duty cycle information. The mixer circuit H3 is used to receive the IP clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data. After mixing, a second mixer signal carrying duty cycle information is obtained. The mixer circuit H4 receives the IN clock signal from the third four-phase clock signal and the IN data signal from the encoded four-channel data. After mixing, it obtains a second mixer signal carrying duty cycle information. The first RC filter circuit is used to filter the first mixing signal to obtain a first average voltage value; The second RC filter circuit is used to filter the second mixing signal to obtain a second average voltage value; The clock comparator is used to receive the first average voltage value and the second average voltage value, and compare the first average voltage value and the second average voltage value to obtain the detection result of the phase difference between the data and the clock. When the detection result is that the phase difference is greater than 90°, the output is 0, and when the phase difference is less than 90°, the output is 1. In one embodiment of the present invention, the retiming circuit further includes switches SW1 and SW2, wherein the first end of switch SW1 is connected to the encoding module and the second end is connected to the phase detection module, and the first end of switch SW2 is connected to the crosspoint adjustment module and the second end is connected to the phase detection module.

[0006] In one embodiment of the present invention, the execution steps of the digital module include: S1. The first counter is used to count the number of clock cycles. When the count of the first counter reaches n clock cycles, the second counter counts the first number of 1s output by the phase detection module and the second counter counts the second number of 0s output by the phase detection module, where n is an integer greater than or equal to 0. S2. Determine the size of the first quantity and the second quantity. If the first quantity is greater than the second quantity, set the flag to 1. If the first quantity is less than the second quantity, set the flag to 0. S3. Determine whether the current flag bit is the same as the flag bit of the previous round. If they are the same, keep the current best control signal unchanged. If they are different, use the current control signal as the current best control signal and update the flag bit to the current flag bit. S4. According to the monotonic change direction of the interpolation phase, linearly generate the phase selection control signal CLKI_S and control signal CLKQ_S covering the entire interpolation range of the alignment module, as well as the phase interpolation weight adjustment signal. The phase interpolation weight adjustment signal includes signal SI, signal SIB, signal SQ, signal SQB, signal SIQ_P, signal SIQ_PB, signal SIQ_N, and signal SIQ_NB. S5. Based on the phase of the alignment module, traverse the preset number of times according to S1-S4, and use the best control signal that appears most frequently as the final best control signal. Then, output the final best control signal to the alignment module and lock the final best control signal unchanged. Compared with the prior art, the beneficial effects of the present invention are as follows: The retiming circuit provided by this invention includes an alignment module, a crosspoint adjustment module, an encoding module, a phase detection module, and a digital module. The alignment module selects and adjusts the phase of the first four-phase clock signal according to the control signals CLKI_S and CLKQ_S to obtain the second four-phase clock signal. The crosspoint adjustment module adjusts the crosspoint of the first four-phase clock signal to obtain the third four-phase clock signal. Then, the encoding module uses the second four-phase clock signal to encode the input data of the encoding module to obtain four encoded data channels. The phase detection module then detects the phase between the third four-phase clock signal and the four encoded data channels, and outputs the detection result of the phase difference between the data and the clock. The digital module updates the current optimal control signal according to the detection result of the phase difference between the data and the clock, and generates control signals CLKI_S, CLKQ_S, and phase interpolation weight adjustment signals for phase selection. The control signals CLKI_S, CLKQ_S, and phase interpolation weight adjustment signals are output to the alignment module, and the final optimal control signal is locked after the adjustment is completed. The circuit structure provided by this invention can accurately align with the center of the data eye diagram, thereby effectively reducing the path delay difference caused by process deviations. By eliminating nonlinear distortion caused by timing errors, it improves the high-frequency spurious suppression performance, significantly improves SFDR, and effectively enhances SNR compared with traditional solutions.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a retiming circuit applied to an ultra-high-speed, high-precision DAC, provided by an embodiment of the present invention. Figure 2 This is a schematic diagram of the alignment module provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the integral phase interpolator provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the phase interpolation principle provided in an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the working principle of the integral phase interpolator in the alignment module provided in this embodiment of the invention. Figure 6 This is a schematic diagram of the switching between the octagonal phase rotator and the control code provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the phase detection module provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the input and output of the mixer circuit and the output of the clock comparator provided in an embodiment of the present invention; Figure 9This is a schematic diagram illustrating the adjustment effect of the retiming circuit provided in an embodiment of the present invention. Detailed Implementation

[0009] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0010] Example 1 Please see Figure 1 , Figure 1 This is a module block diagram of a retiming circuit applied to an ultra-high-speed, high-precision DAC provided by an embodiment of the present invention. The present invention provides a retiming circuit applied to an ultra-high-speed, high-precision DAC, the retiming circuit comprising: The alignment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and select and adjust the phase of the first four-phase clock signal according to the control signals CLKI_S and CLKQ_S to obtain the second four-phase clock signal. The crosspoint adjustment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and to adjust the crosspoint of the first four-phase clock signal to obtain the third four-phase clock signal. The encoding module, connected to the alignment module, is used to encode the input data of the encoding module using the second four-phase clock signal to obtain the encoded four-channel data. The phase detection module, which connects the crosspoint adjustment module and the encoding module, is used to detect the phase between the third and fourth phase clock signals and the encoded four-channel data, and outputs the detection result of the phase difference between the data and the clock. The digital module connects the phase detection module and the alignment module. It updates the current optimal control signal based on the detection result of the phase difference between the data and the clock, and generates control signals CLKI_S, CLKQ_S, and phase interpolation weight adjustment signals for phase selection. It outputs the control signals CLKI_S, CLKQ_S, and phase interpolation weight adjustment signals to the alignment module, and locks the final optimal control signal after the adjustment is completed.

[0011] In this embodiment, the four-phase clock signal refers to a set of four clock signals with non-overlapping phases. The phase of each clock signal is usually 90 degrees different, that is, clock signals with phases of 0°, 90°, 180°, and 270°. The first four-phase clock signals input to the alignment module and the cross-point adjustment module are clock signals after duty cycle and phase calibration. The purpose of phase calibration is to eliminate the phase error between the four-phase clock signals, and the purpose of duty cycle calibration is to ensure that the duty cycle of each clock signal accurately meets the target value, such as a duty cycle of 50%.

[0012] In one specific embodiment, please refer to Figure 2The alignment module includes two identical first phase interpolation circuits and a second phase interpolation circuit. Both the first phase interpolation circuit and the second phase interpolation circuit include: A 4:2 MUX phase selector is used to select two clock signals with orthogonal phases, namely a first clock signal and a second clock signal, from the first four-phase clock signal based on the control signals CLKI_S and CLKQ_S output by the digital module. The first clock signal is denoted as PHASE_I clock signal and the second clock signal is denoted as PHASE_Q clock signal. The first integrating phase interpolator is connected to a 4-to-2 phase selector and is used to perform interpolation processing using the first clock signal to obtain the first interpolated clock signal. The second integrating phase interpolator is connected to a 4-to-2 phase selector and is used to perform interpolation processing using the second clock signal to obtain the second interpolation clock signal. The CML2CMOS (Current Mode Logic (CML) Level to CMOS Level) module and capacitor C1, the first integrating phase interpolator, the second integrating phase interpolator and the CML2CMOS module are all connected to capacitor C1. The first interpolation clock signal and the second interpolation clock signal charge and discharge capacitor C1, and form a non-full swing clock signal on capacitor C1. The CML2CMOS module shapes the non-full swing clock signal into a full swing single-ended clock signal. The single-ended to differential module, connected to the CML2CMOS module, is used to convert a full-swing single-ended clock signal into a differential two-phase clock signal.

[0013] Specifically, the digital module generates control signals CLKI_S and CLKQ_S to control the interpolation range. This is achieved through a 4-to-2 phase selector. Its basic circuit is a 4-to-2 MUX (Multiplexer) circuit. Based on the control signals CLKI_S and CLKQ_S, two orthogonal clock signals are selected to enter the first and second integrating phase interpolators, respectively. When different MUX control codes are used, two orthogonal clocks will be selected respectively, thereby completing the 0-360° phase coverage. The generated phase-interpolated clock (first interpolated clock signal and second interpolated clock signal) is sampled by the CML2CMOS module to sample the voltage on capacitor C1 at the output of the integrating interpolator. The first interpolated clock signal and the second interpolated clock signal are combined on capacitor C1 to form a non-full-swing clock signal. The CML2CMOS module restores and reshapes the non-full-swing clock signal into a full-swing clock signal and improves the duty cycle, thereby improving the clock quality and reducing the jitter of the clock generated by the integrating phase interpolator. The single-ended to differential module converts this full-swing clock signal into a differential two-phase clock signal, namely clock signal CLKP and clock signal CLKN.

[0014] The positions of the four-phase clock signals input to the first and second phase interpolation circuits are swapped. For example, the first phase interpolation circuit selects clock signals at 0° and 90°, while the same control signals in the second phase interpolation circuit select 270° and 0°. The PHASE_I2 selected by the 4-to-2 phase selector in the second phase interpolation circuit differs from the PHASE_I1 output by the first phase interpolation circuit by 90°, and the PHASE_Q2 output by the second phase interpolation circuit differs from the PHASE_Q1 output by the first phase interpolation circuit by 90°. Finally, the first and second phase interpolation circuits output a differential four-phase clock signal, which is then output as the second four-phase clock signal to the encoding module. Where CLKI_S=0, CLKQ_S=0, PHASE_I outputs a 0° clock signal, and PHASE_Q outputs a 90° clock signal; CLKI_S=1, CLKQ_S=0, PHASE_I outputs a 90° clock signal, and PHASE_Q outputs a 180° clock signal; CLKI_S=1, CLKQ_S=1, PHASE_I outputs a 180° clock signal, and PHASE_Q outputs a 270° clock signal; CLKI_S=0, CLKQ_S=1, PHASE_I outputs a 270° clock signal, and PHASE_Q outputs a 360° (0°) clock signal.

[0015] Further, please see Figure 3 The first integrating phase interpolator includes a first phase interpolation unit and a second phase interpolation unit. The first phase interpolation unit includes four parallel first phase interpolation sub-units, and the second phase interpolation unit includes eight parallel first phase interpolation sub-units. The first phase interpolation sub-unit includes transistors M1, M2, M3, and M4, resistors R2 and R3, wherein: The source of transistor M1 is connected to the power supply terminal, the drain of transistor M1 is connected to the source of transistor M2, the drain of transistor M2, resistor R2, resistor R3 and the drain of transistor M3 are connected in sequence, the source of transistor M3 is connected to the drain of transistor M4, and the source of transistor M4 is connected to the ground terminal. The gates of all transistors M1 and M4 are connected to the PHASE_I signal output of the 4-to-2 phase selector. The nodes connected by all resistors R2 and R3 are connected to capacitor C1. The gates of all transistors M2 in the first phase interpolation unit are connected to the SI signal terminal, and the gates of all transistors M3 are connected to the SIB signal terminal. The gates of all transistors M2 in the second phase interpolation unit are connected to the SIQ_P signal terminal, and the gates of all transistors M3 are connected to the SIQ_PB signal terminal. Here, signals SI and SIB are complementary, and signals SIQ_P and SIQ_PB are complementary.

[0016] Optionally, transistors M1 and M2 are PMOS, and transistors M3 and M4 are NMOS.

[0017] Furthermore, please see again Figure 3 The second integrating phase interpolator includes a third phase interpolation unit and a fourth phase interpolation unit. The third phase interpolation unit includes four parallel second phase interpolation sub-units, and the fourth phase interpolation unit includes eight parallel second phase interpolation sub-units. Each second phase interpolation sub-unit includes transistors M5, M6, M7, and M8, resistors R4 and R5, wherein: The source of transistor M5 is connected to the power supply terminal, the drain of transistor M5 is connected to the source of transistor M6, the drain of transistor M6, resistor R3, resistor R4 and the drain of transistor M7 are connected in sequence, the source of transistor M7 is connected to the drain of transistor M8, and the source of transistor M8 is connected to the ground terminal. The gates of all transistors M5 and M8 are connected to the PHASE_Q signal output of the 4-to-2 phase selector. The nodes connected by all resistors R4 and R5 are connected to capacitor C1. The gates of all transistors M6 in the third phase interpolation unit are connected to the SQ signal terminal, and the gates of all transistors M7 are connected to the SQB signal terminal. The gates of all transistors M6 in the fourth phase interpolation unit are connected to the SIQ_N signal terminal, and the gates of all transistors M3 are connected to the SIQ_NB signal terminal. Here, signals SQ and SQB are complementary, and signals SIQ_N and SIQ_NB are complementary.

[0018] Optionally, transistors M5 and M6 are PMOS, and transistors M7 and M8 are NMOS.

[0019] Furthermore, the CML2CMOS module includes a capacitor C2, a resistor R1, an inverter, and a buffer. One end of capacitor C2 is connected to capacitor C1, and the other end is connected to one end of resistor R1 and the input terminal of the inverter. The other end of resistor R1 and the output terminal of the inverter are connected to the input terminal of the buffer. The output terminal of the buffer is connected to a single-ended to differential converter module.

[0020] In this embodiment, the basic principle of phase interpolation is to generate a new phase between two known phases based on interpolation weighting coefficients KA and KB. Its implementation principle is to add two orthogonal clocks according to different ratios KA and KB based on a control code, thereby obtaining any clock with a phase between these two orthogonal phases. Generally, a phase interpolator achieves phase interpolation by controlling the current value applied to the load. For example... Figure 4 As shown, CLKI and CLKQ under different control weights will generate CLK_PI with different phases, and the generated clock phase is only between these two orthogonal clock phases, with the period being consistent with the two clocks.

[0021] Please see Figure 5 The working principle of an integrating phase interpolator is that before the rising edge of the input clock arrives, all PMOS transistors are turned on, NMOS transistors are turned off, and the output is high. Figure 5 As shown in Figure (a). Next, the rising edge of the first clock signal PHASEI arrives first, the NMOS of the first inverter array turns on, and begins to discharge the capacitors at the output nodes, gradually decreasing the output level, as shown in Figure (a). Figure 5 As shown in Figure (b). Until the rising edge of the second clock signal, PHASEQ, arrives, the NMOS transistors of the second inverter array also turn on, discharging the capacitor at the output node together until the output level goes low, as shown in Figure (b). Figure 5 As shown in Figure (c), the final output voltage waveform can be approximated using a piecewise straight line. In practical applications, the output phase can be changed by altering the enable weights and combinations of the two inverter arrays. When the first inverter array has a large number of inverters or a high weight, more charge is discharged in the first discharge stage, resulting in an earlier phase of the final output waveform; conversely, when the first inverter array has a small number of inverters or a low weight, less charge is discharged in the first discharge stage, resulting in a later phase of the output waveform.

[0022] The SI and SIQ_P signals respectively control the 4+8 first phase interpolation sub-units in the first integrating phase interpolator that receives the PHASE_I clock signal, and control the weight of turning the first phase interpolation sub-units on or off according to the SI and SIQ_P signals; the SQ and SIQ_N signals respectively control the 4+8 second phase interpolation sub-units in the second integrating phase interpolator that receives the PHASE_Q clock signal, and control the weight of turning the second phase interpolation sub-units on or off according to the SQ and SIQ_N signals.

[0023] This embodiment uses an integrating phase interpolator, which adds a load resistor to an inverter-based voltage interpolator to reduce nonlinearity and achieves interpolation within a 90° interval. By connecting a resistor in series at the output, the output impedance of a single phase interpolation unit is made so that... Increasing the impedance at the output makes the current source more similar to an ideal current source, improves the linearity of the interpolator, and makes the current signal at the output as linear as possible.

[0024] In this embodiment, the method of interpolating the phase interpolation circuit by the digital circuit, and the phase interpolation circuit itself, can be considered as an octagonal phase rotator. The octagonal phase rotator is described below. In this octagonal phase rotator, 100 phases correspond to the 7-bit accumulator result S[6:0]. Its control signal is generated by a decoder, and the required four-phase quadrature clock signal is provided by the duty cycle and phase calibration circuit of the preceding stage after duty cycle and quadrature phase calibration. The schematic diagram of the octagonal phase rotator is shown below. Figure 6 As shown, the coordinate axes represent the phases of the four-phase quadrature clock signals: 0°, 90°, 180°, and 270°. The two quadrature clocks used for interpolation are controlled by the control signals CLKI_S and CLKQ_S, which control the quadrants of phase interpolation. The weighting coefficients KI and KQ of the I and Q quadrature clocks are controlled by SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0]. By changing the above control signals, clocks with different phases can be generated, and the new clock phase is between the phases of the two quadrature clocks.

[0025] The quadrant control code changes as S[6:0] increases as follows: When S[6:0] changes from 0 to 24, CLKI_S=0, CLKQ_S=0; When S[6:0] changes from 25 to 49, CLKI_S=1, CLKQ_S=0; When S[6:0] changes from 50 to 74, CLKI_S=1, CLKQ_S=1; When S[6:0] changes from 75 to 99, CLKI_S=0 and CLKQ_S=1.

[0026] The weight control codes SI[3:0], SQ[3:0], SIQ_P[7:0], and SIQ_N[7:0] change as the accumulator S[6:0] changes from 0 to 24, as follows: When S[6:0]=0, SI[3:0]=1111, SQ[3:0]=0000, SIQ_P[7:0]=11111111, SIQ_N[7:0]=00000000; When S[6:0] changes from 1 to 4, SI[3:0]=1111 remains unchanged, SQ[3:0] changes from 0000 to 1111 and only changes by one bit each time, SIQ_P[7:0]=11111111 remains unchanged, and SIQ_N[7:0]=00000000 remains unchanged. When S[6:0] changes from 5 to 20, SI[3:0]=1111 remains unchanged, SQ[3:0]=1111 remains unchanged, SIQ_P[7:0] changes from 11111111 to 0000000, changing only one bit at a time. Correspondingly, SIQ_N[7:0] changes from 0000000 to 11111111, changing only one bit at a time. Compared to the complementary control codes used for SIQ_P and SIQ_N in 64-phase interpolation, this invention uses alternating changes of SIQ_P and SIQ_N to increase the number of interpolable phases, achieving 100 phases without increasing interpolation units, thus improving interpolation accuracy. If S[6:0]=5, when SIQ_P[7:0] changes from 11111111 to 11111110, SIQ_N[7:0] remains unchanged at 00000000; if S[6:0]=6, when SIQ_P[7:0] remains unchanged at 11111110, SIQ_N[7:0] changes from 00000000 to 00000001. And so on.

[0027] When S[6:0] changes from 21 to 24, SI[3:0] changes from 1111 to 0000, changing only one bit at a time. SQ[3:0]=1111 remains unchanged, SIQ_P[7:0]=00000000 remains unchanged, and SIQ_N[7:0]=11111111 remains unchanged.

[0028] In one specific embodiment, the encoding module uses the second four-phase clock signal output by the alignment module to encode the input data, obtaining four encoded data channels. The encoding module can use a two-to-one multiplexer implemented with an inverter to sample and recombine the input data, inserting another set of data into the equally spaced data of the four sampling points of the I-channel output data. The final output of the encoding module is four non-full-swing data signals arranged at intervals, related to the input four-phase clock, i.e., the four encoded data channels. The input data of the encoding module is four high-speed serial data channels converted from parallel to serial.

[0029] By adjusting the phase of the four-phase clock before the encoding module, the phase of the output data of the encoding module can be controlled and adjusted, thereby aligning the sampling points of the four-phase clock output by the crosspoint adjustment module with the center of the data eye diagram. Compared with the data and clock phase retiming circuit that adjusts the phase of the four-phase clock to align with the center of the data eye diagram while keeping the data phase unchanged, this method can achieve better multi-chip synchronization.

[0030] In one specific embodiment, the retiming circuit further includes switches SW1 and SW2, wherein the first terminal of switch SW1 is connected to the encoding module and the second terminal is connected to the phase detection module, and the first terminal of switch SW2 is connected to the crosspoint adjustment module and the second terminal is connected to the phase detection module. The second terminals of switches SW1 and SW2 may also be connected to the dummy terminal of the four-switch module. Additionally, the retiming circuit may also include switch SW3, the first terminal of which is connected to the crosspoint adjustment module, and the second terminal of switch SW3 is connected to the dummy terminal of the four-switch module.

[0031] Specifically, the data generated by the encoding module is sent to the four-switch module and the four-switch module Dummy terminal through switches SW1 and SW3 respectively. When the retiming circuit is working, switch SW3 is turned on and switch SW1 is turned off. The crosspoint adjustment module generates a crosspoint-adjusted four-phase clock as the sampling clock of the four-switch module. The phase detection module detects the phase between the data passing through switch SW1 and the data with the four-switch module Dummy terminal as the load, and the sampling clock passing through switch SW2 and the data with the four-switch module Dummy terminal as the load, and outputs the detection result.

[0032] In other words, the phase detection module detects the phase between the data output by the encoding module after switch SW1 is closed and the clock signal output by the crosspoint adjustment module after switch SW2 is closed, and outputs the phase detection result. The four-phase clock signal after crosspoint adjustment and the encoded data are both split in two. One output is sent to the subsequent four-switch module, which contains multiple identical sampling switch sub-circuits. The four-switch module achieves non-overlapping sampling of the data output by the encoding module, converting the 0 / 1 code stream output by the encoding module into differential currents with alternating polarities and different weights. The differential voltage is output through the load resistor, and finally synthesized into an analog signal output. The other output is sent to the phase detection module, and the dummy terminal of the four-switch module is used as a load to ensure that the data and clock input to the phase detection module have the same phase relationship as the data and clock actually used in the main path four-switch module. The circuit of the dummy terminal of the four-switch module is the same as the circuit of the main path four-switch module, and only one sub-circuit is selected to ensure that it has the same parasitic and subsequent load environment.

[0033] In one specific embodiment, please refer to Figure 7The phase detection module includes mixer circuits H1, H2, H3, and H4, a first RC filter circuit, a second RC filter circuit, and a clock comparator. The first RC filter circuit includes a resistor R6 and a capacitor C3, and the second RC filter circuit includes a resistor R7 and a capacitor C4. The outputs of mixer circuits H1 and H2 are connected to one end of resistor R6, and the other end of resistor R6 is connected to one end of capacitor C3 and the positive input of the clock comparator. The other end of capacitor C3 is connected to ground. The outputs of mixer circuits H3 and H4 are connected to one end of resistor R7, and the other end of resistor R7 is connected to one end of capacitor C4 and the negative input of the clock comparator. The other end of capacitor C4 is connected to ground. The output of the clock comparator is connected to the digital module. The mixer circuit H1 is used to receive the IN clock signal and the IP data signal of the encoded four-channel data in the third four-phase clock signal. After mixing, it outputs the first mixer signal carrying the duty cycle information. The mixer circuit H2 is used to receive the IP clock signal and the IN data signal of the encoded four-channel data in the third four-phase clock signal. After mixing, it outputs the first mixer signal carrying the duty cycle information. The mixer circuit H3 is used to receive the IP clock signal and the IP data signal of the encoded four-channel data in the third four-phase clock signal. After mixing, a second mixer signal carrying duty cycle information is obtained. The mixer circuit H4 receives the IN clock signal from the third four-phase clock signal and the IN data signal of the encoded four data channels. After mixing, it obtains the second mixer signal carrying duty cycle information. The first RC filter circuit is used to filter the first mixing signal to obtain the first average voltage value; The second RC filter circuit is used to filter the second mixing signal to obtain the second average voltage value; The clock comparator is used to receive the first average voltage value and the second average voltage value, and compare the first average voltage value and the second average voltage value to obtain the detection result of the phase difference between the data and the clock. When the detection result is that the phase difference is greater than 90°, the output is 0, and when the phase difference is less than 90°, the output is 1.

[0034] Specifically, the input of the phase detection module is connected to the sampling clock via switch SW1, with the Dummy terminal of the four-switch module as the load, and the sampled data generated by the encoding module via switch SW2. The data generated by the encoding module is adjusted to a simple 0 / 1 output during retiming. The input of the phase detection module includes two sets of four mixer circuits. The first set detects the phase difference between the IN clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data, as well as the phase difference between the IP clock signal in the third four-phase clock signal and the IN data signal of the encoded four-channel data, outputting a first mixer signal MIX_CLK_P carrying duty cycle information. The second set detects the phase difference between the IP clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data, as well as the phase difference between the IN clock signal in the third four-phase clock signal and the IN data signal of the encoded four-channel data. One data C and the IN clock are input to one of the mixer circuits, outputting a second mixer signal MIX_CLK_N carrying duty cycle information. The input and output of the mixer circuits are as follows: Figure 8 As shown in Figure (a), the two sets of mixer circuits in the phase detection module convert the phase information between the data and the sampling clock into duty cycle information of MIX_CLK_N and MIX_CLK_P. For example, if the phase difference between the data and the sampling clock is greater than 90°, it is manifested as the duty cycle of MIX_CLK_N being greater than 50%, while the duty cycle of MIX_CLK_P is less than 50%. The average voltage value output by the RC filter circuit is thus greater than the average voltage filtered out at the MIX_CLK_N terminal. Conversely, if the phase difference between the data and the sampling clock is less than 90°, the opposite is true. Therefore, the clock carrying the duty cycle information is input to the clock comparator. By comparing the average voltage values ​​of MIX_CLK_P and MIX_CLK_N, the detection result of whether the phase difference between the data and the clock is greater than or less than 90° is obtained. That is, the output is 0 if the phase difference is greater than 90°, and the output is 1 if the phase difference is less than 90°. When the output of the orthogonal phase detection module shows a transition between 0 and 1, it indicates a 90° phase difference between the sampled data and the sampling clock during phase adjustment. This transition in the output is an important indicator for the digital circuit to determine the phase adjustment result.

[0035] Figure 7In the diagram, CLK_IN is the IN clock signal in the third-fourth phase clock signal, representing the clock IN after cross-point adjustment. CLK_IP is the IP clock signal in the third-fourth phase clock signal, representing the clock IN after cross-point adjustment. The IN data signal DATA_A of the encoded four-channel data represents the data sampled by the encoding module using the IN clock. The IP data signal DATA_C of the encoded four-channel data represents the data sampled by the encoding module using the IP clock. The four-phase clocks are typically represented by relative phases as IN, QN, IP, and QP, with I and Q differing by 90° and N and P differing by 180°. If the clock after cross-point adjustment is taken as IN and IP, the data output by the encoding module must also be the data sampled from the corresponding phase IN and IP clocks output by the alignment module.

[0036] Optionally, the mixer circuits H1, H2, H3, and H4 are Gilbert unit multipliers. When performing a mixing operation on the input signal, their output signal can be regarded as the XOR of the input signal.

[0037] In one specific embodiment, the execution steps of the digital module include: S1. The first counter is used to count the number of clock cycles. When the count of the first counter reaches n clock cycles, the second counter counts the first number of 1s output by the phase detection module and the second counter counts the second number of 0s output by the phase detection module, where n is an integer greater than or equal to 0. S2. Determine the size of the first quantity and the second quantity. If the first quantity is greater than the second quantity, set the flag to 1. If the first quantity is less than the second quantity, set the flag to 0. S3. Determine whether the current flag bit is the same as the flag bit of the previous round. If they are the same, keep the current best control signal unchanged (starting with the default value). If they are different, use the current control signal as the current best control signal and update the flag bit to the current flag bit. S4. Based on the monotonic change direction of the interpolation phase, linearly generate control signals CLKI_S and CLKQ_S covering the entire interpolation range of the alignment module, as well as a phase interpolation weight adjustment signal. Output the control signals CLKI_S, CLKQ_S, and the phase interpolation weight adjustment signal to the alignment module. The phase interpolation weight adjustment signal includes signals SI, SIB, SQ, SQB, SIQ_P, SIQ_PB, SIQ_N, and SIQ_NB.

[0038] S5. Based on the phase of the alignment module, traverse the preset number of times according to S1-S4, and count the best control signal that appears most frequently as the final best control signal. Then, output the final best control signal to the alignment module and lock the final best control signal unchanged.

[0039] Specifically, the phase detection module uses an RC filter circuit to filter out the average voltage value of the calibrated clock. A larger RC filter circuit results in better filtering and a more stable voltage value. However, a larger filter circuit also leads to a larger time constant, increasing the stabilization time of the filter circuit. Therefore, a digital filter is added to the digital module. A first counter is set to count to n clock cycles (i.e., waiting for the average voltage value filtered by the RC filter in the phase detection circuit to stabilize; the clock cycle is determined by the clock signal CLK input to the clock comparator, for example, 3-5MHz, and n is for example, 3). Then, a second and third counter are used to count the number of 1s and 0s output by the clock comparator in the phase detection module over n clock cycles, with the first counter cnt2 and the second counter cnt3 being the same. There are five possible statistical results: the first is all 1s, the second is all 0s, the third is a greater number of 1s than 0s, the fourth is a greater number of 0s than 1s, and the fifth is a number of 1s equal to the number of 0s. The first and second statistical results indicate that within these n clock cycles, the average voltage value of the circuit output clock with adjusted duty cycle corresponding to the control signal at this time, after RC filtering, does not exist. Figure 8 The crossover phenomenon shown in Figure (b) indicates that there is no point in the phase adjustment process where the sampled data and the sampling clock have a 90° phase difference; the third, fourth, and fifth results show that there is a point in the n clock cycles where the sampled data and the sampling clock have a 90° phase difference.

[0040] The control signal S_REG is continuously changed according to the phase rotator control code switching method for phase interpolation, and the phase difference between the data and the sampling clock increases / decreases linearly. There are five statistical results for the first quantity cnt2 and the second quantity cnt3. To reduce the complexity of the digital module in determining the point where the phase between the sampled data and the sampling clock exceeds 90°, it was found that detecting the crossover point of the average voltage value filtered out by the RC filter circuit during the adjustment process—that is, the transition point between 1 and 0 in the phase detection module output—is an important and effective judgment method. The magnitudes of the first quantity cnt2 and the second quantity cnt3 are compared, and a flag bit sign is set. When the first quantity cnt2 is greater than the second quantity cnt3, the flag bit sign=1; when the first quantity cnt2 is less than the second quantity cnt3, the flag bit sign=0. The flag bit sign obtained in this comparison is compared with the flag bit sign obtained after the previous round of delay adjustment. If they are the same, it means that there is no point where the sampled data and the sampling clock phase are 90° apart during the process of control signal change and sampling clock phase adjustment. Therefore, it is only necessary to update the current flag bit sign. If they are different, it means that there is a point where the sampled data and the sampling clock phase are 90° apart during the process of digital control signal change and sampling clock phase adjustment. That is, the transition point where the phase detection module outputs 1 and 0. Therefore, it is necessary to set the control signal S_REG (the current control signal) with the transition edge to the current best control signal S_REG_BEST and update the flag bit sign to the current flag bit.

[0041] To reduce detection errors, the phase rotator control code switching method is changed by setting the control signal to a preset number of times. That is, controlling all the phases of the set cases (e.g., 100 phases) through all control codes is set to once, and the preset number of times is the total number of times this case is completed, for example, traversing 3 times. Therefore, this embodiment increases the number of times the control signal is traversed to determine the best control signal obtained through steps S1-S4 for each traversal. After the traversal is completed, the best control signal that appears most frequently is determined as the final best control signal, and the final best control signal is output to the alignment module and kept locked. As the final control signal of the alignment module, the alignment module continues to work under the control of the final best control signal.

[0042] The retiming circuit adjustment effect of the present invention is as follows: Figure 9 As shown, by dynamically adjusting the phase difference between the sampling clock and the data, the edge of the sampling clock is accurately aligned with the center of the data eye diagram. After dynamically adjusting the phase, the phase difference between the sampling clock and the center of the data eye diagram is less than 1ps, achieving a good retiming effect.

[0043] The retiming circuit of this invention achieves a key technical solution through a dynamic phase calibration mechanism. This circuit utilizes a phase interpolator to dynamically adjust the sampling time, ensuring the sampling clock edge is precisely aligned with the center of the data eye diagram. This effectively reduces path delay differences caused by process variations, further improving indicators such as INL (integral nonlinearity error) and DNL (differential nonlinearity error). By eliminating nonlinear distortion caused by timing errors, high-frequency spurious suppression performance is improved, significantly enhancing SFDR. Furthermore, by introducing a lower jitter sampling clock at the data end, SNR is effectively improved compared to traditional solutions.

[0044] This invention uses a digital module to control the alignment module. The detection results from the phase detection module are processed and fed back to the digital module, which outputs a control signal to control the alignment circuit to adjust, thereby achieving automatic phase adjustment between the high-speed sampling clock and high-speed data. At the same time, the alignment circuit can also be controlled via SPI to achieve manual phase adjustment, which improves the reliability of the circuit.

[0045] This invention employs an architecture of an integral phase interpolator operating at a high speed, and introduces an improved octagonal phase rotator to achieve higher phase interpolation linearity and improve integral nonlinearity and differential nonlinearity.

[0046] This invention employs a phase interpolation circuit based on a CMOS tri-state inverter. By stacking resistors at the output end, the output impedance of the current source is increased, providing better power / area efficiency and higher interpolation linearity.

[0047] The digital part of this invention solves the nonlinearity problem of interpolation clock when the phase interpolator changes quadrants by adding four separate phase transitions; and improves the accuracy of phase interpolation by adopting a stepped control model based on an octagonal phase rotator.

[0048] The retiming circuit implemented in this invention can effectively improve the dynamic performance of DAC circuits, such as SFDR.

[0049] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0050] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0051] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0052] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A retiming circuit for an ultra-high-speed, high-precision DAC, characterized in that, include: The alignment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and select and adjust the phase of the first four-phase clock signal according to the control signals CLKI_S and CLKQ_S to obtain the second four-phase clock signal. The crosspoint adjustment module is used to receive the first four-phase clock signal after duty cycle and phase calibration, and to adjust the crosspoint of the first four-phase clock signal to obtain the third four-phase clock signal. The encoding module, connected to the alignment module, is used to encode the input data of the encoding module using the second four-phase clock signal to obtain the encoded four-channel data. The phase detection module, connected to the crosspoint adjustment module and the encoding module, is used to detect the phase between the third four-phase clock signal and the encoded four-channel data, and output the detection result of the phase difference between the data and the clock. The digital module, connected to the phase detection module and the alignment module, is used to update the current optimal control signal based on the detection result of the phase difference between the data and the clock, and generate control signals CLKI_S, CLKQ_S and phase interpolation weight adjustment signals for phase selection. The control signals CLKI_S, CLKQ_S and phase interpolation weight adjustment signals are output to the alignment module, and the final optimal control signal is locked after the adjustment is completed.

2. The retiming circuit according to claim 1, characterized in that, The alignment module includes two identical first phase interpolation circuits and a second phase interpolation circuit.

3. The retiming circuit according to claim 2, characterized in that, Both the first phase interpolation circuit and the second phase interpolation circuit include: A 4-to-2 phase selector is used to select, based on the control signals CLKI_S and CLKQ_S output by the digital module, two orthogonal phases of a first clock signal and a second clock signal from the first four-phase clock signal. The first integrating phase interpolator is connected to the four-to-two phase selector and is used to perform interpolation processing using the first clock signal to obtain the first interpolated clock signal. The second integral phase interpolator is connected to the four-to-two phase selector and is used to perform interpolation processing using the second clock signal to obtain the second interpolated clock signal. The CML2CMOS module and capacitor C1 are connected to the first integrating phase interpolator, the second integrating phase interpolator, and the CML2CMOS module. The first interpolation clock signal and the second interpolation clock signal charge and discharge the capacitor C1, forming a non-full-swing clock signal on the capacitor C1. The CML2CMOS module then shapes the non-full-swing clock signal into a full-swing single-ended clock signal. A single-ended to differential converter module, connected to the CML2CMOS module, is used to convert the full-swing clock signal into a differential two-phase clock signal.

4. The retiming circuit according to claim 3, characterized in that, The first integrating phase interpolator includes a first phase interpolation unit and a second phase interpolation unit. The first phase interpolation unit includes four parallel first phase interpolation sub-units, and the second phase interpolation unit includes eight parallel first phase interpolation sub-units. Each first phase interpolation sub-unit includes transistor M1, transistor M2, transistor M3, transistor M4, resistor R2, and resistor R3, wherein: The source of transistor M1 is connected to the power supply terminal, the drain of transistor M1 is connected to the source of transistor M2, the drain of transistor M2, resistor R2, resistor R3 and the drain of transistor M3 are connected in sequence, the source of transistor M3 is connected to the drain of transistor M4, and the source of transistor M4 is connected to the ground terminal. The gates of all transistors M1 and M4 are connected to the PHASE_I signal output of the 4-to-2 phase selector. The nodes connected to all resistors R2 and R3 are connected to capacitor C1. The gates of all transistors M2 in the first phase interpolation unit are connected to the SI signal terminal, and the gates of all transistors M3 are connected to the SIB signal terminal. The gates of all transistors M2 in the second phase interpolation unit are connected to the SIQ_P signal terminal, and the gates of all transistors M3 are connected to the SIQ_PB signal terminal. Here, signals SI and SIB are complementary, and signals SIQ_P and SIQ_PB are complementary.

5. The retiming circuit according to claim 4, characterized in that, Transistor M1 and transistor M2 are PMOS, and transistor M3 and transistor M4 are NMOS.

6. The retiming circuit according to claim 3, characterized in that, The second integrating phase interpolator includes a third phase interpolation unit and a fourth phase interpolation unit. The third phase interpolation unit includes four parallel second phase interpolation sub-units, and the fourth phase interpolation unit includes eight parallel second phase interpolation sub-units. Each second phase interpolation sub-unit includes transistors M5, M6, M7, and M8, resistor R4, and resistor R5, wherein: The source of transistor M5 is connected to the power supply terminal, the drain of transistor M5 is connected to the source of transistor M6, the drain of transistor M6, resistor R3, resistor R4 and the drain of transistor M7 are connected in sequence, the source of transistor M7 is connected to the drain of transistor M8, and the source of transistor M8 is connected to the ground terminal. The gates of all transistors M5 and M8 are connected to the PHASE_Q signal output of the 4-to-2 phase selector. The nodes connected to all resistors R4 and R5 are connected to capacitor C1. The gates of all transistors M6 in the third phase interpolation unit are connected to the SQ signal terminal, and the gates of all transistors M7 are connected to the SQB signal terminal. The gates of all transistors M6 in the fourth phase interpolation unit are connected to the SIQ_N signal terminal, and the gates of all transistors M3 are connected to the SIQ_NB signal terminal. Here, signals SQ and SQB are complementary, and signals SIQ_N and SIQ_NB are complementary.

7. The retiming circuit according to claim 6, characterized in that, Transistor M5 and transistor M6 are PMOS, and transistor M7 and transistor M8 are NMOS.

8. The retiming circuit according to claim 1, characterized in that, The phase detection module includes mixer circuits H1, H2, H3, and H4, a first RC filter circuit, a second RC filter circuit, and a clock comparator. The first RC filter circuit includes a resistor R6 and a capacitor C3. The second RC filter circuit includes a resistor R7 and a capacitor C4. The output terminals of mixer circuits H1 and H2 are connected to one end of resistor R6. The other end of resistor R6 is connected to one end of capacitor C3 and the positive input terminal of the clock comparator. The other end of capacitor C3 is connected to ground. The output terminals of mixer circuits H3 and H4 are connected to one end of resistor R7. The other end of resistor R7 is connected to one end of capacitor C4 and the negative input terminal of the clock comparator. The other end of capacitor C4 is connected to ground. The output terminal of the clock comparator is connected to a digital module. The mixing circuit H1 is used to receive the IN clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data. After mixing, it outputs a first mixing signal carrying duty cycle information. The mixer circuit H2 is used to receive the IP clock signal in the third four-phase clock signal and the IN data signal of the encoded four-channel data. After mixing, it outputs a first mixer signal carrying duty cycle information. The mixer circuit H3 is used to receive the IP clock signal in the third four-phase clock signal and the IP data signal of the encoded four-channel data. After mixing, a second mixer signal carrying duty cycle information is obtained. The mixer circuit H4 receives the IN clock signal from the third four-phase clock signal and the IN data signal from the encoded four-channel data. After mixing, it obtains a second mixer signal carrying duty cycle information. The first RC filter circuit is used to filter the first mixing signal to obtain a first average voltage value; The second RC filter circuit is used to filter the second mixing signal to obtain a second average voltage value; The clock comparator is used to receive the first average voltage value and the second average voltage value, and compare the first average voltage value and the second average voltage value to obtain the detection result of the phase difference between the data and the clock. When the detection result is that the phase difference is greater than 90°, the output is 0, and when the phase difference is less than 90°, the output is 1.

9. The retiming circuit according to claim 8, characterized in that, It also includes switches SW1 and SW2, wherein the first end of switch SW1 is connected to the encoding module and the second end is connected to the phase detection module, and the first end of switch SW2 is connected to the crosspoint adjustment module and the second end is connected to the phase detection module.

10. The retiming circuit according to claim 8, characterized in that, The execution steps of the digital module include: S1. The first counter is used to count the number of clock cycles. When the count of the first counter reaches n clock cycles, the second counter counts the first number of 1s output by the phase detection module and the second counter counts the second number of 0s output by the phase detection module, where n is an integer greater than or equal to 0. S2. Determine the size of the first quantity and the second quantity. If the first quantity is greater than the second quantity, set the flag to 1. If the first quantity is less than the second quantity, set the flag to 0. S3. Determine whether the current flag bit is the same as the flag bit of the previous round. If they are the same, keep the current best control signal unchanged. If they are different, use the current control signal as the current best control signal and update the flag bit to the current flag bit. S4. According to the monotonic change direction of the interpolation phase, linearly generate the phase selection control signal CLKI_S and control signal CLKQ_S covering the entire interpolation range of the alignment module, as well as the phase interpolation weight adjustment signal. The phase interpolation weight adjustment signal includes signal SI, signal SIB, signal SQ, signal SQB, signal SIQ_P, signal SIQ_PB, signal SIQ_N, and signal SIQ_NB. S5. Based on the phase of the alignment module, traverse the preset number of times according to S1-S4, and use the best control signal that appears most frequently as the final best control signal. Then, output the final best control signal to the alignment module and lock the final best control signal unchanged.

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