14 results about "Quadrature error" patented technology

Embodiments of the present disclosure provide a fully decoupled three-axis MEMS gyroscope and an electronic product. The gyroscope comprises: a substrate, and an X / Y proof mass, Z proof masses, driving structures and Z decoupling masses that are fixed on the substrate; the X / Y proof mass is arranged around outer sides of the Z proof masses, the driving structures and the Z decoupling masses; the Z proof masses are oppositely arranged in an x-axis direction; the driving structures are oppositely arranged at outer sides of the Z proof masses in the x-axis direction; and the Z decoupling masses are oppositely arranged at inner sides of the Z proof masses in the x-axis direction. The X / Y proof mass is elastically connected to the driving structures adjacent thereto, the Z proof masses are elastically connected to the driving structures adjacent thereto, and the Z decoupling masses are elastically connected to the Z proof masses adjacent thereto. The gyroscope improves the Coriolis conversion rate of the X / Y proof mass, maximizes the utilization of the chip area, reduces chip size and cost, and reduces coupling errors and quadrature errors, thereby improving sensing accuracy.

The application discloses an improved flux linkage observer position sensor observation method and system, comprising the following steps: constructing a motor model, and estimating a flux linkage vector; performing amplitude normalization processing on the flux linkage vector, and constructing a quadrature error signal; inputting a phase-locked loop, and obtaining a motor angle and a motor estimated rotating speed. The application has high adaptability, is small in system dependence degree, and is convenient to transplant in different systems.

The application discloses a zero intermediate frequency receiver quadrature error calibration method and device, in which an initial clock signal of a phase-locked loop of a zero intermediate frequency receiver is acquired; the initial clock signal is subjected to delay demodulation to determine a first clock signal and a second clock signal; wherein the phase difference between the first clock signal and the second clock signal is 180°; whether there is a duty cycle deviation between the first clock signal and the second clock signal is detected; when the duty cycle deviation is detected, the initial clock signal is calibrated based on the duty cycle deviation. Thus, by subjecting the initial clock signal of the phase-locked loop to delay demodulation, two opposite phase clock signals are determined, the duty cycle deviation of the two signals is used to feed back and adjust the duty cycle of the initial clock signal, a stable closed loop system is formed, and higher precision quadrature error calibration can be realized under the premise of lower static power consumption.

Methods, systems, and devices for four-phase clocking techniques, and in particular for a hybrid clock cycle correction and quadrature error correction (DCC-QEC) circuit, are described. The DCC-QEC circuit comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibrating without receiving a reference signal.The DCC-QEC circuit further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuits comprising a pair of phase dividers configured to convert the two-phase clock signals into four-phase clock signals, and an offset matcher configured to match clock offsets associated with a subset of the four-phase clock signals based on QEC matching codes and in an open-loop manner, wherein data from multiple lanes of parallel data channels based on the offset-matched four-phase clock signals are serialized and sent to outside a device comprising the DCC-QEC circuit.

Systems and methods are provided for generating timing control signals for phase and duty cycle trimming to reduce or eliminate a quadrature error of a clock signal in a memory device. The memory device employs a trim circuit to perform phase tuning to reduce or eliminate the quadrature error. Different phase tuning settings are used by the trim circuit for different types of quadrature errors. The trim circuit adjusts different phases of the clock signal independently or dependently based on the phase tuning settings.

The invention relates to phase and duty cycle trimming for multi-phase clocking. Systems and methods are provided for generating timing control signals tailored for phase and duty cycle to reduce or eliminate quadrature errors of clock signals in memory devices. The memory device employs a trimming circuit to perform phase tuning to reduce or eliminate the quadrature error. The trimming circuit uses different phase tuning settings for different types of quadrature errors. The trimming circuit adjusts different phases of the clock signal independently or dependently based on the phase tuning settings.

The invention discloses an improved flux linkage observer position-sensorless observation method and system, and the method comprises the following steps: constructing a motor model, and estimating a flux linkage vector; performing amplitude normalization processing on the flux linkage vector to construct an orthogonal error signal; and inputting a phase-locked loop to obtain a motor angle and a motor estimated rotating speed. The method is high in adaptability, small in system dependence degree and convenient to transplant in different systems.

The memory device includes a clock receiver receiving an external clock signal, a transmitter receiving first to Nth data in parallel and sequentially outputting the first to Nth data based on first to Nth clock signals including different phases, and a QEC circuit correcting a skew between the first to Nth clock signals, wherein the external clock signal includes a same frequency as the first to Nth clock signals, and the QEC circuit selectively receives the first clock signal among the first to Nth clock signals, generates the second clock signal including a phase different from a phase of the first clock signal based on a delay operation with respect to the first clock signal, and corrects the skew between the first to Nth clock signals by performing a phase comparison between the first to Nth clock signals generated based on the first and second clock signals.

A semiconductor memory device is provided. The semiconductor includes a data clock buffer that receives a data clock signal from a memory controller and outputs a pair of differential input signals, an edge delay controller that adjusts duty ratios of the pair of differential input signals based on a control code and outputs a pair of corrected clock signals, a first unit delay path circuit that generates four output clock signals having different phases based on the pair of corrected clock signals, a rising edge multiplexer that serially outputs data corresponding to a rising edge of each of the four output clock signals, a second unit delay path circuit that generates four duplicate clock signals having different phases based on the pair of corrected clock signals and a quadrature error correction circuit detector that detects a duty error based on the duplicate clock signals and outputs the control code.

Methods, systems, and devices for techniques for four-phase clocking, and in particular, to a hybrid duty-cycle correction and quadrature error correction (DCC-QEC) circuitry are described. The DCC-QEC circuitry comprises a DCC circuit configured to generate two-phase clock signals based on external clock signals. The DCC circuit is self-calibratable without receiving a reference signal. The DCC-QEC circuitry further comprises one or more QEC circuits coupled to the DCC circuit, each of the QEC circuit comprising a pair of phase splitters configured to convert the two-phase clock signals to four-phase clock signals, and a skew adjuster configured to adjust, based on QEC adjustment codes and in an open loop manner, clock skews associated with a subset of the four-phase clock signals, in which data from multiple lanes of parallel data channels are serialized based on the skew-adjusted four-phase clock signals and transmitted to external of a device comprising the DCC-QEC circuitry.

The application relates to the technical field of fluxgate sensor detection, and discloses a phase adjustment and quadrature error self-adaptive correction system for a fluxgate sensor, which comprises a digital phase shifter, a double-channel demodulation module and a processing unit. The digital phase shifter performs phase shifting on a first reference signal generated by a digital signal synthesizer and having a frequency of twice that of an excitation signal based on a shifted phase, and generates a shifted signal. The double-channel demodulation module demodulates an in-phase direct current component and a quadrature error component. The processing unit is configured to perform the following: when VQ satisfies a preset closed-loop suppression condition and is not zero, a compensation signal is generated and superimposed on a to-be-demodulated signal; when VQ does not satisfy the preset closed-loop suppression condition, an updated locking phase is generated, VQ is detected based on the updated locking phase, and a closed-loop suppression process of the quadrature error component is performed. The application can eliminate the quadrature error, improve the stability of a demodulated direct current signal and the demodulation sensitivity.

This disclosure provides an interface circuit for a capacitive MEMS sensor and a quadrature error suppression method. The quadrature error suppression method includes: acquiring a first-direction displacement from the capacitive MEMS sensor; providing a driving voltage to a driving electrode based on the first-direction displacement to cause the capacitive MEMS sensor to resonate along the first direction; acquiring a second-direction displacement from the capacitive MEMS sensor; amplifying and converting the second-direction displacement signal to obtain a detection signal containing a quadrature error component and an input angular velocity; performing in-phase quadrature demodulation on the detection signal; and obtaining an output signal characterizing the input angular velocity based on the demodulated quadrature component, in-phase component, and error elimination coefficient. The error elimination coefficient is obtained based on the changes in the in-phase component and quadrature component before and after an electrostatic force is applied to the torsion electrode. This application can obtain a more accurate error elimination coefficient, thereby improving the detection accuracy of the capacitive MEMS sensor.

A semiconductor system and a method for operating the semiconductor system are provided. The semiconductor system comprises a duty cycle corrector (DCC) and an analog quadrature error corrector (QEC). The DCC is configured to receive an input clock signal to adjust a duty cycle of the input clock signal and generate a first modified clock signal. The analog QEC is configured to receive the first modified clock signal. The analog QEC is configured to adjust a delay of the first modified clock signal and generate a first output clock signal and a second output clock signal. The second output clock signal delays or advances a quarter of period from the first output clock signal. The analog QEC comprises a first inverter chain, a phase error detector (PED) and a first low-pass filter (LPF).

A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.