Clock path and serialization circuit of SerDes with quarter-rate architecture

Abstract

The invention relates to a quarter-rate architecture SerDes clock path and a serialization circuit. The quarter-rate architecture SerDes clock path comprises a PLL (Phase Locked Loop) used for generating a differential clock signal consisting of two signals with opposite phases; the four-phase clock signal generation module is used for generating four four-phase clock signals with the phase difference of 90 degrees in sequence according to the differential clock signal; the retiming module is used for performing delay processing on the input four-way parallel data according to the four-phase clock signal, so that the delay interval among the input four-way parallel data is 1UI; the 1UI PULSE generation module is used for synthesizing clock signals of two adjacent phases in four-phase clock signals of which the phase difference is 90 degrees in sequence into clock signals with 1UI pulse width; and 4, the 1MUX module is used for synthesizing the four paths of delayed parallel data into one path of serial data according to the clock signal of the 1UI pulse width synthesized by the 1UI PULSE generation module.

Description

Technical Field

[0001] The present invention belongs to the field of high-speed serial link (Serializer / Deserializer, SerDes) clock path, and in particular to a quarter-rate architecture SerDes clock path and a serialization circuit. Background Art

[0002] Due to the increasing demand for total bandwidth in high-performance computing, networking / communications, and more recently, machine learning and artificial intelligence, the data rate per channel of the IO interface doubles every 3-4 years. Recent journals have demonstrated long-reach (LR) transceivers using four-level pulse amplitude modulation (PAM-4), which have been operating at speeds of up to 200Gb / s. When the operating rate reaches 56Gb / s, the traditional half-rate architecture SerDes has reached a clock rate requirement of 28Gb / s, which significantly increases the design cost of the clock. At this time, the same clock rate can be maintained by doubling the number of clock phases (four-phase clock), and the use of more phases such as eight-phase and sixteen-phase can further relax the clock requirements, but with the increase of clock phases, the complexity of the clock layout is also increased, requiring more complex multi-phase clock calibration, and at the same time, the parasitics of the last-level MUX are doubled, which greatly reduces the bandwidth. In summary, the current mainstream architecture in the field of high-speed SerDes is a quarter-rate architecture.

[0003] In high-speed serial interface (SerDes) circuits, the quality requirements of clock signals are extremely high. There are many ways to generate multi-phase clocks. The most commonly used method is to use high-frequency clock division, which is simple and stable, but in fact, the need to provide a higher-speed clock further increases the cost of clock design; polyphase filters are a commonly used open-loop method. The efficiency and flexibility of polyphase filters in signal processing allow the entire system to use a relatively low clock frequency to process high-speed signals without sacrificing performance. This can alleviate the demand for high-frequency clocks to a certain extent, thereby indirectly reducing the cost of clock design. This method also has obvious disadvantages. When this filter is cascaded to work in a wide frequency range, the I / Q gain mismatch and signal attenuation will be very serious, and the input signal can only be in the form of a sine wave to avoid phase errors caused by the presence of harmonic components. Another passive solution is to use an inductor hybrid structure. Since the inductor has good impedance characteristics at high frequencies, the inductor hybrid structure can effectively reduce the energy loss of the signal during transmission. In order to achieve the required inductance value and quality factor (Q value), a larger physical area is usually required to arrange the inductor coil. A large-area layout not only increases the manufacturing cost, but also affects the integration and reliability of the entire system. Summary of the invention

[0004] In order to solve the problems existing in the background technology, the present invention provides a clock path and serialization circuit of a quarter rate architecture SerDes, including: a PLL phase locked loop, a four-phase clock signal generation module, a retiming module, a 1UIPULSE generation module and a 4:1MUX module;

[0005] The PLL phase-locked loop is used to generate a differential clock signal consisting of two signals with opposite phases;

[0006] The four-phase clock signal generating module is used to generate a four-phase clock signal with four phases separated by 90° in sequence according to the differential clock signal;

[0007] The retiming module is used to delay the input four-way parallel data according to the four-phase clock signal, so that the delay interval between the input four-way parallel data is 1UI;

[0008] The 1UIPULSE generation module is used to synthesize clock signals of two adjacent phases in a four-phase clock signal with four phases separated by 90° into a clock signal with a pulse width of 1UI;

[0009] The 4:1MUX module is used to synthesize the delayed four-way parallel data into one-way serial data according to the clock signal of 1UI pulse width synthesized by the 1UIPULSE generation module.

[0010] Preferably, the four-phase clock signal generation module includes: 4 tetrahedral oscillators and 5 inverter groups; each tetrahedral oscillator includes 4 ports, represented as IP terminal, QP terminal, IN terminal and QN terminal; each inverter group includes 4 inverters; two signals with opposite phases constituting the differential clock signal are defined as CLKP and CLKN;

[0011] The signal CLKP passes through the first inverter in the first inverter group, the IP terminal of the first tetrahedral oscillator, the fourth inverter in the second inverter group, the QN terminal of the second tetrahedral oscillator, the third inverter in the third inverter group, the IN terminal of the third tetrahedral oscillator, the second inverter in the fourth inverter group, the QP terminal of the fourth tetrahedral oscillator and the first inverter in the fifth inverter group in sequence to obtain the CLKIP signal;

[0012] The signal CLKP passes through the second inverter in the first inverter group, the QP terminal of the first tetrahedral oscillator, the first inverter in the second inverter group, the IP terminal of the second tetrahedral oscillator, the fourth inverter in the third inverter group, the QN terminal of the third tetrahedral oscillator, the third inverter in the fourth inverter group, the IN terminal of the fourth tetrahedral oscillator and the second inverter in the fifth inverter group in sequence to obtain the CLKQP signal;

[0013] The signal CLKN passes through the third inverter in the first inverter group, the IN terminal of the first tetrahedral oscillator, the second inverter in the second inverter group, the QP terminal of the second tetrahedral oscillator, the first inverter in the third inverter group, the IP terminal of the third tetrahedral oscillator, the fourth inverter in the fourth inverter group, the QN terminal of the fourth tetrahedral oscillator and the third inverter in the fifth inverter group in sequence to obtain the CLKIN signal;

[0014] The signal CLKN passes through the fourth inverter in the first inverter group, the QN terminal of the first tetrahedral oscillator, the third inverter in the second inverter group, the IN terminal of the second tetrahedral oscillator, the second inverter in the third inverter group, the QP terminal of the third tetrahedral oscillator, the first inverter in the fourth inverter group, the IP terminal of the fourth tetrahedral oscillator and the fourth inverter in the fifth inverter group in sequence to obtain the CLKQN signal.

[0015] Preferably, the tetrahedral oscillator comprises: 8 inverters, denoted as I1 to I8; the output end of inverter I1, the output end of inverter I6, the input end of inverter I4 and the input end of inverter I8 are connected to the IP end of the tetrahedral oscillator; the output end of inverter I4, the output end of inverter I5, the input end of inverter I7 and the input end of inverter I3 are connected to the QP end of the tetrahedral oscillator; the input end of inverter I1, the input end of inverter I5, the output end of inverter I7 and the output end of inverter I2 are connected to the QN end of the tetrahedral oscillator; the output end of inverter I3, the output end of inverter I8, the input end of inverter I2 and the input end of inverter I6 are connected to the IN end of the tetrahedral oscillator.

[0016] Preferably, the CLKIP signal, the CLKQP signal, the CLKIN signal and the CLKQN signal form a four-phase clock signal; the phases of the CLKIP signal, the CLKQP signal, the CLKIN signal and the CLKQN signal differ by 90° respectively.

[0017] Preferably, the retiming module includes four delay branches; the first delay branch includes two D flip-flops connected in series; the second delay branch includes three D flip-flops connected in series; the third delay branch includes three D flip-flops connected in series; the fourth delay branch includes four D flip-flops connected in series; the four delay branches are respectively used to perform delay processing on four input parallel data.

[0018] Preferably, the clock input terminal of the first D flip-flop in the first delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the first delay branch is connected to the CLKIN signal;

[0019] The clock input terminal of the first D flip-flop in the second delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the second delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the second delay branch is connected to the CLKQN signal;

[0020] The clock input terminal of the first D flip-flop in the third delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the third delay branch is connected to the CLKIN signal; the clock input terminal of the third D flip-flop in the third delay branch is connected to the CLKIP signal;

[0021] The clock input terminal of the first D flip-flop in the fourth delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the fourth delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the fourth delay branch is connected to the CLKQN signal; the clock input terminal of the fourth D flip-flop in the fourth delay branch is connected to the CLKQP signal.

[0022] Preferably, the input terminal of the first D flip-flop in the first delay branch is defined to be connected to the parallel data D <0> , then the output end of the second D flip-flop in the first delay branch outputs the delayed parallel data D <0> DLY;

[0023] Define the input of the first D flip-flop in the second delay branch to be connected to the parallel data D <1> , then the output end of the third D flip-flop in the second delay branch outputs the delayed parallel data D <1> DLY;

[0024] Define the input of the first D flip-flop in the third delay branch to be connected to the parallel data D <2> , then the output end of the third D flip-flop in the third delay branch outputs the delayed parallel data D <2> DLY;

[0025] Define the input of the first D flip-flop in the fourth delay branch to be connected to the parallel data D <3> , then the output end of the fourth D flip-flop in the fourth delay branch outputs the delayed parallel data D <3> DLY; where the delayed parallel data D<n+1> DLY is the delay time of parallel data D <n>DLY is delayed by 1UI; n∈{0,1,2}.

[0026] Preferably, the 1UIPULSE generation module includes: 4 1UI signal generation units; each generation unit includes: P-type MOS tubes MP1-MP3; N-type MOS tubes MN1-MN3; inverters INV1-INV2; the source of MP1 and the source of MP2 are connected to VCC; the source of MN2 and the source of MN3 are grounded; the drain of MP1, the drain of MN1 and the input end of the inverter INV1 are connected; the source of MN1 and the drain of MN2 are connected; the drain of MP2 and the source of MP3 are connected; the drain of MP3, the drain of MN3 and the input end of the inverter INV2 are connected;

[0027] In the first 1UI signal generating unit, the gate of MN1 is connected to the CLKIP signal; the gate of MP1 and the gate of MN2 are connected to the CLKQN signal; the output end of the inverter INV1 outputs the clock signal N_0 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIN signal; the gate of MP2 and the gate of MN3 are connected to the CLKQP signal; the output end of the inverter INV2 outputs the clock signal P_0 with a pulse width of 1UI;

[0028] In the second 1UI signal generating unit, the gate of MN1 is connected to the CLKQP signal; the gate of MP1 and the gate of MN2 are connected to the CLKIP signal; the output end of the inverter INV1 outputs the clock signal N_1 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQN signal; the gate of MP2 and the gate of MN3 are connected to the CLKIN signal; the output end of the inverter INV2 outputs the clock signal P_1 with a pulse width of 1UI;

[0029] In the third 1UI signal generating unit, the gate of MN1 is connected to the CLKIN signal; the gate of MP1 and the gate of MN2 are connected to the CLKQP signal; the output end of the inverter INV1 outputs the clock signal N_2 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIP signal; the gate of MP2 and the gate of MN3 are connected to the CLKQN signal; the output end of the inverter INV2 outputs the clock signal P_2 with a pulse width of 1UI;

[0030] In the fourth 1UI signal generating unit, the gate of MN1 is connected to the CLKQN signal; the gate of MP1 and the gate of MN2 are connected to the CLKIN signal; the output end of the inverter INV1 outputs the clock signal N_3 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQP signal; the gate of MP2 and the gate of MN3 are connected to the CLKIP signal; the output end of the inverter INV2 outputs the clock signal P_3 with a pulse width of 1UI.

[0031] Preferably, the 4:1 MUX module comprises: 4 transmission gates TG1-TG4 and 5 inverters I01-I05; the input end of the inverter I01 is connected to the delayed parallel data D <0> DLY; the output of inverter I01 is connected to the input of transmission gate TG1; the input of inverter I02 is connected to the delayed parallel data D <1> DLY; the output of inverter I02 is connected to the input of transmission gate TG2; the input of inverter I03 is connected to the delayed parallel data D <2> DLY; the output of inverter I03 is connected to the input of transmission gate TG3; the input of inverter I04 is connected to the delayed parallel data D <3> DLY; the output of the inverter I04 is connected to the input of the transmission gate TG4; the output of the transmission gate TG1, the output of the transmission gate TG2, the output of the transmission gate TG3 and the output of the transmission gate TG4 are connected to the input of the inverter I05; the output of the inverter I05 outputs a serial data D out ; Among them, the control end C of the transmission gate TG1 is connected to the clock signal N_0 with a pulse width of 1UI; the C reverse end of the transmission gate TG1 is connected to the clock signal P_0 with a pulse width of 1UI; the control end C of the transmission gate TG2 is connected to the clock signal N_1 with a pulse width of 1UI; the C reverse end of the transmission gate TG2 is connected to the clock signal P_1 with a pulse width of 1UI; the control end C of the transmission gate TG3 is connected to the clock signal N_2 with a pulse width of 1UI; the C reverse end of the transmission gate TG3 is connected to the clock signal P_2 with a pulse width of 1UI; the control end C of the transmission gate TG4 is connected to the clock signal N_3 with a pulse width of 1UI; the C reverse end of the transmission gate TG4 is connected to the clock signal P_3 with a pulse width of 1UI.

[0032] The present invention has at least the following beneficial effects

[0033] Compared with the half-rate architecture SerDes serialization circuit, the present invention significantly reduces the clock frequency required at the same rate, and relaxes the timing requirements of the last stage retiming circuit of the serialization; at the same time, the four-phase clock signal generation module based on the injection-locked ring oscillator provided by the present invention greatly avoids the use of high-multiple clocks, and has more advantages in loss, power consumption, and area compared to traditional passive solutions. The 1UIPULSE generation circuit provided in this article has a better control matching effect on the transmission gate than the traditional solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the circuit architecture of the present invention;

[0035] Figure 2 Schematic diagram of the circuit architecture of the four-phase clock signal generating module of the present invention;

[0036] Figure 3 is a schematic diagram of a basic ring oscillator architecture in an embodiment of the present invention;

[0037] Figure 4 It is a timing diagram of the four-phase clock signal generating module of the present invention;

[0038] Figure 5 is a schematic diagram of the architecture of the retiming module of the present invention;

[0039] Figure 6 is a timing diagram of the retiming module of the present invention;

[0040] Figure 7 This is a schematic diagram of the architecture of the 4:1 MUX module of the present invention;

[0041] Figure 8 This is a schematic diagram of the architecture of the 1UIPULSE generation module of the present invention;

[0042] Fig. 9 It is a schematic diagram of the overall circuit of the present invention. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0044] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0045] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0046] See also Figure 1 , the present invention provides a clock path and serialization circuit of a quarter rate architecture SerDes, including: a PLL phase locked loop, a four-phase clock signal generation module, a retiming module, a 1UIPULSE generation module and a 4:1MUX module;

[0047] The PLL phase-locked loop is used to generate a differential clock signal consisting of two signals with opposite phases;

[0048] The four-phase clock signal generating module is used to generate a four-phase clock signal with four phases separated by 90° in sequence according to the differential clock signal;

[0049] The retiming module is used to delay the input four-way parallel data according to the four-phase clock signal, so that the delay interval between the input four-way parallel data is 1UI;

[0050] The 1UIPULSE generation module is used to synthesize clock signals of two adjacent phases in a four-phase clock signal with four phases separated by 90° into a clock signal with a pulse width of 1UI;

[0051] The 4:1MUX module is used to synthesize the delayed four-way parallel data into one-way serial data according to the clock signal of 1UI pulse width synthesized by the 1UIPULSE generation module.

[0052] See also Figure 2 Preferably, the four-phase clock signal generation module includes: 4 tetrahedral oscillators and 5 inverter groups; each tetrahedral oscillator includes 4 ports, represented as IP terminal, QP terminal, IN terminal and QN terminal; each inverter group includes 4 inverters; two signals with opposite phases constituting the differential clock signal are defined as CLKP and CLKN;

[0053] The signal CLKP passes through the first inverter in the first inverter group, the IP terminal of the first tetrahedral oscillator, the fourth inverter in the second inverter group, the QN terminal of the second tetrahedral oscillator, the third inverter in the third inverter group, the IN terminal of the third tetrahedral oscillator, the second inverter in the fourth inverter group, the QP terminal of the fourth tetrahedral oscillator and the first inverter in the fifth inverter group in sequence to obtain the CLKIP signal;

[0054] The signal CLKP passes through the second inverter in the first inverter group, the QP terminal of the first tetrahedral oscillator, the first inverter in the second inverter group, the IP terminal of the second tetrahedral oscillator, the fourth inverter in the third inverter group, the QN terminal of the third tetrahedral oscillator, the third inverter in the fourth inverter group, the IN terminal of the fourth tetrahedral oscillator and the second inverter in the fifth inverter group in sequence to obtain the CLKQP signal;

[0055] The signal CLKN passes through the third inverter in the first inverter group, the IN terminal of the first tetrahedral oscillator, the second inverter in the second inverter group, the QP terminal of the second tetrahedral oscillator, the first inverter in the third inverter group, the IP terminal of the third tetrahedral oscillator, the fourth inverter in the fourth inverter group, the QN terminal of the fourth tetrahedral oscillator and the third inverter in the fifth inverter group in sequence to obtain the CLKIN signal;

[0056] The signal CLKN passes through the fourth inverter in the first inverter group, the QN terminal of the first tetrahedral oscillator, the third inverter in the second inverter group, the IN terminal of the second tetrahedral oscillator, the second inverter in the third inverter group, the QP terminal of the third tetrahedral oscillator, the first inverter in the fourth inverter group, the IP terminal of the fourth tetrahedral oscillator and the fourth inverter in the fifth inverter group in sequence to obtain the CLKQN signal.

[0057] In this embodiment, the connection relationship between the components of the four-phase clock signal generation module is as follows: the input end of the first inverter and the input end of the second inverter in the first inverter group are connected to the signal CLKP;

[0058] The input terminal of the third inverter and the input terminal of the fourth inverter in the first inverter group are connected to the signal CLKN;

[0059] The output end of the first inverter in the first inverter group and the input end of the fourth inverter in the second inverter group are connected to the IP end of the first tetrahedral oscillator; the output end of the fourth inverter in the second inverter group and the input end of the third inverter in the third inverter group are connected to the QN end of the second tetrahedral oscillator; the output end of the third inverter in the third inverter group and the input end of the second inverter in the fourth inverter group are connected to the IN end of the third tetrahedral oscillator; the output end of the second inverter in the fourth inverter group and the input end of the first inverter in the fifth inverter group are connected to the QP end of the fourth tetrahedral oscillator; the output end of the first inverter in the fifth inverter group outputs the CLKIP signal;

[0060] The output end of the second inverter in the first inverter group and the input end of the first inverter in the second inverter group are connected to the QP end of the first tetrahedral oscillator; the output end of the first inverter in the second inverter group and the input end of the fourth inverter in the third inverter group are connected to the IP end of the second tetrahedral oscillator; the output end of the fourth inverter in the third inverter group and the input end of the third inverter in the fourth inverter group are connected to the QN end of the third tetrahedral oscillator; the output end of the third inverter in the fourth inverter group and the input end of the second inverter in the fifth inverter group are connected to the IN end of the fourth tetrahedral oscillator; the output end of the second inverter in the fifth inverter group outputs the CLKQP signal;

[0061] The output end of the third inverter in the first inverter group and the input end of the second inverter in the second inverter group are connected to the IN end of the first tetrahedral oscillator; the output end of the second inverter in the second inverter group and the input end of the first inverter in the third inverter group are connected to the QP end of the second tetrahedral oscillator; the output end of the first inverter in the third inverter group and the input end of the fourth inverter in the fourth inverter group are connected to the IP end of the third tetrahedral oscillator; the output end of the fourth inverter in the fourth inverter group and the input end of the third inverter in the fifth inverter group are connected to the QN end of the fourth tetrahedral oscillator; the output end of the third inverter in the fifth inverter group outputs the CLKIN signal;

[0062] The output end of the fourth inverter in the first inverter group and the input end of the third inverter in the second inverter group are connected to the QN end of the first tetrahedral oscillator; the output end of the third inverter in the second inverter group and the input end of the second inverter in the third inverter group are connected to the IN end of the second tetrahedral oscillator; the output end of the second inverter in the third inverter group and the input end of the first inverter in the fourth inverter group are connected to the QP end of the third tetrahedral oscillator; the output end of the first inverter in the fourth inverter group and the input end of the fourth inverter in the fifth inverter group are connected to the IP end of the fourth tetrahedral oscillator; the output end of the fourth inverter in the fifth inverter group outputs the CLKQN signal.

[0063] Preferably, the tetrahedral oscillator comprises: 8 inverters, denoted as I1 to I8; the output end of inverter I1, the output end of inverter I6, the input end of inverter I4 and the input end of inverter I8 are connected to the IP end of the tetrahedral oscillator; the output end of inverter I4, the output end of inverter I5, the input end of inverter I7 and the input end of inverter I3 are connected to the QP end of the tetrahedral oscillator; the input end of inverter I1, the input end of inverter I5, the output end of inverter I7 and the output end of inverter I2 are connected to the QN end of the tetrahedral oscillator; the output end of inverter I3, the output end of inverter I8, the input end of inverter I2 and the input end of inverter I6 are connected to the IN end of the tetrahedral oscillator.

[0064] In this embodiment, the main body of the four-phase clock signal generation module is composed of four tetrahedral oscillators and five inverters to form an injection-locked ring oscillator. Figure 2 The principle is to obtain complementary orthogonal phases from an inverter-based ring oscillator, as shown in Figure 3 As shown, assuming that this structure is in an oscillating state (i.e., ignoring the high and low level flips caused by the inverter), there is a 90° phase separation between A, B, C, and D. However, the ring oscillator composed of an even number of inverters generally cannot oscillate, but locks A and C at 1\0, and B and D at 0\1. Therefore, it is necessary to introduce a pair of cross-coupled inverters at their input and output nodes to counteract the locked state. Figure 2 As shown, a middle circle of inverters is introduced, I6 / I8 constitutes a pair of cross-coupled inverters, and I5 / I7 constitutes a pair of cross-coupled inverters. Assuming that IP is locked to 1, QP=0, IN=1, and QN=0. At this time, inverter I6 tends to pull IP to 0, inverter I8 tends to pull IN to 0, and I5 and I7 tend to pull nodes QP and QN to 1, destroying the locked state of the peripheral ring oscillator. Therefore, the entire tetrahedral oscillator can be started, and a 90° phase difference is generated between the four nodes IP, QN, QP, and IN. The oscillation frequency of the tetrahedral oscillator is adjusted to be close to the clock frequency. The oscillation frequency of the tetrahedral oscillator can be locked by inputting a differential clock to generate a four-phase clock signal, and the phase difference between the four-phase clocks can be reduced by cascading multiple tetrahedral oscillators. However, too many cascaded tetrahedral oscillators will bring greater power consumption. Considering the compromise, the present invention uses four cascaded tetrahedral oscillators to generate a stable four-phase clock. Its timing diagram is as follows: Figure 4 shown.

[0065] Preferably, the CLKIP signal, the CLKQP signal, the CLKIN signal and the CLKQN signal form a four-phase clock signal; the phases of the CLKIP signal, the CLKQP signal, the CLKIN signal and the CLKQN signal differ by 90° respectively.

[0066] See also Figure 5 Preferably, the retiming module includes four delay branches; the first delay branch includes two D flip-flops connected in series, that is, the output end Q of the first D flip-flop is connected to the input end D of the second D flip-flop; the second delay branch includes three D flip-flops connected in series, that is, the output end Q of the first D flip-flop is connected to the input end D of the second D flip-flop, and the output end Q of the second D flip-flop is connected to the input end D of the third D flip-flop; the third delay branch includes three D flip-flops connected in series, that is, the output end Q of the first D flip-flop is connected to the input end D of the second D flip-flop, and the output end Q of the second D flip-flop is connected to the input end D of the third D flip-flop; the fourth delay branch includes four D flip-flops connected in series, that is, the output end Q of the first D flip-flop is connected to the input end D of the second D flip-flop, the output end Q of the second D flip-flop is connected to the input end D of the third D flip-flop, and the output end Q of the third D flip-flop is connected to the input end D of the fourth D flip-flop; the four delay branches are respectively used to delay the input four-way parallel data.

[0067] Preferably, the clock input terminal of the first D flip-flop in the first delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the first delay branch is connected to the CLKIN signal;

[0068] The clock input terminal of the first D flip-flop in the second delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the second delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the second delay branch is connected to the CLKQN signal;

[0069] The clock input terminal of the first D flip-flop in the third delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the third delay branch is connected to the CLKIN signal; the clock input terminal of the third D flip-flop in the third delay branch is connected to the CLKIP signal;

[0070] The clock input terminal of the first D flip-flop in the fourth delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the fourth delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the fourth delay branch is connected to the CLKQN signal; the clock input terminal of the fourth D flip-flop in the fourth delay branch is connected to the CLKQP signal.

[0071] Preferably, the input terminal of the first D flip-flop in the first delay branch is defined to be connected to the parallel data D <0> , then the output end of the second D flip-flop in the first delay branch outputs the delayed parallel data D <0> DLY;

[0072] Define the input of the first D flip-flop in the second delay branch to be connected to the parallel data D <1> , then the output end of the third D flip-flop in the second delay branch outputs the delayed parallel data D <1> DLY;

[0073] Define the input of the first D flip-flop in the third delay branch to be connected to the parallel data D <2> , then the output end of the third D flip-flop in the third delay branch outputs the delayed parallel data D <2> DLY;

[0074] Define the input of the first D flip-flop in the fourth delay branch to be connected to the parallel data D <3> , then the output end of the fourth D flip-flop in the fourth delay branch outputs the delayed parallel data D <3> DLY; where the delayed parallel data D<n+1> DLY is the delay of parallel data D <n>DLY is delayed by 1UI; n∈{0,1,2}.

[0075] Preferably, the 1UIPULSE generation module includes: 4 1UI signal generation units; each generation unit includes: P-type MOS tubes MP1-MP3; N-type MOS tubes MN1-MN3; inverters INV1-INV2; the source of MP1 and the source of MP2 are connected to VCC; the source of MN2 and the source of MN3 are grounded; the drain of MP1, the drain of MN1 and the input end of the inverter INV1 are connected; the source of MN1 and the drain of MN2 are connected; the drain of MP2 and the source of MP3 are connected; the drain of MP3, the drain of MN3 and the input end of the inverter INV2 are connected;

[0076] In the first 1UI signal generating unit, the gate of MN1 is connected to the CLKIP signal; the gate of MP1 and the gate of MN2 are connected to the CLKQN signal; the output end of the inverter INV1 outputs the clock signal N_0 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIN signal; the gate of MP2 and the gate of MN3 are connected to the CLKQP signal; the output end of the inverter INV2 outputs the clock signal P_0 with a pulse width of 1UI;

[0077] In the second 1UI signal generating unit, the gate of MN1 is connected to the CLKQP signal; the gate of MP1 and the gate of MN2 are connected to the CLKIP signal; the output end of the inverter INV1 outputs the clock signal N_1 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQN signal; the gate of MP2 and the gate of MN3 are connected to the CLKIN signal; the output end of the inverter INV2 outputs the clock signal P_1 with a pulse width of 1UI;

[0078] In the third 1UI signal generating unit, the gate of MN1 is connected to the CLKIN signal; the gate of MP1 and the gate of MN2 are connected to the CLKQP signal; the output end of the inverter INV1 outputs the clock signal N_2 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIP signal; the gate of MP2 and the gate of MN3 are connected to the CLKQN signal; the output end of the inverter INV2 outputs the clock signal P_2 with a pulse width of 1UI;

[0079] In the fourth 1UI signal generating unit, the gate of MN1 is connected to the CLKQN signal; the gate of MP1 and the gate of MN2 are connected to the CLKIN signal; the output end of the inverter INV1 outputs the clock signal N_3 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQP signal; the gate of MP2 and the gate of MN3 are connected to the CLKIP signal; the output end of the inverter INV2 outputs the clock signal P_3 with a pulse width of 1UI.

[0080] In this embodiment, the retiming module is composed of a plurality of D flip-flops. Figure 5 As shown, the input four-way parallel data is delayed, and the timing diagram is as follows Figure 6 shown.

[0081] Preferably, the 4:1 MUX module comprises: 4 transmission gates TG1-TG4 and 5 inverters I01-I05; the input end of the inverter I01 is connected to the delayed parallel data D <0> DLY; the output of inverter I01 is connected to the input of transmission gate TG1; the input of inverter I02 is connected to the delayed parallel data D <1> DLY; the output of inverter I02 is connected to the input of transmission gate TG2; the input of inverter I03 is connected to the delayed parallel data D <2> DLY; the output of inverter I03 is connected to the input of transmission gate TG3; the input of inverter I04 is connected to the delayed parallel data D <3> DLY; the output of the inverter I04 is connected to the input of the transmission gate TG4; the output of the transmission gate TG1, the output of the transmission gate TG2, the output of the transmission gate TG3 and the output of the transmission gate TG4 are connected to the input of the inverter I05; the output of the inverter I05 outputs a serial data D out ; Among them, the control end C of the transmission gate TG1 is connected to the clock signal N_0 with a pulse width of 1UI; the C reverse end of the transmission gate TG1 is connected to the clock signal P_0 with a pulse width of 1UI; the control end C of the transmission gate TG2 is connected to the clock signal N_1 with a pulse width of 1UI; the C reverse end of the transmission gate TG2 is connected to the clock signal P_1 with a pulse width of 1UI; the control end C of the transmission gate TG3 is connected to the clock signal N_2 with a pulse width of 1UI; the C reverse end of the transmission gate TG3 is connected to the clock signal P_2 with a pulse width of 1UI; the control end C of the transmission gate TG4 is connected to the clock signal N_3 with a pulse width of 1UI; the C reverse end of the transmission gate TG4 is connected to the clock signal P_3 with a pulse width of 1UI.

[0082] In this embodiment, the 4:1 MUX module is composed of a transmission gate and an inverter, such as Figure 7 As shown, the 1UIPULSE generation module provides a 1UI pulse width clock signal to control the transmission gate switch, merging the four parallel 4UI data into one serial data. The 1UIPULSE generation module is composed of a dynamic AND gate and an OR gate. Figure 8 As shown in the figure, the high level and low level of the overlapping clocks of the adjacent two phases are synthesized respectively to generate opposite 1UI pulse width signals to control the N-tube and P-tube of the transmission gate respectively. Compared with directly using the inverter to generate opposite signals, this method can better avoid the pull-up and pull-down mismatch caused by the inverter delay in ultra-high-speed scenarios. The final timing diagram is shown in Fig. 9 shown.

[0083] In summary, compared with the half-rate architecture SerDes serialization circuit, the present invention significantly reduces the clock frequency required at the same rate (at a 56Gb / s operating rate, the required clock frequency is reduced from 28GHz to 14GHz), and at the same time relaxes the timing requirements of the last-stage retiming circuit of the serialization (the last-stage retiming module under the half-rate architecture needs to run at 28Gb / s, while it only needs to run at 14Gb / s under a quarter rate); at the same time, the four-phase clock signal generation module based on the injection-locked ring oscillator provided by the present invention greatly avoids the use of high-multiple clocks, and compared with the traditional passive solution (using a large number of resistors and capacitors to form a multi-phase filter network), it has more advantages in terms of loss, power consumption, and area. The 1UIPULSE generation circuit provided in this article has a better control matching effect on the transmission gate than the traditional solution (the traditional solution uses an inverter to directly produce a reverse control signal, which has a delay and causes a transmission gate control mismatch).

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.< / n> < / n>

Claims

1. A clock path and serialization circuit of a quarter rate SerDes architecture, characterized in that: include: PLL phase-locked loop, four-phase clock signal generation module, retiming module, 1UIPULSE generation module and 4:1MUX module; The PLL phase-locked loop is used to generate a differential clock signal consisting of two signals with opposite phases; The four-phase clock signal generating module is used to generate a four-phase clock signal with four phases separated by 90° in sequence according to the differential clock signal; The retiming module is used to delay the input four-way parallel data according to the four-phase clock signal, so that the delay interval between the input four-way parallel data is 1UI; The 1UIPULSE generation module is used to synthesize clock signals of two adjacent phases in a four-phase clock signal with four phases separated by 90° into a clock signal with a pulse width of 1UI; The 4:1MUX module is used to synthesize the delayed four-way parallel data into one-way serial data according to the clock signal of 1UI pulse width synthesized by the 1UIPULSE generation module.

2. The clock path and serialization circuit of a quarter rate SerDes according to claim 1, characterized in that: The four-phase clock signal generation module includes: 4 tetrahedral oscillators and 5 inverter groups; each tetrahedral oscillator includes 4 ports, represented as IP terminal, QP terminal, IN terminal and QN terminal; each inverter group includes 4 inverters; two signals with opposite phases constituting the differential clock signal are defined as CLKP and CLKN; The signal CLKP passes through the first inverter in the first inverter group, the IP terminal of the first tetrahedral oscillator, the fourth inverter in the second inverter group, the QN terminal of the second tetrahedral oscillator, the third inverter in the third inverter group, the IN terminal of the third tetrahedral oscillator, the second inverter in the fourth inverter group, the QP terminal of the fourth tetrahedral oscillator and the first inverter in the fifth inverter group in sequence to obtain the CLKIP signal; The signal CLKP passes through the second inverter in the first inverter group, the QP terminal of the first tetrahedral oscillator, the first inverter in the second inverter group, the IP terminal of the second tetrahedral oscillator, the fourth inverter in the third inverter group, the QN terminal of the third tetrahedral oscillator, the third inverter in the fourth inverter group, the IN terminal of the fourth tetrahedral oscillator and the second inverter in the fifth inverter group in sequence to obtain the CLKQP signal; The signal CLKN passes through the third inverter in the first inverter group, the IN terminal of the first tetrahedral oscillator, the second inverter in the second inverter group, the QP terminal of the second tetrahedral oscillator, the first inverter in the third inverter group, the IP terminal of the third tetrahedral oscillator, the fourth inverter in the fourth inverter group, the QN terminal of the fourth tetrahedral oscillator and the third inverter in the fifth inverter group in sequence to obtain the CLKIN signal; The signal CLKN passes through the fourth inverter in the first inverter group, the QN terminal of the first tetrahedral oscillator, the third inverter in the second inverter group, the IN terminal of the second tetrahedral oscillator, the second inverter in the third inverter group, the QP terminal of the third tetrahedral oscillator, the first inverter in the fourth inverter group, the IP terminal of the fourth tetrahedral oscillator and the fourth inverter in the fifth inverter group in sequence to obtain the CLKQN signal.

3. The clock path and serialization circuit of a quarter rate SerDes according to claim 2, characterized in that: The tetrahedron oscillator includes: 8 inverters, denoted as I1~I8; the output end of inverter I1, the output end of inverter I6, the input end of inverter I4 and the input end of inverter I8 are connected to the IP end of the tetrahedron oscillator; the output end of inverter I4, the output end of inverter I5, the input end of inverter I7 and the input end of inverter I3 are connected to the QP end of the tetrahedron oscillator; the input end of inverter I1, the input end of inverter I5, the output end of inverter I7 and the output end of inverter I2 are connected to the QN end of the tetrahedron oscillator; the output end of inverter I3, the output end of inverter I8, the input end of inverter I2 and the input end of inverter I6 are connected to the IN end of the tetrahedron oscillator.

4. The clock path and serialization circuit of a quarter rate SerDes according to claim 2, characterized in that: The CLKIP signal, CLKQP signal, CLKIN signal and CLKQN signal form a four-phase clock signal; the phases of the CLKIP signal, CLKQP signal, CLKIN signal and CLKQN signal differ by 90° respectively.

5. The clock path and serialization circuit of a quarter rate SerDes according to claim 4, characterized in that: The retiming module includes four delay branches; the first delay branch includes two D flip-flops connected in series; the second delay branch includes three D flip-flops connected in series; the third delay branch includes three D flip-flops connected in series; the fourth delay branch includes four D flip-flops connected in series; the four delay branches are respectively used to delay processing of four input parallel data.

6. The clock path and serialization circuit of a quarter rate SerDes according to claim 5, characterized in that: The clock input terminal of the first D flip-flop in the first delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the first delay branch is connected to the CLKIN signal; The clock input terminal of the first D flip-flop in the second delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the second delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the second delay branch is connected to the CLKQN signal; The clock input terminal of the first D flip-flop in the third delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the third delay branch is connected to the CLKIN signal; the clock input terminal of the third D flip-flop in the third delay branch is connected to the CLKIP signal; The clock input terminal of the first D flip-flop in the fourth delay branch is connected to the CLKIP signal; the clock input terminal of the second D flip-flop in the fourth delay branch is connected to the CLKQP signal; the clock input terminal of the third D flip-flop in the fourth delay branch is connected to the CLKQN signal; the clock input terminal of the fourth D flip-flop in the fourth delay branch is connected to the CLKQP signal.

7. The clock path and serialization circuit of a quarter rate SerDes according to claim 6, characterized in that: Define the first D flip-flop in the first delay branch to have its input connected to the parallel data D <0> , then the output end of the second D flip-flop in the first delay branch outputs the delayed parallel data D <0> DLY; Define the input of the first D flip-flop in the second delay branch to be connected to the parallel data D <1> , then the output end of the third D flip-flop in the second delay branch outputs the delayed parallel data D <1> DLY; Define the input of the first D flip-flop in the third delay branch to be connected to the parallel data D <2> , then the output end of the third D flip-flop in the third delay branch outputs the delayed parallel data D <2> DLY; Define the input of the first D flip-flop in the fourth delay branch to be connected to the parallel data D <3> , then the output end of the fourth D flip-flop in the fourth delay branch outputs the delayed parallel data D <3> DLY; where the delayed parallel data D<n+1> DLY is the delay time of parallel data D <n> DLY is delayed by 1UI; n∈{0,1,2}.< / n> 8. The clock path and serialization circuit of a quarter rate SerDes according to claim 7, characterized in that: The 1UIPULSE generation module includes: 4 1UI signal generation units; each generation unit includes: P-type MOS tubes MP1-MP3; N-type MOS tubes MN1-MN3; inverters INV1-INV2; the source of MP1 and the source of MP2 are connected to VCC; the source of MN2 and the source of MN3 are grounded; the drain of MP1, the drain of MN1 and the input end of the inverter INV1 are connected; the source of MN1 and the drain of MN2 are connected; the drain of MP2 and the source of MP3 are connected; the drain of MP3, the drain of MN3 and the input end of the inverter INV2 are connected; In the first 1UI signal generating unit, the gate of MN1 is connected to the CLKIP signal; the gate of MP1 and the gate of MN2 are connected to the CLKQN signal; the output end of the inverter INV1 outputs the clock signal N_0 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIN signal; the gate of MP2 and the gate of MN3 are connected to the CLKQP signal; the output end of the inverter INV2 outputs the clock signal P_0 with a pulse width of 1UI; In the second 1UI signal generating unit, the gate of MN1 is connected to the CLKQP signal; the gate of MP1 and the gate of MN2 are connected to the CLKIP signal; the output end of the inverter INV1 outputs the clock signal N_1 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQN signal; the gate of MP2 and the gate of MN3 are connected to the CLKIN signal; the output end of the inverter INV2 outputs the clock signal P_1 with a pulse width of 1UI; In the third 1UI signal generating unit, the gate of MN1 is connected to the CLKIN signal; the gate of MP1 and the gate of MN2 are connected to the CLKQP signal; the output end of the inverter INV1 outputs the clock signal N_2 with a pulse width of 1UI; the gate of MP3 is connected to the CLKIP signal; the gate of MP2 and the gate of MN3 are connected to the CLKQN signal; the output end of the inverter INV2 outputs the clock signal P_2 with a pulse width of 1UI; In the fourth 1UI signal generating unit, the gate of MN1 is connected to the CLKQN signal; the gate of MP1 and the gate of MN2 are connected to the CLKIN signal; the output end of the inverter INV1 outputs the clock signal N_3 with a pulse width of 1UI; the gate of MP3 is connected to the CLKQP signal; the gate of MP2 and the gate of MN3 are connected to the CLKIP signal; the output end of the inverter INV2 outputs the clock signal P_3 with a pulse width of 1UI.

9. The clock path and serialization circuit of a quarter rate SerDes according to claim 8, characterized in that: The 4:1 MUX module comprises: 4 transmission gates TG1-TG4 and 5 inverters I01-I05; the input end of the inverter I01 is connected to the delayed parallel data D <0> DLY; the output of inverter I01 is connected to the input of transmission gate TG1; the input of inverter I02 is connected to the delayed parallel data D <1> DLY; the output of inverter I02 is connected to the input of transmission gate TG2; the input of inverter I03 is connected to the delayed parallel data D <2> DLY; the output of inverter I03 is connected to the input of transmission gate TG3; the input of inverter I04 is connected to the delayed parallel data D <3> DLY; the output of the inverter I04 is connected to the input of the transmission gate TG4; the output of the transmission gate TG1, the output of the transmission gate TG2, the output of the transmission gate TG3 and the output of the transmission gate TG4 are connected to the input of the inverter I05; the output of the inverter I05 outputs a serial data D out ; Among them, the control end C of the transmission gate TG1 is connected to the clock signal N_0 with a pulse width of 1UI; the C reverse end of the transmission gate TG1 is connected to the clock signal P_0 with a pulse width of 1UI; the control end C of the transmission gate TG2 is connected to the clock signal N_1 with a pulse width of 1UI; the C reverse end of the transmission gate TG2 is connected to the clock signal P_1 with a pulse width of 1UI; the control end C of the transmission gate TG3 is connected to the clock signal N_2 with a pulse width of 1UI; the C reverse end of the transmission gate TG3 is connected to the clock signal P_2 with a pulse width of 1UI; the control end C of the transmission gate TG4 is connected to the clock signal N_3 with a pulse width of 1UI; the C reverse end of the transmission gate TG4 is connected to the clock signal P_3 with a pulse width of 1UI.

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