Dual-channel parallel processing architecture for ultrahigh frequency partial discharge signals

Abstract

In order to solve the problem that quick response and distortionless recording of ultrahigh-frequency partial discharge signals are difficult to realize when accidental pulses are generated in the prior art, the invention relates to a dual-channel parallel processing architecture for ultrahigh-frequency partial discharge signals, which comprises a signal cloning circuit and a signal processing circuit, the ultrahigh-frequency partial discharge module is used for receiving ultrahigh-frequency partial discharge signals and synchronously outputting the ultrahigh-frequency partial discharge signals as first target signals and second target signals after lossless copying; the low-gain channel circuit is used for performing buffer transmission for maintaining an original bandwidth and a dynamic range on the first target signal to generate a first gain signal; the high-gain channel circuit is used for performing gain amplification on the second target signal to generate a second gain signal; the digital signal processing unit is used for performing synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; and the FPGA chip is integrated in the digital signal processing unit and is used for performing fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm and generating a fusion signal.

Description

Technical Field

[0001] The present invention relates to the technical field of measuring electrical variables, and in particular to a dual-channel parallel processing architecture for ultra-high frequency partial discharge signals. Background Art

[0002] UHF PD signals usually refer to nanosecond electromagnetic pulses with a frequency range of 300MHz to 3GHz and a dynamic range of 60 to 100dB, which are often generated in transient discharge processes at insulation defects of power equipment. Such signals have the characteristics of large amplitude span, short time domain characteristics, and strong sporadic nature. In the dynamic capture process, they are easily affected by the mutual constraints of the dynamic range and sensitivity of the detection system: strong signals are prone to saturation distortion in high-gain mode, while weak signals are easily submerged by background noise in low-gain mode. Therefore, it is crucial to achieve distortion-free recording of the nanosecond waveform of UHF PD signals in a single discharge event to achieve high-precision detection.

[0003] Existing technologies usually detect and record UHF PD signals based on an architecture that combines an automatic gain mechanism with a single amplification path. However, the dynamic range of its signal detection is limited to 30-40 dB, and its gain adjustment of the signal relies on an analog feedback mechanism. When faced with occasional pulses of UHF PD signals, this type of architecture has a significant delay in gain switching, so it is often unable to achieve dynamic response and complete gain matching for occasional pulses within nanoseconds, which may result in the loss of leading pulses or clipping of subsequent pulses. This dynamic response bottleneck severely limits the ability of this type of architecture to fully capture occasional pulses, making it difficult to record the full waveform of UHF PD signals without distortion.

[0004] In view of this, there is an urgent need to provide a dual-channel parallel processing architecture for UHF partial discharge signals to achieve rapid response and complete capture of UHF partial discharge signals. Summary of the invention

[0005] Based on the foregoing analysis, the main purpose of the present invention is to provide a dual-channel parallel processing architecture for UHF partial discharge signals to solve the problem that the traditional automatic gain detection architecture is difficult to achieve rapid response and distortion-free recording of UHF partial discharge signals when occasional pulses occur.

[0006] For this, a dual-channel parallel processing architecture for ultra-high frequency partial discharge signals of the present invention includes: a signal cloning circuit, configured to receive the ultra-high frequency partial discharge signal, and after losslessly replicating the ultra-high frequency partial discharge signal, synchronously output it as a first target signal and a second target signal; a low-gain channel circuit, configured to perform buffered transmission of the first target signal while maintaining the original bandwidth and dynamic range, and output it as a first gain signal; a high-gain channel circuit, configured to perform gain amplification on the second target signal, and output it as a second gain signal; a digital signal processing unit, configured to perform synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; an FPGA chip, integrated in the digital signal processing unit, configured to perform fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm, and generate a fusion signal.

[0007] Preferably, the signal cloning circuit includes a power divider, a first matching resistor, a second matching resistor, a first delay element group, a second delay element group, and a phase compensation network; the input end of the power divider is configured to receive the ultra-high frequency partial discharge signal, and the power divider is configured to replicate the ultra-high frequency partial discharge signal, and synchronously output the replicated ultra-high frequency partial discharge signal through a first output end and a second output end; and the first end of the first matching resistor is electrically connected to the first output end of the power divider, the second end of the first matching resistor is electrically connected to the first end of the first delay element group through the first end of the first delay element group, and the second end of the first delay element group is electrically connected to the first end of the phase compensation network; the first end of the second matching resistor is electrically connected to the second output end of the power divider, the second end of the second matching resistor is electrically connected to the first end of the second delay element group, and the second end of the second delay element group is electrically connected to the second end of the phase compensation network; the phase compensation network is configured to perform synchronous phase compensation on the ultra-high frequency partial discharge signals output from the first output end and the second output end of the power divider.

[0008] More preferably, the phase compensation network includes a phase-shifting inductor, a first matching capacitor, and a second matching capacitor; the first end of the phase-shifting inductor is electrically connected to the first end of the first matching capacitor, the second end of the phase-shifting inductor is electrically connected to the second end of the second matching capacitor, and the second end of the first matching capacitor is electrically connected to the first end of the second matching capacitor; and the first end of the phase-shifting inductor serves as the first end of the phase compensation network, and is configured to extract the first target signal; the second end of the phase-shifting inductor serves as the second end of the phase compensation network, and is configured to extract the second target signal.

[0009] Preferably, the low-gain channel circuit includes a duplexer, a selection switch, and a first programmable gain amplifier. The duplexer is configured to perform frequency isolation on the first target signal to maintain the original bandwidth and dynamic range of the first target signal. Its input terminal is used to receive the first target signal, its first output terminal is used to output the first isolation signal, and its second output terminal is used to output the second isolation signal. The first input terminal of the selection switch is used to receive the second isolation signal, its second input terminal is used to receive a reference ground signal, and its output terminal is used to output the second isolation signal or the reference ground signal. The first input terminal of the first programmable gain amplifier is used to receive the first isolation signal or the reference ground signal, its second input terminal is used to receive the second isolation signal, and its output terminal is used to output the first gain signal.

[0010] Preferably, the high-gain channel circuit includes a filter network, a differential amplifier, a band-pass filter, a radio frequency switch, and a second programmable gain amplifier. The first terminal of the filter network is used to receive the second target signal, and its second terminal is used to output an initial filtered signal. The input terminal of the differential amplifier is used to receive the initial filtered signal, its first output terminal is used to output a positive-phase amplified signal, and its second output terminal is used to output a negative-phase amplified signal. The first input terminal of the radio frequency switch is used to receive the positive-phase amplified signal, its second input terminal is used to receive the negative-phase amplified signal, and its output terminal is used to selectively output the positive-phase amplified signal or the negative-phase amplified signal. The input terminal of the band-pass filter is used to communicate with the output terminal of the radio frequency switch, and the output terminal of the band-pass filter is used to output a band-pass filtered signal corresponding to the positive-phase amplified signal or the negative-phase amplified signal. The first input terminal of the second programmable gain amplifier is used to receive the band-pass filtered signal, and its output terminal is used to output the second gain signal.

[0011] More preferably, the filter network includes a first filter capacitor, a filter inductor, and a second filter capacitor. The first terminal of the first filter capacitor is electrically connected to the first terminal of the second filter capacitor, and the second terminal of the first filter capacitor is electrically connected to the first terminal of the filter inductor. The second terminal of the filter inductor is electrically connected to the second terminal of the second filter capacitor. And the first terminal of the second filter capacitor serves as the first terminal of the filter network, and the second terminal of the second filter capacitor serves as the second terminal of the filter network.

[0012] Preferably, the digital signal processing unit further includes a clock processing unit circuit and at least two independent ADC acquisition unit circuits. The clock processing unit is configured to perform synchronous clock control on the low-gain channel circuit and the high-gain channel circuit, and is used to drive the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit them to the FPGA chip.

[0013] Preferably, the waveform fusion splicing algorithm performs fusion splicing processing on the first gain signal and the second gain signal and generates a fusion signal, including: determining the first gain signal and the second gain signal for an effective overlapping time period, where represents the signal sampling points in the effective overlapping time period; Normalize the first gain signal and the second gain signal respectively: ; where, is the gain coefficient of the low-gain channel circuit, is the gain coefficient of the high-gain channel circuit; Generate a fusion signal using the weighted superposition method : ; where, is the weighting coefficient of the second gain signal.

[0014] As a further preference, it further includes: obtaining the spectral information of the first gain signal and the spectral information of the second gain signal , and determining the weighting coefficient of the second gain signal based on the spectral information: ; where, is the spectral correlation term adjustment factor, is the spectral correlation index, is the index frequency of the spectrum, and outputs a weight adjustment factor within the range of [0, 1]; is the base weight of the second gain signal; is the real-time signal-to-noise ratio of the second gain signal; is the real-time signal-to-noise ratio of the first gain signal.

[0015] Preferably, it further includes determining the base weight of the second gain signal: ; where: represents the signal strength of the second gain signal at the current signal sampling point; represents the weak signal threshold, represents the strong signal threshold, is the empirical coefficient, is the signal attenuation rate.

[0016] A dual-channel parallel processing architecture for ultra-high frequency partial discharge signals of the present invention has the following beneficial effects: First, different from the traditional automatic gain architecture limited by the fixed gain adjustment mechanism, this architecture realizes the lossless replication of ultra-high frequency partial discharge signals based on the signal cloning circuit, and performs dual-channel parallel processing on ultra-high frequency partial discharge signals by combining the low-gain channel circuit and the high-gain channel circuit. By using the differential gain design of the low-gain channel circuit and the high-gain channel circuit, it synchronously realizes the wide dynamic range maintenance of strong amplitude pulses and the high-sensitivity amplification of weak signals, and can also achieve a fast response to ultra-high frequency partial discharge signals when occasional pulses occur.

[0017] Second, different from the traditional architecture that relies on the automatic gain control method of feedback adjustment after the signal is stable, this architecture realizes real-time control of dual-channel clock synchronization through the digital signal processing unit, and dynamically fuses the two signals based on the waveform splicing algorithm integrated in the FPGA chip. It can directly extract the complete strong signal of the low-gain channel and the enhanced weak signal of the high-gain channel in a single acquisition, and effectively fuse the two to achieve the complete capture of ultra-high frequency partial discharge signals.

[0018] Third, considering that there is a risk of oversaturation for strong signals when amplifying the gain of ultra-high frequency partial discharge signals, this architecture uses the waveform fusion and splicing algorithm integrated in the FPGA chip to effectively fuse the first gain signal and the second gain signal. While avoiding signal clipping caused by too high gain in a single channel circuit, it effectively restores the weak detail information missed by the low-gain channel circuit, thus avoiding the signal distortion risk brought by relying solely on hardware gain adjustment. Description of the Drawings

[0019] Figure 1 is a schematic diagram of the dual-channel parallel processing architecture for ultra-high frequency partial discharge signals according to an embodiment of the present invention; Figure 2 is a signal cloning circuit diagram according to an embodiment of the present invention; Figure 3 is a low-gain channel circuit diagram according to an embodiment of the present invention; Figure 4 is a high-gain channel circuit diagram according to an embodiment of the present invention; Figure 5 is a front-end input circuit diagram according to an embodiment of the present invention; Figure 6 is a fusion and splicing flow chart of the first gain signal and the second gain signal according to an embodiment of the present invention. Detailed Embodiments

[0020] The present invention will be described in more detail below in conjunction with the accompanying drawings. It should be noted that the description of the present invention with reference to the accompanying drawings below is illustrative only and not restrictive.

[0021] Where possible, various different embodiments described below can be recombined with each other to form other embodiments not shown in the following description; various different technical features described below can also be recombined with each other to form other embodiments not shown in the following description.

[0022] Please refer to the attached Figures 1 to 6 。

[0023] Ultra-high frequency partial discharge signals, that is, nanosecond electromagnetic pulses with a frequency range of 300 MHz to 3 GHz and a dynamic range of 60 to 100 dB, usually refer to local discharge signals generated during the deterioration process of power equipment. Such signals have obvious transient characteristics. The duration of a single pulse is usually on the nanosecond scale, and the occurrence time has a high degree of randomness and suddenness. Therefore, extremely high requirements are placed on the dynamic range and response speed of the signal acquisition system in actual detection. Since this signal may contain weak early fault information and may also be accompanied by occasional strong pulse interference, the automatic gain control (AGC) technology is widely used to adapt to the change of signal strength.

[0024] However, the existing automatic gain control technology is usually limited to the dynamic response of a single channel and is equipped with a fixed gain adjustment mechanism. It is limited to the adaptability to partial discharge signals with strong suddenness and large amplitude changes, and depends on the feedback adjustment process after the signal stabilizes. Therefore, it is impossible to capture the complete waveform characteristics of occasional pulse signals in a timely and accurate manner, and there is an obvious gap from the actual requirements of on-line monitoring and fault warning of partial discharges in power equipment.

[0025] Therefore, to solve the problem that the traditional automatic gain detection architecture is difficult to achieve fast response and distortion-free recording of ultra-high frequency partial discharge signals when occasional pulses occur, this embodiment provides a dual-channel parallel processing architecture for ultra-high frequency partial discharge signals. Based on the principle of cloning circuits, the ultra-high frequency partial discharge signals are losslessly replicated, and two-channel parallel signals with synchronous time domain and consistent spectrum are generated. The low-gain channel circuit and the high-gain channel circuit with differential gain amplification are used to maintain a wide dynamic range and perform high-sensitivity detection on the ultra-high frequency partial discharge signals respectively. The two-channel circuit is synchronously clock-controlled based on a digital signal processing unit, and based on the integrated FPGA chip (field programmable gate array) in it, the waveform fusion splicing algorithm is used to perform fusion splicing processing on the output signals of the low-gain channel and the high-gain channel, and the finally generated fusion signal is used as the complete waveform of the ultra-high frequency partial discharge signal.

[0026] Please refer to Figure 1, A dual-channel parallel processing architecture for ultra-high frequency partial discharge signals in this embodiment mainly includes a signal cloning circuit, a low-gain channel circuit, a high-gain channel circuit, and a digital signal processing unit. Among them, the signal cloning circuit is used to perform lossless replication on the ultra-high frequency partial discharge signal after receiving it, making the two signals synchronized in time domain and consistent in spectrum, and outputting them in two paths as the first target signal and the second target signal. The first target signal is received by the low-gain channel circuit, which buffers and transmits the first target signal while maintaining the original bandwidth and dynamic range, and then outputs the first target signal as the first gain signal. The second target signal is received by the high-gain channel circuit, which amplifies the second target signal and then outputs the second target signal as the second gain signal. In the above architecture, the digital signal processing unit performs synchronous clock control on the low-gain channel and the high-gain channel by sending a synchronous clock signal, so as to ensure the time domain consistency of their output signals. At the same time, an FPGA chip is integrated on the digital signal processing unit. The FPGA chip can splice the waveforms of the first gain signal with wide dynamic range retention and the second gain signal with high-sensitivity amplification through the integrated waveform fusion and splicing algorithm, and finally obtain the fusion signal, that is, the complete ultra-high frequency partial discharge signal waveform. This embodiment realizes the lossless replication and dual-channel synchronous output of ultra-high frequency partial discharge signals through the signal cloning circuit, uses the low-gain channel to maintain the original dynamic range and waveform integrity of strong signals, and at the same time improves the signal-to-noise ratio of weak signals through the high-gain channel. Then, the dual-channel signals are intelligently spliced through the waveform fusion algorithm integrated in the FPGA chip, synchronously realizing the distortion-free recording of strong signals and the high-sensitivity detection of weak signals in a single acquisition, effectively solving the problems such as incomplete capture of occasional pulses and waveform distortion caused by the dynamic response lag and limited gain switching in the prior art.

[0027] In this embodiment, the dual-channel parallel processing architecture performs differential gain on the first target signal and the second target signal transmitted after being replicated by the signal cloning circuit by respectively setting a low-gain channel circuit and a high-gain channel circuit. Among them, the gain range of the low-gain channel circuit can be 0 to 6 dB, which is mainly used to capture strong amplitude partial discharge pulse signals, ensure their complete transmission without clipping distortion, and at the same time take into account signal integrity and transmission loss compensation. The gain range of the high-gain channel circuit can be 20 to 40 dB, which is used to amplify weak signals step by step, significantly improving the signal-to-noise ratio, so as to effectively detect low-amplitude discharge signals caused by early faults. This design fully considers the characteristics of ultra-high frequency partial discharge signals with a wide dynamic range (usually exceeding 60 dB) and a large amplitude span, as well as the implementation requirements such as system noise floor, input limitations, and circuit stability.

[0028] Please refer to Figure 2, in order to further achieve lossless replication of UHF partial discharge signals, in a preferred embodiment, the signal cloning circuit is designed in detail: the signal cloning circuit includes a power divider W1, a first matching resistor R3, a second matching resistor R4, a first delay element group, a second delay element group, and a phase compensation network. Among them, the power divider W1 includes an input terminal IN, a first output terminal O1, and a second output terminal O2. After receiving the UHF partial discharge signal at its input terminal IN, the power divider W1 duplicates the signal equivalently and outputs it through the first output terminal and the second output terminal respectively. The first output terminal O1 of the power divider W1 is electrically connected to the first end of the first matching resistor R3, and the second end of the first matching resistor R3 is electrically connected to the first end of the first delay element group. The second end of the first delay element group is electrically connected to the first end of the phase compensation network. At the same time, the second output terminal O2 of the power divider W1 is electrically connected to the first end of the second matching resistor R4, and the second end of the second matching resistor R4 is electrically connected to the first end of the second delay element group. The second end of the second delay element group is electrically connected to the second end of the phase compensation network. Both the first matching resistor R3 and the second matching resistor R4 are used to prevent reflection or loss of the UHF partial discharge signal in the corresponding path during transmission due to impedance mismatch, so as to maintain lossless transmission of the UHF partial discharge signal. The first delay element group and the second delay element group are used to adjust the transmission time of the UHF partial discharge signal in the corresponding path to compensate for any signal delay caused by physical path differences or other factors that may exist. The phase compensation network is used to adjust and calibrate the phase of the UHF partial discharge signals output corresponding to the first output terminal O1 and the second output terminal O2 of the power divider W1, so as to assist the overall signal cloning circuit to complete lossless replication and transmission of the UHF partial discharge signal. Such a circuit design can ensure that the finally extracted first target signal and second target signal are consistent in the time domain.

[0029] Please refer to Figure 2, in order to further achieve the time-domain consistency of the ultra-high frequency partial discharge signals output from the first output terminal O1 and the second output terminal O2 of the power divider W1, in a further preferred embodiment, both the first delay element and the second delay element group adopt delay lines, delay inductors and delay capacitors; among them, the delay line can provide a time delay on the physical path, the delay inductor can adjust the phase delay of the ultra-high frequency partial discharge signal, and the delay capacitor can cooperate with the delay inductor to finely adjust the phase and amplitude of the ultra-high frequency partial discharge signal, so as to ensure the time-domain consistency of the two signals to the greatest extent. More specifically, the first delay element group includes a first delay inductor L4, a first delay line and a first delay capacitor C4, wherein the first end of the first delay inductor L4 is electrically connected to the second end of the first matching resistor R3 through the first delay line, the second end of the first delay inductor L4 is electrically connected to the first end of the first delay capacitor C4, and the second end of the first delay capacitor C4 is electrically connected to the first end of the phase compensation network. The second delay element group includes a second delay inductor L5, a second delay line and a second delay capacitor C5, wherein the first end of the second delay inductor L5 is electrically connected to the second end of the second matching resistor R4 through the second delay line, the second end of the second delay inductor L5 is electrically connected to the first end of the second delay capacitor C5, and the second end of the second delay capacitor C5 is electrically connected to the second end of the phase compensation network. This electrical connection method ensures that the signal can pass through multiple delay links in sequence during the transmission process and finally converge to the phase compensation network for unified correction. By using the above components in combination, the signal cloning circuit can finely adjust the delay amount of each path of signal while making a lossless copy of the ultra-high frequency partial discharge signal, so as to eliminate the delay deviation caused by physical factors, component parameters, etc. of the two signals after replication and during transmission to the greatest extent. It should be noted that in the actual application scenario, the number, combination and model of the corresponding delay elements can also be designed according to the characteristics of the elements themselves, so as to increase their flexibility in use.

[0030] Please refer to Figure 2, in order to further achieve phase compensation for ultra-high frequency signals and assist the power divider in making a lossless replication of ultra-high frequency partial discharge signals, in a further preferred embodiment, a specific design of the phase compensation network is made: the phase compensation network includes a phase-shifting inductor L6, a first matching capacitor C6, and a second matching capacitor C7. The first end of the phase-shifting inductor L6 is electrically connected to the first end of the first matching capacitor C6, the second end of the phase-shifting inductor L6 is electrically connected to the second end of the second matching capacitor C7, and the second end of the first matching capacitor C6 is electrically connected to the first end of the second matching capacitor C7, so that the above components form a complete phase compensation network. Among them, the first end of the phase-shifting inductor L6 serves as the first end of the phase compensation network, and its second end serves as the second end of the phase compensation network. The above design enables the first end and the second end of the phase compensation network to cooperate with the first output end O1 and the second output end O2 of the power divider W1 respectively. By reasonably configuring the parameters of its phase-shifting inductor and matching capacitor, the phase compensation network can perform precise phase correction on both signals simultaneously, while preventing the two signals from interfering with each other, thereby maintaining the integrity and consistency of their respective spectra.

[0031] Please refer to Figure 3, in order to perform buffered transmission of the first target signal while maintaining the original bandwidth and dynamic range, in another preferred embodiment, the low-gain channel circuit is designed as follows: The low-gain channel circuit mainly includes a duplexer D1, a selection switch S1, and a first programmable gain amplifier U4. After the input end of the duplexer D1 receives the first target signal, it performs frequency isolation on the first target signal itself and generates a first isolation signal and a second isolation signal; the first output end of the duplexer outputs the first isolation signal, and its second output end outputs the second isolation signal. By introducing a duplexer to perform frequency isolation processing on the first target signal, the initial division of the signal frequency band is realized, thereby effectively suppressing the mutual interference between different frequency bands. The first input end of the above selection switch S1 communicates with the second output end of the duplexer D1 and receives the second isolation signal, and its second input end is electrically connected to the ground wire through an isolation device for receiving a reference ground signal. The output end of the selection switch S1 outputs the second isolation signal or the reference ground signal. The design of the selection switch enables the signal input to the digital-to-analog converter to be flexibly switched between the first isolation signal and the reference ground signal, thereby enhancing the adaptability and anti-interference ability of the system. The first input end AIN# of the first programmable gain amplifier U4 communicates with the first output end of the duplexer D1 and receives the first isolation signal, and its second input end AIN communicates with the output end of the selection switch S1 and receives the second isolation signal or the reference ground signal. After the first programmable gain amplifier U4 receives the first isolation signal, the reference ground signal, or the second isolation signal, it processes and outputs a first gain signal. In this embodiment, the input signal is separated into a main frequency band containing effective partial discharge information and a secondary frequency band that may contain interference information, that is, the first isolation signal and the second isolation signal, by a duplexer, and then the second isolation signal or the reference ground signal is intelligently switched to be input to the first programmable gain amplifier through the selection switch, so as to suppress noise while retaining the complete dynamic range of the main signal from 0 to 60 dB; the first programmable gain amplifier optimally amplifies the first isolation signal by 0 to 6 dB to ensure that strong pulses are undistorted, and selectively processes the second isolation signal for auxiliary analysis or complete suppression. Finally, a first gain signal with both a wide dynamic range (total harmonic distortion < 1%) and a high signal-to-noise ratio (signal-to-noise ratio > 40 dB) is output, realizing high-fidelity acquisition and flexible analysis of ultra-high frequency partial discharge signals in a complex environment.

[0032] Please refer to Figure 4, in order to perform stable gain amplification on the second target signal, in another preferred embodiment, the high-gain channel circuit is designed as follows: The high-gain channel circuit is configured with a filter network, a differential amplifier U5, a band-pass filter U7, a radio frequency switch U6, and a second programmable gain amplifier U8. Among them, the first end of the filter network receives the second target signal. After filtering the second target signal, the initial filtered signal is output from its second end. The filter network can effectively suppress out-of-band noise and interference, improve the signal-to-noise ratio, and maintain the purity of the output signal. Next, the input terminal +IN of the differential amplifier U5 receives the initial filtered signal. After differential amplification at its reference input terminal -IN, its first output terminal +OUT and second output terminal -OUT respectively output a positive-phase amplified signal and a negative-phase amplified signal. The differential amplifier U5 can perform high-fidelity amplification on the filtered second gain signal. In a high-noise environment, using differential signals (positive and negative phases) can effectively suppress common-mode interference. The differential amplifier U5 amplifies the difference between the two signals while ignoring the common noise components. The first input terminal RF1 of the radio frequency switch U6 is used to receive the positive-phase amplified signal, its second input terminal RF2 is used to receive the negative-phase amplified signal, and its output terminal RFC is used to output the positive-phase amplified signal or the negative-phase amplified signal. The radio frequency switch U6 can provide a signal path selection function while reducing signal reflection, thereby maintaining signal integrity. The input terminal of the band-pass filter U7 is used to receive the positive-phase amplified signal or the negative-phase amplified signal, and its output terminal is used to output the band-pass filtered signal corresponding to the positive-phase amplified signal or the negative-phase amplified signal. The band-pass filtered signal can only retain the signal components within the target frequency range, so it has strong anti-interference ability. The first input terminal of the second programmable gain amplifier U8 is used to receive the band-pass filtered signal, and its output terminal is used to output the second gain signal.

[0033] Please refer to Figure 4 , in order to preliminarily filter the noise in the second target signal before the input differential amplifier, in a further preferred embodiment, the filter network is specifically designed as follows: The filter network includes a first filter capacitor C11, a filter inductor L7, and a second filter capacitor C12, which can effectively suppress the high-frequency noise of the second target signal before the signal enters the differential amplifier U5, thereby improving the signal-to-noise ratio and stability of the subsequent amplification stage. Among them, the first end of the first filter capacitor C11 serves as the first end of the filter network. The second end of the first filter capacitor C11 is electrically connected to the first end of the filter inductor L7. The second end of the filter inductor L7 is electrically connected to the first end of the second filter capacitor C12. The second end of the second filter capacitor C12 is electrically connected to the input terminal +IN of the differential amplifier U5. Through the coordinated action of the first filter capacitor C11, the filter inductor L7, and the second filter capacitor C12, the above filter network effectively suppresses the DC component, low-frequency interference, and high-frequency noise in the second target signal, improves the signal-to-noise ratio and frequency selectivity of the signal, and at the same time optimizes the impedance matching and system stability.

[0034] Please refer to Figure 5 ,In order to perform basic processing on the ultra-high frequency partial discharge signal before the input signal cloning circuit, in another preferred embodiment, an input front-end circuit is also designed in the dual-channel parallel architecture, which includes a wireless chip U1, a transient voltage suppressor U2, a filter U3, a transformer T1, and a matching network; wherein the wireless chip U1 is used to receive and transmit the initial ultra-high frequency partial discharge signal, and the transient voltage suppressor U2 is electrically connected between the RF terminal of the wireless chip and the input terminal IN of the filter U3 to perform transient voltage stabilization on the initial ultra-high frequency partial discharge signal. And the input terminal of the filter U3 is used to receive the initially ultra-high frequency partial discharge signal after transient voltage stabilization, and its output terminal is used to output the filtered initial ultra-high frequency partial discharge signal. The input terminal of the transformer T1 receives the filtered initial ultra-high frequency partial discharge signal, and its output terminal outputs the ultra-high frequency partial discharge signal after isolation and impedance transformation. The first end of the matching network is electrically connected to the output end point of the transformer T1, and its second end is electrically connected to the GND terminal of the wireless chip, and is used to perform radio frequency reflection processing on the ultra-high frequency partial discharge signal. And in the first end of the matching network, the ultra-high frequency partial discharge signal is extracted. In this embodiment, after the wireless chip U1 receives the initial ultra-high frequency partial discharge signal, the overvoltage pulse is clamped by the transient voltage suppressor U2 to protect the backend circuit; the band-pass filter U3 suppresses out-of-band interference and improves the signal-to-noise ratio; the transformer T1 realizes impedance matching and electrical isolation to reduce common-mode interference; the π-type matching network further optimizes the radio frequency characteristics and minimizes the reflection loss while extracting the signal. This preprocessing chain makes the signal of the input signal cloning circuit have better purity and stability, providing a high-quality signal source for subsequent dual-channel processing.

[0035] Please refer to Figure 5 ,In order to perform radio frequency reflection processing on the ultra-high frequency partial discharge signal, in a further preferred embodiment, a detailed design is carried out on the matching network: it includes an input filter capacitor C1, a signal tuning inductor L2, a resonant capacitor C3, an output filter capacitor C2, an output matching inductor L3, and a load resistor R2. The first ends of the input filter capacitor C1 and the output filter capacitor C1 are both electrically connected to the GND terminal of the wireless chip, and serve as the first end of the matching network. The second end of the input filter capacitor C1 is electrically connected to the first end of the signal tuning inductor L2, and the second end of the signal tuning inductor L2 is electrically connected to the first end of the resonant capacitor C3. The second end of the output filter capacitor C2 is electrically connected to the first end of the output matching inductor, and the second end of the output matching inductor is electrically connected to the first end of the load resistor. And the second ends of the resonant capacitor C3 and the load resistor R2 are both electrically connected to the output terminal of the transformer, serving as The second end of the matching network. In the above circuit design, the input filter capacitor C1 provides a grounding path for high-frequency interference to protect the front-end chip; the signal tuning inductor L2 and the resonant capacitor C3 form a series resonant circuit to provide the best path for the target frequency signal; the output filter capacitor C2 and the output matching inductor L3 work together to further filter out stray signals and achieve impedance matching with the subsequent equipment; the load resistor R2 simulates the actual load to absorb the effective signal energy and prevent signal reflection. The overall structure not only improves the signal integrity and system stability but also enhances the detection sensitivity to weak partial discharge signals.

[0036] To further illustrate the control of the dual-channel parallel processing architecture of the digital signal processing unit for ultra-high frequency partial discharge signals, in a further preferred embodiment, the digital signal processing unit is described in detail, including a clock processing unit circuit and at least two independent ADC acquisition unit circuits (analog-to-digital conversion acquisition unit circuits). The clock processing unit is used to perform synchronous clock control on the low-gain channel circuit and the high-gain channel circuit, and is used to drive the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit them to the FPGA chip. This design eliminates the clock offset problem in traditional multi-channel acquisitions, ensuring the waveform reconstruction accuracy of subsequent ultra-high frequency partial discharge signals on the nanosecond time scale to prevent distortion of the final fused waveform.

[0037] Please refer to Figure 6 , because the dynamic range of ultra-high frequency partial discharge signals is extremely large, with weak discharge pulses and background noise coexisting in the signals, a single gain amplifier or single-channel dynamic regulation cannot effectively capture them, resulting in response blocking and signal distortion. To perform waveform stitching operations on the first gain signal and the second gain signal based on the waveform stitching algorithm integrated on the FPGA chip, in another preferred embodiment, the execution of the waveform stitching algorithm is specifically described: Based on the signal trigger time and the gain switching delay, determine the effective overlapping time period between the two signals, so as to align the waveforms of the first gain signal and the second gain signal. Use to represent the signal sampling points in the effective overlapping time period, denote the first gain signal output by the high-gain channel as , and denote the second gain signal output by the low-gain channel as ; Since the amplification multiples of different channels are different, direct superposition will cause amplitude imbalance. Therefore, to ensure that the true amplitude characteristics of the signals are retained within the overlapping time period, the first gain signal and the second gain signal are respectively normalized: ; Among them, is the gain coefficient of the low-gain channel circuit, is the gain coefficient of the high gain channel circuit; In the effective overlapping time period, the weighted superposition method is used to generate the fusion signal , which is expressed as follows: ; in, is the weighting coefficient of the second gain signal.

[0038] In the above algorithm, the contribution ratio of high / low gain channels is automatically adjusted according to the signal strength, saturation is suppressed in the strong signal area, and sensitivity is enhanced in the weak signal area. The two gain signals are dynamically fused in a weighted manner, achieving seamless splicing of UHF partial discharge signals from weak to strong pulses, avoiding waveform mutations or information loss caused by gain switching.

[0039] Obtaining the first gain signal Spectrum information and the second gain signal Spectrum information , determining a weighting coefficient of the second gain signal based on the spectrum information :

[0040] in, is the spectrum-related adjustment factor, is the spectrum correlation index, is the index frequency of the spectrum, It is an S-shaped function used to measure the spectral matching degree between the first gain signal and the second gain signal, and output a weight adjustment factor in the range of [0,1].

[0041] in is the basic weight, which is determined as follows: ; in: Represents the signal strength of the current sampling point; represents the weak signal threshold, represents the strong signal threshold, represents that a higher weight is given to the second gain signal when the signal strength during the effective overlap period is lower than the weak signal threshold; 0 represents that the second gain signal is not used when the signal strength during the effective overlap period is higher than the strong signal threshold; It represents the realization of smooth weighted switching in the signal transition area to prevent splicing mutations. And, is the empirical coefficient, which can be taken as 0.2; Controls the decay rate of the signal transition.

[0042] The above waveform splicing method fundamentally solves the technical contradiction that a single gain channel cannot balance strong and weak signals. It not only retains the original waveform characteristics of strong signals but also effectively amplifies the detailed information of weak signals. By accurately positioning the effective overlapping time period between high and low gain signals and using dynamic weights based on signal strength to fuse the two signals at each sampling point during this period, the adaptability and continuity of signal processing are achieved. The weight assignment follows the principle of signal strength adaptability: when the signal strength is lower than the preset weak signal threshold, a higher weight is given to the high gain signal to highlight the weak components; when the signal strength exceeds the strong signal threshold, the low gain signal is completely adopted to avoid distortion; in the transition interval between the two, natural transition is achieved through smooth interpolation to eliminate splicing mutations.

[0043] It should be noted that although the high gain channel has a higher amplification factor, it is only used to enhance the information expression ability of the weaker part of the signal and does not dominate the final output. During the subsequent waveform splicing process, the algorithm will automatically select the complete signal from the low gain channel as the dominant component according to the signal strength, and switch to the high gain channel for supplementation in the area with a lower signal amplitude. Therefore, even if the initial signal contains strong occasional pulses and low amplitude discharge signals, the high gain channel only amplifies its relatively weak part, without affecting the upper limit of the dynamic range of the overall output, thus effectively avoiding the overflow or saturation problem caused by the large amplification of strong signals. This design enables the system to simultaneously achieve distortion-free recording of strong signals and high-sensitivity capture of weak signals in a single acquisition, significantly superior to the dynamic response performance of traditional single-channel automatic gain control mechanisms in occasional strong pulse scenarios.

[0044] To further determine the weak signal threshold and strong signal threshold in practical application scenarios, in a further preferred embodiment, the following method is used to determine the weak signal threshold and the strong signal threshold as follows: ; where represents the minimum signal amplitude in the current window, represents the average signal strength of the current window, represents the low-frequency band energy (such as 300 MHz - 800 MHz), represents the total band energy; is the weighting coefficient, controlling the influence of historical information and spectral characteristics, represents a small constant.

[0045] ; where represents the maximum signal amplitude in the current window, represents the average signal strength of the current window, represents the estimated signal-to-noise ratio (SNR) of the current frame, represents the SNR impact factor, represents a small constant to prevent the logarithm from being zero, represents the weighting coefficient used to balance the relationship between the peak value and the average value.

[0046] Among them, the weak signal threshold comprehensively considers features such as the minimum value, mean value, and low-frequency energy ratio of the signal, and uses the energy concentration characteristic of the partial discharge signal in a specific frequency band to distinguish the effective signal from the noise. The strong signal threshold introduces the logarithmic calculation of the SNR, enabling the threshold to be automatically adjusted according to the noise level: reducing the threshold at high SNR to retain more signal details, and increasing the threshold at low SNR to avoid noise interference. This threshold calculation based on multi-dimensional signal features enables the dual-channel processing architecture in this embodiment to have strong environmental adaptability.

[0047] It should be understood that the embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

Claims

1. A dual-channel parallel processing architecture for ultra-high frequency partial discharge signals, characterized in that, Comprising: A signal cloning circuit, configured to receive a UHF partial discharge signal, and after losslessly replicating the UHF partial discharge signal, synchronously output it as a first target signal and a second target signal; A low-gain channel circuit, configured to perform buffered transmission on the first target signal while maintaining the original bandwidth and dynamic range, and output it as a first gain signal; A high-gain channel circuit, configured to perform gain amplification on the second target signal, and output it as a second gain signal; A digital signal processing unit, configured to perform synchronous clock control on the low-gain channel circuit and the high-gain channel circuit; An FPGA chip, integrated in the digital signal processing unit, configured to perform fusion splicing processing on the first gain signal and the second gain signal based on a waveform fusion splicing algorithm, and generate a fusion signal.

2. The dual-channel parallel processing architecture according to claim 1, wherein The signal cloning circuit includes a power divider, a first matching resistor, a second matching resistor, a first delay element group, a second delay element group, and a phase compensation network; The input end of the power divider is configured to receive the UHF partial discharge signal, and the power divider is configured to replicate the UHF partial discharge signal, and synchronously output the replicated UHF partial discharge signal through a first output end and a second output end; and The first end of the first matching resistor is electrically connected to the first output end of the power divider, the second end of the first matching resistor is electrically connected to the first end of the first delay element group through the first end of the first delay element group, and the second end of the first delay element group is electrically connected to the first end of the phase compensation network; The first end of the second matching resistor is electrically connected to the second output end of the power divider, the second end of the second matching resistor is electrically connected to the first end of the second delay element group, and the second end of the second delay element group is electrically connected to the second end of the phase compensation network; The phase compensation network is configured to perform synchronous phase compensation on the UHF partial discharge signals output from the first output end and the second output end of the power divider.

3. The dual-channel parallel processing architecture according to claim 2, wherein The phase compensation network includes a phase-shifting inductor, a first matching capacitor, and a second matching capacitor; The first end of the phase-shifting inductor is electrically connected to the first end of the first matching capacitor, the second end of the phase-shifting inductor is electrically connected to the second end of the second matching capacitor, and the second end of the first matching capacitor is electrically connected to the first end of the second matching capacitor; The first end of the phase-shifting inductor serves as the first end of the phase compensation network, and is configured to extract the first target signal; The second end of the phase-shifting inductor serves as the second end of the phase compensation network, and is configured to extract the second target signal.

4. The dual-channel parallel processing architecture according to claim 1, wherein The low-gain channel circuit includes a duplexer, a selection switch, and a first programmable gain amplifier; The duplexer is configured to perform frequency isolation on the first target signal to maintain the original bandwidth and dynamic range of the first target signal. Its input end is configured to receive the first target signal, its first output end is configured to output a first isolation signal, and its second output end is configured to output a second isolation signal; The first input end of the selection switch is configured to receive the second isolation signal, its second input end is configured to receive a reference ground signal, and its output end is configured to output the second isolation signal or the reference ground signal; The first input terminal of the first programmable gain amplifier is used to receive the first isolation signal or the reference ground signal, its second input terminal is used to receive the second isolation signal, and its output terminal is used to output the first gain signal.

5. The dual-channel parallel processing architecture according to claim 1, wherein The high-gain channel circuit includes a filter network, a differential amplifier, a band-pass filter, a radio frequency switch, and a second programmable gain amplifier; The first terminal of the filter network is used to receive the second target signal, and its second terminal is used to output an initial filtered signal; The input terminal of the differential amplifier is used to receive the initial filtered signal, its first output terminal is used to output a positive-phase amplified signal, and its second output terminal is used to output a negative-phase amplified signal; The first input terminal of the radio frequency switch is used to receive the positive-phase amplified signal, its second input terminal is used to receive the negative-phase amplified signal, and its output terminal is used to selectively output the positive-phase amplified signal or the negative-phase amplified signal; The input terminal of the band-pass filter is used to communicate with the output terminal of the radio frequency switch, and the output terminal of the band-pass filter is used to output a band-pass filtered signal corresponding to the positive-phase amplified signal or the negative-phase amplified signal; The first input terminal of the second programmable gain amplifier is used to receive the band-pass filtered signal, and its output terminal is used to output the second gain signal.

6. The dual-channel parallel processing architecture according to claim 5, wherein The filter network includes a first filter capacitor, a filter inductor, and a second filter capacitor; The first terminal of the first filter capacitor is electrically connected to the first terminal of the second filter capacitor, and the second terminal of the first filter capacitor is electrically connected to the first terminal of the filter inductor; The second terminal of the filter inductor is electrically connected to the second terminal of the second filter capacitor; The first terminal of the second filter capacitor serves as the first terminal of the filter network, and the second terminal of the second filter capacitor serves as the second terminal of the filter network.

7. The dual-channel parallel processing architecture according to claim 1, wherein The digital signal processing unit further includes a clock processing unit circuit and at least two independent ADC acquisition unit circuits; The clock processing unit is used to perform synchronous clock control on the low-gain channel circuit and the high-gain channel circuit, and is used to drive the at least two independent ADC acquisition unit circuits to synchronously acquire and process the first gain signal and the second gain signal, and then transmit them to the FPGA chip.

8. The dual-channel parallel processing architecture according to any one of claims 1 to 7, characterized in that, Performing fusion splicing processing on the first gain signal and the second gain signal based on the waveform fusion splicing algorithm, and generating a fusion signal, includes: Determine the first gain signal and the second gain signal for an effective overlapping time period, where represents the signal sampling points in the effective overlapping time period; Normalizing the first gain signal and the second gain signal respectively: ； Among them, is the gain coefficient of the low-gain channel circuit, is the gain coefficient of the high-gain channel circuit; Generate a fusion signal using the weighted superposition method : ; Among them, is the weighting coefficient of the second gain signal.

9. The dual-channel parallel processing architecture according to claim 8, wherein Further includes: Obtain the first gain signal spectrum information and the second gain signal spectrum information , determine the weighting coefficient of the second gain signal based on the spectrum information : ； Among them, is the spectrum correlation term adjustment factor, is the spectrum correlation index, is the index frequency of the spectrum, and outputs a weight adjustment factor within the range of [0, 1]; is the base weight of the second gain signal; is the real-time signal-to-noise ratio of the second gain signal; is the real-time signal-to-noise ratio of the first gain signal.

10. The dual-channel parallel processing architecture according to claim 9, wherein It also includes determining the base weight of the second gain signal : ； Wherein: represents the signal strength of the second gain signal at the current signal sampling point; represents the weak signal threshold, represents the strong signal threshold, is an empirical coefficient, is the signal attenuation rate.

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