88 results about "Transistor switch" patented technology

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

The invention relates to a trigger unit. The trigger unit comprises a first comparison feedback circuit, a first clock gating circuit, a master latch and a slave latch assembly, the first comparison feedback circuit is used for detecting a signal hopping state of an external input signal according to a first output signal output by the output end of the main latch, and generating a corresponding first state feedback signal, so that the first clock gating circuit generates a corresponding first gating clock signal according to the first state feedback signal and a reference clock signal, and sends the first gating clock signal to the second clock gating circuit; under the condition that the first gating clock signal is valid, the main latch is controlled to update the first output signal according to the external input signal; the state switching opportunity of the main latch can be accurately controlled, and unnecessary clock flipping in the trigger and transistor switching activity caused by the unnecessary clock flipping are effectively reduced, so that dynamic power consumption related to a clock network and dynamic power consumption generated by flipping of nodes in a data path are effectively reduced.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.

This disclosure relates to systems and methods for power management in memory design. One device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wake-up detector. The first and second virtual power lines are coupled to a power source via a first set of transistor switches and a second set of transistor switches. The first delay circuit is coupled between the gate terminals of the first and second sets of transistor switches. The first wake-up detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.

The utility model discloses a dust detector through control luminous time to control luminous quantity, including setting in the detection area's luminous element, light receiving element and be used for to the light current signal of light receiving element in producing amplification amplifier circuit, control and detect light emission and light receiving signal's singlechip, the drive circuit of luminous element adopts transistor switch circuit to control luminous time, the drive circuit includes transistor and current -limiting resistance, luminous element, transistor and current -limiting resistance series connection with power supply and form the electric loop, the transistor trigger control end is controlledly connected in the singlechip, the utility model discloses dust sensor through control luminous time realizes to luminous element luminous quantity control, through the luminous quantity of luminous element accurate control, can improve dust sensor measurement result's accuracy and reliability.

An electromagnetic brake control circuit is applied to an electromagnetic brake and a motor. The electromagnetic brake comprises an electromagnet; the electromagnetic brake control circuit comprises a microcontroller, a first transistor switch and a first diode. The microcontroller is configured to transmit a pulse width modulation signal to the first transistor switch to turn on or turn off the first transistor switch. When the electromagnetic brake control circuit is in a follow current stage of a driving mode, the first transistor switch is configured to be cut off by the pulse width modulation signal transmitted by the microcontroller, so that a coil driving current sequentially flows through the electromagnet and the first diode and then returns to the electromagnet; the electromagnetic brake control circuit is configured to drive the electromagnetic brake so that the electromagnetic brake stops braking the motor.

The invention discloses a display panel and a display device, the display panel comprises a substrate, a plurality of pixel driving circuits (Pi) and a control circuit (K), orthographic projections of the plurality of pixel driving circuits (Pi) on the substrate are distributed in an array along a first direction (X) and a second direction (Y), and the first direction (X) and the second direction (Y) intersect; wherein the pixel driving circuit (Pi) comprises a driving transistor (T3) and a switching transistor (Tx), and a first electrode of the switching transistor (Tx) is connected with a grid electrode of the driving transistor (T3); the control circuit (K) and at least one pixel driving circuit (Pi) are correspondingly arranged, the control circuit (K) is connected with the grid electrode of the switching transistor (Tx) in the corresponding pixel driving circuit (Pi), and the control circuit (K) is used for controlling the switching-on and switching-off of the switching transistor (Tx) connected with the control circuit (K). The display panel can realize adjustment of the refreshing frequency of the local area of the display panel.

The invention provides a relay driving circuit and a control method thereof, the relay driving circuit comprises a filtering module, a relay module, a transistor switch module and a PFC control module, the relay module comprises a coil and an armature switch, the transistor switch module comprises a switch transistor and a second diode DF2, and the PFC control module comprises a PFC control module. The input end of the first diode DF2 is connected to the input end of the coil, the input end of the second diode DF2 is connected to the output end of the coil, the output end of the second diode DF2 is connected to the input end of the coil, the drain electrode of the switch transistor is connected to the output end of the coil, and the PFC control module comprises a load current detection unit and a transistor control unit. The output end of the load current detection unit is connected to the input end of the transistor control unit, and the output end of the transistor control unit is connected to the grid electrode of the switching transistor, so that unnecessary electric energy loss when the circuit is in a no-load state can be effectively reduced, and meanwhile, the safety and reliability of the circuit are improved.

According to the display substrate and the display device, the display substrate comprises a plurality of sub-pixels, at least one sub-pixel comprises a switching transistor, the switching transistor comprises an active pattern, a gate electrode, a first electrode and a second electrode, the gate electrode of the switching transistor comprises a gate main body part and a gate connecting part which are arranged in the first direction and connected with each other, at least part of the gate connecting part extends in the first direction, the length of the gate body part in the second direction is larger than that of the gate connecting part in the second direction, and the orthographic projection of the active pattern of the at least one switching transistor on the substrate is at least partially overlapped with the orthographic projection of the gate body part on the substrate. And the orthographic projection of the data signal line connected with at least one switch transistor on the substrate is at least partially overlapped with the orthographic projection of the gate connection part on the substrate.

The invention provides an array substrate, a preparation method thereof and a display panel, the array substrate comprises a substrate and a driving layer located on the substrate, and the driving layer comprises a switching thin film transistor and a driving thin film transistor; the switching thin film transistor comprises a first active layer, a first gate insulating layer and a first gate; the driving thin film transistor comprises a second active layer, a second gate insulating layer and a second gate; the first grid insulating layer covers the first active layer, the second grid insulating layer covers the second active layer, the first grid is located on the side, away from the substrate, of the first grid insulating layer, the second grid is located on the side, away from the substrate, of the second grid insulating layer, and the orthographic projection of the first grid on the substrate is overlapped with the orthographic projection of the first active layer on the substrate; the orthographic projection of the second grid electrode on the substrate is overlapped with the orthographic projection of the second active layer on the substrate, and the thickness of the first active layer is smaller than that of the second active layer; the problems of non-uniform gray scale expansion and non-uniform low-gray-scale brightness are effectively solved, and the display effect is improved.

Disclosed in the present invention are an LDO circuit and method for mitigating output overshoot. The LDO circuit comprises a comparator. A first amplifier is connected to a low static power consumption circuit by means of a first NMOS transistor; a first voltage-dividing sampling resistor and a second voltage-dividing sampling resistor are connected to the low static power consumption circuit and generate a feedback voltage; the comparator is connected to the low static power consumption circuit by means of a fourth PMOS transistor, and compares a second reference voltage and a driving voltage that are generated inside a circuit, to control the turning-on and turning-off of a fourth PMOS transistor switch controller; on the basis of a first reference voltage and the feedback voltage, the first amplifier outputs a first voltage signal, and outputs the driving voltage by means of the first NMOS transistor and the low static power consumption circuit; on the basis of an external input voltage and the driving voltage, a second PMOS transistor generates and controls an output voltage; and the driving voltage is modulated by means of a comparator circuit to control a power transistor, so as to mitigate output voltage overshoot during slow start-up under no-load conditions and output voltage overshoot during no-load hot-swapping.

A display panel includes a pixel including a pixel circuit and a light-emitting diode, a data line providing a data signal to the pixel, a gate line providing a gate signal to the pixel, and a power line providing a power signal to the pixel. The pixel circuit includes a driving transistor, a switching transistor, a compensation transistor, and a sub-compensation transistor. The sub-compensation transistor is connected between the power line and a second capacitor or connected between the second capacitor and the driving transistor.

This invention relates to the field of LED lighting driver technology, and discloses a dual-voltage adaptive LED load topology adjustment circuit, comprising: an input rectification module, a load branch module, a topology control module, and a linear constant current adjustment module; the topology control module uses a voltage regulator detection branch to monitor the rectified voltage amplitude, generates a control level based on the internal semiconductor breakdown characteristics, and drives a transistor switching array to reconstruct the connection path between load branches; when the rectified voltage is in the first range, the parallel circuit is connected, and when the voltage reaches a threshold, it switches to the series circuit, and the linear constant current adjustment module regulates the current of the light-emitting device; this invention achieves spontaneous reconstruction of the load topology through hardware physical response, reduces redundant voltage drop and power loss in the driver circuit, and maintains the consistency of luminous brightness under different input voltages.

The present disclosure relates to the technical field of wireless charging, and provides a modulation method and apparatus for a wireless charging system, and a wireless charging system. The method comprises: in response to the startup of a wireless charging system, controlling the operation of a rectifying circuit on the basis of a pre-configured rectification logic, so as to rectify the energy obtained by coil coupling at a receiving end; monitoring an operating state of a lower MOS transistor during the operation of the rectifying circuit; and if it is monitored that the operating state of the lower MOS transistor switches from an on state to an off state, controlling the lower MOS transistor to turn off with a delay on the basis of a pre-configured turn-off delay parameter. The modulation method and apparatus for a wireless charging system, and the wireless charging system provided by the present disclosure allow the lower MOS transistor to turn off with a delay on the basis of the pre-configured turn-off delay parameter, so as to achieve communication modulation at the receiving end; and in addition, the entire modulation process does not require additional material costs, and the flexibility of modulation depth adjustment is improved, thereby meeting diverse application requirements.

The application discloses a display panel and a display device. The display panel comprises a plurality of pixel circuits and a virtual circuit located at a pixel circuit gap. The pixel circuit comprises at least one switching transistor. The virtual circuit comprises at least one virtual transistor. The switching transistor comprises a first gate and a first active layer. The virtual transistor comprises a second gate. The display panel further comprises a substrate, a semiconductor layer and a first metal layer which are located on one side of the substrate and are insulatively and spacedly arranged. The semiconductor layer comprises a plurality of semiconductor structures, at least part of the semiconductor structures being the first active layer. The first metal layer comprises the first gate and the second gate. In a direction perpendicular to a plane where the substrate is located, an overlapping area of the first gate and the first active layer is S1, the second gate does not overlap with the semiconductor structure, or an overlapping area of the second gate and the semiconductor structure is S2, wherein S2 < S1. The application can improve the display resolution or the light transmittance of the display panel.

The present disclosure provides a variable frequency drive with active power factor correction circuit topology to facilitate unity power factor and non-positive DC bias on the output voltage. The topology is an improvement over the traditional boost power factor correction circuit consisting of a bridge rectifier, a plurality of inductors, a plurality of power semiconductor transistor switches, a plurality of boost diodes, a bus capacitor bank and a controller. In certain embodiments, the active power factor correction circuit feeds an inverter circuit that drives a motor.

The utility model discloses an automatic testing device based on image recognition, which comprises a main control chip, a control and interaction module and an image acquisition module, and the image acquisition module adopts an OV2640 camera module; the main control chip adopts ESP32-WROOM-32D, the OV2640 camera module is connected with the ESP32 through a DVP interface, a data line of the OV2640 camera module is connected to a GPIO of the ESP32, and camera parameters are configured through an IC bus interface; the power supply circuit adopts an AMS1117-3. 3V voltage stabilizing chip and provides a working power supply for the ESP32 and external equipment; the output end of the voltage stabilizing chip is connected with the power supply module U1 and the power supply module U3 through the transistor switch Q2, the power supply module U1 and the power supply module U3 respectively output 2.8 V and 1.2 V direct current power supplies to provide 2.8 V and 1.2 V working power supplies for the camera module, and the transistor switch Q2 is in controlled connection with the ESP32.

The application relates to the technical field of electronic power control, in particular to a high-voltage solid-state direct-current circuit breaker, which comprises a main switch, a metal-oxide-semiconductor field-effect transistor and a switch control circuit. When a power supply is connected to the input terminal of the drain of the metal-oxide-semiconductor field-effect transistor, the drain has a voltage, the power taking circuit can take power from the drain to output a driving control signal, and the driving circuit drives the metal-oxide-semiconductor field-effect transistor to be in a conduction state, so that the high-voltage solid-state direct-current circuit breaker is self-started. Since the metal-oxide-semiconductor field-effect transistor is a normally-off device, the main switch is in a conduction state, and the switch control circuit can control the conduction state of the metal-oxide-semiconductor field-effect transistor by using the power taking circuit and the driving circuit, so that the high-voltage solid-state direct-current circuit breaker can be self-started, and the volume and manufacturing cost of the high-voltage solid-state direct-current circuit breaker are reduced.

The application provides a PG protection circuit and a control method thereof. The PG protection circuit comprises a protection switch protection unit for detecting the size of a first main power supply AC1 and providing protection for a transistor switch in a later stage, a light coupling gate unit for connecting a second main power supply VDD to a light emitting diode of a light coupling when the transistor switch is turned on after the first main power supply AC1 is detected, an isolation amplification unit for isolating and amplifying the current generated by a voltage dividing resistor and then outputting a to-be-detected voltage signal of the second main power supply VDD when the light coupling gate unit is in a turn-on state, and a PG signal sending unit for outputting a high-level signal according to the size of a delay capacitor after the to-be-detected voltage signal is detected. The reliability of the PG signal control can be effectively improved, and the safety of the system is ensured.

This application relates to voltage regulators. An apparatus includes a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL includes a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits include a second plurality of capacitors. The FC circuits in the plurality of FC circuits are coupled to each other and to a rail between the input and the output terminals. Each FC circuit in the plurality of FC circuits includes at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

This application relates to the field of integrated circuit technology and discloses a writing circuit and method for configurable SRAM within an FPGA. It improves the write reliability of SRAM with a relatively low increase in design cost. The method includes: a configuration control module connected to a data controller; the data controller connected to a configuration memory cell array via multiple pairs of bit lines and negative bit lines, with each pair of bit lines and negative bit lines connected to a column of memory cells in the configuration memory cell array; the data controller connected to a buffer module via multiple pairs of bit lines and negative bit lines, a write enable signal line, and a data pull-down enable signal line, and connected to a pull-down control module via multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to turn on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turn off the N-type drive transistor switch of the other bit line or negative bit line; the configuration control module is connected to each of multiple address decoders via address enable signal lines.

The application provides a display substrate, a manufacturing method thereof and a display device, and belongs to the technical field of display. The display substrate comprises a pixel circuit on a substrate, the pixel circuit comprising a driving thin film transistor, a switching thin film transistor and a gate drive circuit thin film transistor, the active layer of the driving thin film transistor and the active layer of the switching thin film transistor being located on different layers; and / or, the active layer of the driving thin film transistor and the active layer of the gate drive circuit thin film transistor being located on different layers. The technical scheme of the application can improve the display effect of the display device.

The present disclosure provides a power converter and control circuit and control method thereof. A reference pulse signal is generated by modulating switching frequency information and / or current reference information on a secondary side of the power converter. The pulse signal is transmitted to a primary side through a digital isolator, so that a primary-side control signal could be obtained by demodulating the reference pulse signal on the primary side, and control of a switching state of a power transistor on the primary side is achieved. Wherein, the present disclosure uses special modulation and demodulation settings to transmit several information between the secondary side and primary side through a single channel, the number of isolation devices used between the primary side and secondary side is reduced, system structure is simplified, and system costs are reduced.

The application provides an assembled light emitting diode display device, which comprises a system motherboard and a plurality of assembled sub-boards. The assembled sub-boards are arranged on the system motherboard, each of the assembled sub-boards has a substrate, at least two groups of light emitting diode units arranged on the substrate, and at least one transistor switch. Each group of light emitting diode units has a plurality of light emitting diodes and is electrically connected with the same transistor switch. The light emitting diodes are arranged in rows and columns on the system motherboard. The light emitting diodes arranged in the same row in a first direction are electrically connected with a corresponding power line. The gate of at least one transistor switch of the same assembled sub-board is electrically connected with the same gate line. A large number of light emitting diodes can be simultaneously transferred by using the assembled sub-boards, so as to reduce the problem of mass transfer.

A system for connecting batteries in a circuit, placing no less than two batteries in a series-parallel switching circuit, where a group of batteries are connected in parallel and series in two separate stages using fast switching devices, where average voltage is output to a load based on duty cycle. Renewable energy power sources such as solar panels can be connected in parallel with the batteries in the first stage and the same batteries are connected in series with the load in the second stage using transistor switches, first enabling the batteries to charge and discharge simultaneously, secondly enabling the solar panels to divert voltage, which as an additional battery in series provides the required voltage for the load, and adjusting the duty cycle of charging and discharging by converting the voltage waveform.

Disclosed is a display device which includes pixel drivers, each of which includes a first transistor switched by a voltage of a node and electrically connected between a second electrode and a second power supply line, a second transistor electrically connected between the node and a data line and switched by a write scan signal, and a capacitor including a first capacitor electrode electrically connected to the node and a second capacitor electrode electrically connected between the second power supply line and the first transistor. First electrodes of light emitting elements overlap each of the first capacitor electrodes of the pixel drivers.

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a display area and a frame area located at the periphery of the display area, the display area comprises a plurality of sub-pixels and a plurality of data lines connected with the sub-pixels, the frame area comprises a test area and a binding area; the test area comprises a plurality of test units arranged periodically along a first direction, the test unit comprises at least one switching transistor, the first electrode of the switching transistor is connected with a test signal lead, and the second electrode is connected with a data line; the binding area comprises a plurality of binding units arranged periodically along the first direction, the binding unit comprises at least one binding pad, and the binding pad is connected with the data line; wherein, in the first direction, the ratio between the number of switching transistors contained in one arrangement period of the test unit and the number of binding pads contained in one arrangement period of the binding unit is greater than 0 and less than 2.

Methods and devices to improve the switching speed of radio frequency FET switch stacks are disclosed. The described methods and devices are based on bypassing drain-sources resistors when the FET switch stack is transitioning from an ON to an OFF state. Several implementations of the disclosed teachings are also presented.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.