33 results about "Transistor switch" patented technology

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.

The utility model discloses a dust detector through control luminous time to control luminous quantity, including setting in the detection area's luminous element, light receiving element and be used for to the light current signal of light receiving element in producing amplification amplifier circuit, control and detect light emission and light receiving signal's singlechip, the drive circuit of luminous element adopts transistor switch circuit to control luminous time, the drive circuit includes transistor and current -limiting resistance, luminous element, transistor and current -limiting resistance series connection with power supply and form the electric loop, the transistor trigger control end is controlledly connected in the singlechip, the utility model discloses dust sensor through control luminous time realizes to luminous element luminous quantity control, through the luminous quantity of luminous element accurate control, can improve dust sensor measurement result's accuracy and reliability.

Disclosed in the present invention are an LDO circuit and method for mitigating output overshoot. The LDO circuit comprises a comparator. A first amplifier is connected to a low static power consumption circuit by means of a first NMOS transistor; a first voltage-dividing sampling resistor and a second voltage-dividing sampling resistor are connected to the low static power consumption circuit and generate a feedback voltage; the comparator is connected to the low static power consumption circuit by means of a fourth PMOS transistor, and compares a second reference voltage and a driving voltage that are generated inside a circuit, to control the turning-on and turning-off of a fourth PMOS transistor switch controller; on the basis of a first reference voltage and the feedback voltage, the first amplifier outputs a first voltage signal, and outputs the driving voltage by means of the first NMOS transistor and the low static power consumption circuit; on the basis of an external input voltage and the driving voltage, a second PMOS transistor generates and controls an output voltage; and the driving voltage is modulated by means of a comparator circuit to control a power transistor, so as to mitigate output voltage overshoot during slow start-up under no-load conditions and output voltage overshoot during no-load hot-swapping.

This invention relates to the field of LED lighting driver technology, and discloses a dual-voltage adaptive LED load topology adjustment circuit, comprising: an input rectification module, a load branch module, a topology control module, and a linear constant current adjustment module; the topology control module uses a voltage regulator detection branch to monitor the rectified voltage amplitude, generates a control level based on the internal semiconductor breakdown characteristics, and drives a transistor switching array to reconstruct the connection path between load branches; when the rectified voltage is in the first range, the parallel circuit is connected, and when the voltage reaches a threshold, it switches to the series circuit, and the linear constant current adjustment module regulates the current of the light-emitting device; this invention achieves spontaneous reconstruction of the load topology through hardware physical response, reduces redundant voltage drop and power loss in the driver circuit, and maintains the consistency of luminous brightness under different input voltages.

The present disclosure relates to the technical field of wireless charging, and provides a modulation method and apparatus for a wireless charging system, and a wireless charging system. The method comprises: in response to the startup of a wireless charging system, controlling the operation of a rectifying circuit on the basis of a pre-configured rectification logic, so as to rectify the energy obtained by coil coupling at a receiving end; monitoring an operating state of a lower MOS transistor during the operation of the rectifying circuit; and if it is monitored that the operating state of the lower MOS transistor switches from an on state to an off state, controlling the lower MOS transistor to turn off with a delay on the basis of a pre-configured turn-off delay parameter. The modulation method and apparatus for a wireless charging system, and the wireless charging system provided by the present disclosure allow the lower MOS transistor to turn off with a delay on the basis of the pre-configured turn-off delay parameter, so as to achieve communication modulation at the receiving end; and in addition, the entire modulation process does not require additional material costs, and the flexibility of modulation depth adjustment is improved, thereby meeting diverse application requirements.

The application discloses a display panel and a display device. The display panel comprises a plurality of pixel circuits and a virtual circuit located at a pixel circuit gap. The pixel circuit comprises at least one switching transistor. The virtual circuit comprises at least one virtual transistor. The switching transistor comprises a first gate and a first active layer. The virtual transistor comprises a second gate. The display panel further comprises a substrate, a semiconductor layer and a first metal layer which are located on one side of the substrate and are insulatively and spacedly arranged. The semiconductor layer comprises a plurality of semiconductor structures, at least part of the semiconductor structures being the first active layer. The first metal layer comprises the first gate and the second gate. In a direction perpendicular to a plane where the substrate is located, an overlapping area of the first gate and the first active layer is S1, the second gate does not overlap with the semiconductor structure, or an overlapping area of the second gate and the semiconductor structure is S2, wherein S2 < S1. The application can improve the display resolution or the light transmittance of the display panel.

The present disclosure provides a variable frequency drive with active power factor correction circuit topology to facilitate unity power factor and non-positive DC bias on the output voltage. The topology is an improvement over the traditional boost power factor correction circuit consisting of a bridge rectifier, a plurality of inductors, a plurality of power semiconductor transistor switches, a plurality of boost diodes, a bus capacitor bank and a controller. In certain embodiments, the active power factor correction circuit feeds an inverter circuit that drives a motor.

The application relates to the technical field of electronic power control, in particular to a high-voltage solid-state direct-current circuit breaker, which comprises a main switch, a metal-oxide-semiconductor field-effect transistor and a switch control circuit. When a power supply is connected to the input terminal of the drain of the metal-oxide-semiconductor field-effect transistor, the drain has a voltage, the power taking circuit can take power from the drain to output a driving control signal, and the driving circuit drives the metal-oxide-semiconductor field-effect transistor to be in a conduction state, so that the high-voltage solid-state direct-current circuit breaker is self-started. Since the metal-oxide-semiconductor field-effect transistor is a normally-off device, the main switch is in a conduction state, and the switch control circuit can control the conduction state of the metal-oxide-semiconductor field-effect transistor by using the power taking circuit and the driving circuit, so that the high-voltage solid-state direct-current circuit breaker can be self-started, and the volume and manufacturing cost of the high-voltage solid-state direct-current circuit breaker are reduced.

The application provides a PG protection circuit and a control method thereof. The PG protection circuit comprises a protection switch protection unit for detecting the size of a first main power supply AC1 and providing protection for a transistor switch in a later stage, a light coupling gate unit for connecting a second main power supply VDD to a light emitting diode of a light coupling when the transistor switch is turned on after the first main power supply AC1 is detected, an isolation amplification unit for isolating and amplifying the current generated by a voltage dividing resistor and then outputting a to-be-detected voltage signal of the second main power supply VDD when the light coupling gate unit is in a turn-on state, and a PG signal sending unit for outputting a high-level signal according to the size of a delay capacitor after the to-be-detected voltage signal is detected. The reliability of the PG signal control can be effectively improved, and the safety of the system is ensured.

This application relates to voltage regulators. An apparatus includes a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL includes a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits include a second plurality of capacitors. The FC circuits in the plurality of FC circuits are coupled to each other and to a rail between the input and the output terminals. Each FC circuit in the plurality of FC circuits includes at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

This application relates to the field of integrated circuit technology and discloses a writing circuit and method for configurable SRAM within an FPGA. It improves the write reliability of SRAM with a relatively low increase in design cost. The method includes: a configuration control module connected to a data controller; the data controller connected to a configuration memory cell array via multiple pairs of bit lines and negative bit lines, with each pair of bit lines and negative bit lines connected to a column of memory cells in the configuration memory cell array; the data controller connected to a buffer module via multiple pairs of bit lines and negative bit lines, a write enable signal line, and a data pull-down enable signal line, and connected to a pull-down control module via multiple pairs of bit lines and negative bit lines and the data pull-down enable signal line. The pull-down control module is used to turn on the N-type drive transistor switch of the bit line or negative bit line corresponding to the pull-down "0" signal, and turn off the N-type drive transistor switch of the other bit line or negative bit line; the configuration control module is connected to each of multiple address decoders via address enable signal lines.

The present disclosure provides a power converter and control circuit and control method thereof. A reference pulse signal is generated by modulating switching frequency information and / or current reference information on a secondary side of the power converter. The pulse signal is transmitted to a primary side through a digital isolator, so that a primary-side control signal could be obtained by demodulating the reference pulse signal on the primary side, and control of a switching state of a power transistor on the primary side is achieved. Wherein, the present disclosure uses special modulation and demodulation settings to transmit several information between the secondary side and primary side through a single channel, the number of isolation devices used between the primary side and secondary side is reduced, system structure is simplified, and system costs are reduced.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.

A spliced transistor switching device comprises a transistor switching assembly, a transistor switching circuit and a microcontroller, and the transistor switching circuit comprises a first transistor switching sub-circuit and a second transistor switching sub-circuit. A second on-resistance value of the second transistor switch sub-circuit is greater than a first on-resistance value of the first transistor switch sub-circuit. When the microcontroller switches on the first transistor switch sub-circuit, the transistor switch assembly is switched on; when the microcontroller switches on the second transistor switch sub-circuit, the transistor switch assembly is switched on. When the microcontroller receives a switching-off signal, the microcontroller is configured to sequentially cut off the first transistor switching sub-circuit and the second transistor switching sub-circuit.

This application belongs to the field of power supply technology and provides a method for adjusting the open-circuit voltage of a power supply, a power supply circuit, a power supply device, and a welding machine. By driving the first power transistor switching module and the second power transistor switching module to conduct alternately, the transformer module operates in a state of extremely low energy density, thereby achieving the purpose of adjusting the open-circuit voltage of the power supply over a wide range. By using frequency hopping technology to reduce the equivalent driving frequency of the upper and lower switching transistors in the dual-transistor forward topology circuit in the power supply, the energy transfer density of the transformer is further reduced. The voltage regulation module controls the equivalent resistance at the output terminal of the power supply, and the auxiliary step-down module provides auxiliary voltage, thereby achieving the purpose of compound adjustment of the open-circuit voltage of the power supply. Finally, the rectification and freewheeling modules rectify and freewheel the voltage signal output by the transformer module. This solves the problem that the open-circuit voltage of existing welding power supplies is mostly not adjustable, or very rarely adjustable but with a small adjustment range, resulting in poor adaptability to welding processes.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits includes a second plurality of capacitors. FC circuits of the plurality of FC circuits are coupled to each other and a rail between the input terminal and the output terminal. An FC circuit of the plurality of FC circuits comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the second plurality of capacitors.

This disclosure relates to a display device and a driving method thereof. The display device includes: a display panel including sub-pixels; and a driver configured to drive the display panel, wherein the sub-pixels include: a sensing transistor configured to transmit a reference voltage applied via a data line to a second electrode of a capacitor during a first time period included in a horizontal time period; and a switching transistor configured to transmit a data voltage applied via the data line to a first electrode of the capacitor during a second time period included in the same horizontal time period.

This invention relates to the field of downhole communication in oil and gas wells, and provides a 2FSK modulation and demodulation circuit for downhole communication. It comprises a 2FSK modulation circuit, a power amplifier, a transmitting transducer, a reciprocal transducer, a receiving transducer, a power supply circuit, and a 2FSK demodulation circuit. The baseband signal is processed by a comparator module, a transistor switching module, a signal conditioning module, and a VCO module in the 2FSK modulation circuit, resulting in a phase-continuous 2FSK modulated signal. This signal is then transmitted downhole via the power amplifier and the transmitting transducer. The reciprocal transducer receives the signal and transmits it to the receiving transducer. The 2FSK demodulation circuit then filters the complete signal acquired by the receiving transducer and demodulates the baseband signal. This invention's modulation and demodulation circuit achieves phase continuity of the modulated signal between adjacent symbols, has a simple circuit structure, and offers advantages such as high signal transmission stability and the ability to achieve long-distance downhole communication in oil and gas wells.

An apparatus includes a voltage regulator (VR). The VR includes a capacitor with a top plate and a bottom plate. The VR includes a first plurality of transistor switches (TSs) and a second plurality of TSs. The first plurality of TSs comprises a corresponding plurality of first switch terminals and a corresponding plurality of second switch terminals. The plurality of second switch terminals of the first plurality of TSs are coupled in parallel with each other and to the top plate. The second plurality of TSs includes a corresponding plurality of first switch terminals and a corresponding plurality of second switch terminals. The plurality of second switch terminals of the second plurality of TSs are coupled in parallel with each other and to the bottom plate.

A system for prognosis and control of a power module includes a gate driver circuit and a controller circuit. The gate driver circuit drives a target gate node of a target power transistor in response to a pulse width modulation signal, measures a target gate voltage, switches a desaturation signal in response to the target power transistor switching between an off state and an on state, measures a target transistor voltage, and measures a target transistor current. The controller circuit modulates the pulse width modulation signal to increase the target gate voltage, determines a target threshold voltage as the target gate voltage in response to the desaturation signal switching states, determines a target on-resistance based on the target transistor voltage and the target transistor current, and controls the target power transistor based on the target threshold voltage and the target on-resistance.

The present invention provides a display device and an electrical terminal including a display panel, a driver electrically connected to driving a display panel to display images, a power manager electrically connected to the driver. A first voltage module (included in the power manager) includes a first transistor and a second transistor. The power manager is configured to at least one of the first transistor and the second transistor to switch on according to a value of a first current of the first voltage module transmitted to the driver control. Also, three conversion efficiencies of the first voltage module respectively in conditions of only the first transistor switching on, only the second transistor switching on, and both the first and second transistors switching on are different to reduce power consumption of the display device.

Embodiments of the present application provide a display device and a driving method thereof. The display device comprises a display panel and a driving chip. The display panel comprises a first display part and a second display part. The first display part is provided with a first data line group, and the second display part is provided with a second data line group. The driving chip is arranged at the edge of the first display part, and is electrically connected with the first data line group and the second data line group. The driving chip is integrated with a display driving circuit and a touch driving circuit. The touch driving circuit provides a touch driving signal to the first display part and the second display part in a time-division multiplexing manner. The display device further comprises a switching transistor. The switching transistor is connected in series with the second data line group, and is used for controlling the conduction and the cut-off of the second data line group. The display device of the present application shares the driving chip by the first display part and the second display part, thereby reducing the manufacturing cost of the foldable display device.

This invention relates to an addressable capacitor test circuit and method, comprising: an addressing circuit, a switching circuit, and a capacitor array under test; the capacitor array under test includes multiple capacitor cells under test; the switching circuit includes a transmission gate connected between the addressing circuit and the capacitor array under test; the addressing circuit receives an address signal and selects the capacitor cell under test corresponding to the address signal through the transmission gate in the switching circuit; during QVCM testing, the switching circuit applies a Clk-I measurement signal to one end of the selected capacitor cell under test, while the remaining unselected capacitor cells under test remain in a 0V bias state. This test circuit uses a transmission gate structure instead of a single-transistor switch, effectively reducing the influence of charge injection, leakage current, and non-ideal conduction characteristics generated during switch on and off on the measurement results, thereby reducing the disturbance of the test circuit to the intrinsic electrical characteristics of the capacitor under test.

This utility model discloses an adjustable current-limiting digital signal output circuit, including an input power supply VCC, a voltage divider network, transistor switches, a filter capacitor, an MCU control module, and an output terminal OUT. The input power supply VCC provides energy to the entire circuit. The transistor switches include transistors Q1, Q2, and Q3. The filter capacitor suppresses noise and stabilizes the voltage. The MCU control module includes a microcontroller enable signal MCU_EN and a power ground GND. The voltage divider network includes a current-limiting resistor, a voltage-dividing resistor, and a pull-up resistor. The current-limiting resistor adjusts the current limit by changing its resistance value, the voltage-dividing resistor adjusts the transistor voltage, and the pull-up resistor ensures the transistor conducts when the microcontroller enable signal MCU_EN is valid. The output terminal OUT is located at the circuit's output port. Thus, short-circuit protection is achieved through a simple transistor and resistor-capacitor circuit. The circuit is simple, reliable, requires few components, is cost-effective, and is less prone to failure.

This application relates to a switched-capacitor voltage converter. An inductor and several switching transistors are added between the two branches of a traditional Dickson-type switched-capacitor converter. By controlling the on and off states of these switching transistors, for a period of time after the main switching transistor is turned off, the charge on the parasitic capacitance of one branch is completely transferred to the other branch through the inductor, making the voltage difference across the main switching transistor zero. Thus, at the instant each main switching transistor is turned on, the voltage difference across each main switching transistor becomes zero, thereby reducing switching losses during transistor switching and improving the conversion efficiency of the Dickson-type switched-capacitor voltage converter.

This invention discloses a hardware-delayed self-destruct circuit system for a high-explosive fragmentation bomb, comprising a power input circuit, a power conversion circuit, a power-down switching circuit, a power-on delay circuit, a power-down delay circuit, an ignition trigger circuit, and an ignition circuit. The power-on delay circuit and the power-down delay circuit both utilize the same frequency divider chip, enabling precise delay-triggered ignition. The advantages of this invention are: the frequency divider delay circuit achieves high reliability, high anti-interference capabilities, a simple circuit structure, and low cost; it ensures reliable detonation of the high-explosive fragmentation bomb within a certain time window, effectively preventing accidental detonation, misfires, and other dangerous accidents; the power input circuit also employs input filtering, reverse connection protection, current backflow prevention, and surge protection circuits; the power-down switching circuit uses an NMOS field-effect transistor switching circuit; and the ignition trigger circuit is implemented using a combination of a silicon controlled rectifier (SCR) and a PMOS transistor.

A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

An arc fault detection method, comprising: acquiring a current signal of a direct-current conversion circuit (S110); performing frequency domain analysis on the current signal to obtain frequency spectrum information of the current signal, the frequency spectrum information comprising amplitudes of a plurality of frequency points (S120); calculating a first characteristic quantity on the basis of the amplitudes of the frequency points in the frequency spectrum information corresponding to the switching frequency of switching transistors (S130); calculating a second characteristic quantity on the basis of the amplitudes of the frequency points in the frequency spectrum information within a preset target frequency band (S140); and determining an arc fault detection result of the direct-current conversion circuit on the basis of the first characteristic quantity and the second characteristic quantity (S150).

A method for controlling an inverter (I) with multiple half-bridges (P1 - P3) involves obtaining a pulse pattern that identifies the target switching times of semiconductor switches (11 - 13, 21 - 23) of the inverter (I). Switching times (ZA, ZB) of different switches (11 - 13, 21 - 23) are determined that are separated by less than the minimum time interval than switching times (ZA, ZB) that occur too close together. This is associated with a disturbance in the control signals of the switches (11 - 13, 21 - 23). The switches (11 - 13, 21 - 23) of the inverter (I) are controlled according to the target switching times and according to the shifted switching times. The shifted switching times (ZA', ZB) result from shifting the switching times that occur too close together. The second switching points (ZA', ZB) are then separated by more than the specified time interval. Furthermore, a corresponding control device and a corresponding vehicle drive are described.

A switching circuit has a first transistor, a second transistor, a third transistor and a driving circuit. Drain terminals of the second and third transistors are coupled to a gate terminal of the first transistor, and source terminals of the second and third transistors are coupled to a source terminal of the first transistor. Based on a pulse width modulation signal, the driving circuit provides a first driving signal to control the first transistor, a first pull down control signal to control the second transistor, and a second pull down control signal to control the third transistor. The second transistor has a larger size and a lower resistance than the third transistor.