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562 results about "High- and low-level" patented technology

High-level and low-level, as technical terms, are used to classify, describe and point to specific goals of a systematic operation; and are applied in a wide range of contexts, such as, for instance, in domains as widely varied as computer science and business administration.

Multiple hierarichal/peer domain file server with domain based, cross domain cooperative fault handling mechanisms

A shared system resoure such as a file server includes an integrated, cooperative cluster of domains that include hierarchically related domains and peer related domains, each performing functions supporting the services provided by the system resource. Hierarchically related domains include a higher level domain and a lower level domain respectively performing higher and lower level operations of functions supporting the system resource services and peer related domains include parallel domains performing operations in mutual support of functions supporting the system resource services. A domain may include fault handling mechanisms operating independently of and cooperatively with fault handling mechanisms of other domains, and domain may be comprised of domains. In hierarchically related domains, the lower level domain includes peer related domains performing operations in mutual support of functions of the upper level domain and peer domain includes a monitoring mechanism monitoring operations of the other peer domain that are related to the operations performed in support of the upper level domain. Each monitoring mechanism is responsive to detection of a failure in the other peer domain for directing the peer domain in which the monitoring mechanism resides in assuming the operations performed by the peer domain in support of related functions of the upper level domain independently of operations of the peer domain and independently of a source of the failure in the other peer domain.
Owner:EMC IP HLDG CO LLC

Braking energy recovery system for electric vehicle

The invention relates to a braking energy recovery system for an electric vehicle, comprising a three-phase staggered two-way half-bridge circuit, a gear selection circuit, a sampling hold circuit, a digital chip, a voltage sampling circuit, a current sampling circuit and a driving circuit which are sequentially connected. Two-way half-bridge DC/DC converters are connected in parallel, the three-phase staggered two-way half-bridge circuit serves as a main circuit topology of the system, high and low levels are output through an I/O port to control the switching-on/off of relays so as to select different power requirement gears, and finally, the purpose of recovering the braking energy of motors with different output power is realized. According to the invention, the reliability of the device is improved, current ripples are reduced, and the volume of inductors and the capacity of capacitors are reduced, so that the device is easier to realize; the system can be used for multiple DC motors with different output power requirements; the system can effectively prevent current from being out of control under fault conditions so as to quickly finish overcurrent protection; and in addition, a three-phase staggered DC/DC converter system and an active inverter system are consistent in structure, thereby being favorable for realizing a modular structure of an electric vehicle system.
Owner:CHONGQING UNIV OF POSTS & TELECOMM

Determinant linear array coordinate scanning circuit

The invention discloses a determinant linear array coordinate scanning circuit, comprising an m-channel pulse distribution circuit, a key press event judging circuit, a determinant signal filter shaping and coordinate latch signal generating circuit, a determinant coordinate coding circuit and a determinant coordinate value storage circuit. The m-channel pulse distribution circuit sequentially outputs low level at a line port of an m*n matrix key press circuit, a key press event indicating circuit judges the occurrence of the key press event according to the high and low level at a row port, the determinant coordinate coding circuit 4 codes the line port and the row port to the determinant coordinate according to the current state value, after the key press event indicating signal is generated, the output result of the current determinant coordinate coding circuit is latched in the coordinate value storage circuit by using the latch signal generated by the determinant signal filter shaping and coordinate latch signal generating circuit, and the determinant coordinate value of the coordinate value storage circuit is the coordinate of the key currently pressed. The determinant linear array coordinate scanning circuit has the advantages of concise design, convenient implementation, low hardware cost and no loss of generality.
Owner:UNIV OF ELECTRONICS SCI & TECH OF CHINA ZHONGSHAN INST
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