Shift register unit, grid driving circuit and display device
A shift register and gate technology, applied in the fields of gate drive circuits, display devices, and shift register units, can solve problems such as high power consumption, and achieve the effect of solving large power loss losses
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Embodiment 1
[0024] Such as figure 2 As shown, it is a schematic structural diagram of the shift register unit in Embodiment 1 of the present invention. The shift register unit includes: a pull-up control module 201, a pull-up module 202, a pull-down control module 203, and a pull-down module 204, wherein:
[0025] The pull-up control module 201, whose input terminal is connected to the transmission signal input terminal, and whose output terminal is connected to the pull-up node, is used to output the pull-up control signal to the pull-up node PU according to the transmission signal input by the transmission signal input terminal. The pull node PU is located on the wire used to connect the pull-up control module and the pull-up module;
[0026] The pull-up module 202, whose input terminal is connected to the pull-up node, and whose output terminal is connected to the gate drive signal output terminal and the transmission signal output terminal, is used to input the first clock signal inp...
Embodiment 2
[0041] Such as image 3 Shown is a schematic circuit diagram of the shift register unit in Embodiment 2 of the present invention. in:
[0042] The signals input to the shift register unit include: the first clock signal CLK, the second clock signal CLKB, the transfer signal InPut, the reset signal Reset, the first DC power supply voltage VDD (always a high level signal) and the second DC power supply Voltage signal VSS (always a low-level signal); the signals output from the shift register unit include: transfer signal Output1 and gate drive signal Output2;
[0043] In addition, the pull-up module 202 is formed by the capacitor C, the sixth transistor M6, and the third transistor M3;
[0044] The first pull-down sub-module in the first mode in Embodiment 1 is formed by the second transistor M2 and the eighth transistor M8;
[0045] The second pull-down sub-module in the first mode in Embodiment 1 is formed by the eleventh transistor M11;
[0046] The third pull-down sub-mo...
Embodiment 3
[0089] Based on the same inventive concept as that of Embodiment 1 and Embodiment 2 of the present invention, Embodiment 3 of the present invention provides a gate drive circuit, the schematic diagram of which is shown in Figure 6 As shown, the gate drive circuit includes a plurality of shift register units as described in Embodiment 1: S / R(1), S / R(2)...S / R(N), a total of N shift register units Register unit, except for the first shift register unit and the last shift register unit, the transfer signal output terminals of each shift register unit are connected To the reset signal input terminal of the upper shift register unit adjacent to it and the transfer signal input terminal of the next shift register unit adjacent to it, the gate drive circuit sequentially outputs the gates of the shift register units of each level The gate drive signal output by the pole drive signal output terminal;
[0090] The transfer signal output terminal of the first shift register unit is conn...
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