111 results about "Capacitive feedback" patented technology

Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The amplifier can be operated at a low or no power level during an integration period of a photodetector to reduce power dissipation. The amplifier can be distributed, with an amplifier element within each pixel of an array and with amplifier output circuitry outside the pixel array. The amplifier can be a single ended cascode amplifier, a folded cascode amplifier, a differential input telescopic cascode amplifier, or other configuration. The amplifier can be used in pixel configurations where the amplifier is directly connected to the photodetector, or in configurations which use a transfer transistor to couple signal charges to a floating diffusion node with the amplifier being coupled to the floating diffusion node.

An interference tolerant capacitive touch sensor readout circuit having improved power and area efficiency is disclosed. Interference rejection for the capacitive touch sensing system is realized by transferring charge between a capacitive touch sensor and the readout circuit at frequencies outside bands where a level of interference is unacceptable. Improved power and area efficient come from the simplicity of the readout circuit which comprises a switched-capacitor integrator, a comparator, a digital accumulator and number of switches for driving a touch sensor and a capacitive feedback loop. The readout circuit is capable of interfacing with both self and mutual capacitance sensor to achieve compatibility with a larger collection of sensors and provides additional sensing and diagnostic functionalities.

A CCD imaging array and a charge measurement amplifier for use in such imaging arrays is disclosed. The array includes a plurality of pixels that accumulate charge when exposed to light, a readout amplifier having input and output ports. The readout amplifier has a variable gain that is set by a gain control signal. The readout amplifier also includes a reset path between the input and output ports, the path having an impedance controlled by a reset signal. A controller generates the gain control signal and the reset signal during a charge measurement cycle. Initially the gain is set to a first value after generating the reset signal. The gain is changed to a second value during the charge measurement cycle if the output signal exceeds a first threshold value. The readout amplifier can be constructed from an operational amplifier having a capacitive feedback loop.

An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

An approach is provided for detecting EM waves using a photodetector coupled to an amplifier stage. The amplifier stage uses capacitive feedback to reduce or cancel intrinsic capacitance of the photodetector. A variety of capacitance structures may be used to provide the capacitive feedback such as shielded capacitors and capacitor arrays. The amplifier stage may be either single-ended or fully differential, depending upon the requirements of a particular application. Noise cancellation circuitry may also be included to reduce noise and offset sources present in the amplifier stage. The approach is applicable to a variety of contexts and applications. Example applications include, without limitation, detection of both brightness and Time of Flight (TOF) in 3D sensing applications. The approach may also be used to detect EM wave intensity in 2D sensing systems and, in general, for any application requiring simultaneously high speed and high sensitivity EM detection.

A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.

The present invention relates to double-tilt specimen holders of the side-entry type for transmission electron microscopy (TEM). The invention uses Micro Electro Mechanical Systems (MEMS) and Piezoelectric Transducer (PZT) technology to create a digitally programmable dynamically tilting specimen holder integrated into a standard transmission electron microscope stage.

In this invention, specimens can be tilted using a MEMS/PZT-actuated specimen holder to between 10 and 25° for stereo pairs and at higher angles (up to 90°) for tomography applications. In one embodiment, the specimen cradle may be effectively rotated 360° about the Y axis, enabling virtually the complete three-dimensional mapping of a specimen. By incorporating closed-loop capacitive feedback sensors for sub-nanometer positional control, the specimen holder allows rapid movement and full digital control of specimen tilt, enabling a number of novel techniques including real-time stereo imaging, auto crystal plane alignment and zero loss imaging.

A CMOS active pixel for image sensors has a photosensitive element, a capacitive feedback element with a capacitance CF, and four transistors, namely a first transistor, two reset transistors and a transistor for the selection of the pixel. These transistors are laid out and controlled in such a way that the first transistor is mounted as an amplifier during the pixel reset phase and as a follower during the read phase.

The present invention is related to a device comprising a capacitive feedback transimpedance operational amplifier, that comprises a main operational amplifier (with a first input, a second input and an output) and an integrating capacitor, connected between the second input and the output, and a first switch connected in parallel to the integrating capacitor. The device further comprises an auto-zero operational amplifier having a third input and a fourth input, whereby to the third input and the first input signals at virtual ground potential are applied. The fourth input is connected to the output by a circuit comprising two offset error capacitors, a second switch and a third switch.

A power amplifier includes an input amplifier, a comparator, a switching circuit, an output filter and a feedback filter. The input amplifier receives an input signal of the power amplifier at a positive input of the input amplifier and an output signal of the feedback filter at a negative input of the input amplifier. The input amplifier has a capacitive feedback from an output of the input amplifier to the negative input of the input amplifier. The comparator receives the output signal of the input amplifier at a positive input of the comparator and the output signal of the feedback filter at a negative input of the comparator. The comparator provides a control signal based on a comparison between signal levels of the signals at the positive and the negative inputs of the comparator. The switching circuit includes power switches and receives the control signal and controls the power switches that connect an output of the switching circuit to either a positive supply voltage or a negative supply voltage based on the control signal. The output filter receives an output signal provided at the output of the switching circuit and provides a filtered signal thereof to an output of the power amplifier. The feedback filter receives the output of the power amplifier and provides a filtered feedback signal to the negative input of the comparator and towards the negative input of the input amplifier.

An analog-to-digital converter (ADC) having a reduced number of amplifiers and feed-forward signal paths provides for reduced complexity and power consumption. The analog-to-digital converter includes a delta-sigma modulator having a loop filter with second-order stages implemented with a single amplifier each, provided by a series-connected capacitive feedback network with a switched capacitor shunt. The reduction in the amplifier stages reduces the number of inputs to, and dynamic range required from, the summing node that provides input to the quantizer, as well as reducing the power requirements and complexity of the circuit due to the reduced number of amplifiers.

The invention discloses a variable gain low-noise driving amplifier. The amplifier has a fully differential cascode structure, wherein a common gate consists of three side-by-side silicon germanide bipolar transistors; the central silicon germanide bipolar transistor adopts parallel capacitive feedback, a reasonable input/output matching circuit is adopted, a high variable gain is provided for a circuit, and the noise coefficient is reduced; a cascade circuit provides a high variable gain and increases the reverse isolation of the circuit at the same time; and a common source amplifying circuit further improves the gain of the circuit. By controlling the selection of an external bias, the variable gain with a 3dB step length is obtained. The variable gain low-noise driving amplifier has the characteristics of high variable gain, low noise and low power consumption.

The invention relates to a capacitance negative feedback type low noise amplifier. The existing low noise amplifier is complex in circuit structure and is existed with outside noise. The invention provides a capacitance feedback type low noise amplifier with simple structure, the low noise amplifier can balance and amplify conflict between noise matching and power matching of circuit without introducing extra outside noise. In the invention, an appropriate capacitance value is added between the source electrode and drain electrode of a field effect tube on the basis of low noise amplifier circuit after initial design, thus optimal input matching point of the low noise amplifier circuit can be close to the optimal noise matching point. The essence thereof is that the real part of optimal input matching impedance of the original amplifying circuit is changed and is caused to be closer to the real part of optimal noise matching impedance of amplifying circuit. The invention is simple in circuit structure and is convenient to implement; and conflict between noise matching and input matching of low noise amplifier can be balanced.

An output buffer (100, 200) in accordance with the present invention exhibits a fixed output signal slew rate. The output signal behavior is independent of the capacitive load (CL) seen by the buffer. The circuit includes a capacitive feedback path from the output node to circuitry which drives the output transistors. In one embodiment, the feedback path comprises two capacitive elements (CFP, CFN), one which comes into play during a rising edge transition and the other which affects a falling edge transition. In a second embodiment, a single capacitive element (CF) is coupled to a switching circuit for use during either a falling transition or a rising transition. The second embodiment provides precharging of the output transistor gates, and so improves response time.

The invention discloses a power transmission real-time monitoring system, which comprises a signal frequency acquisition circuit, a phase shift feedback circuit and a frequency selection output circuit, and is characterized in that the signal frequency acquisition circuit adopts an SJ-type; A signal frequency collector J1 of the ADC collects the frequency of a data signal received by a control terminal in the power transmission real-time monitoring system. The phase shift feedback circuit uses an operational amplifier AR1, resistors R5 to R8 and a capacitor C3. the capacitor C4 forms a phase shift circuit to adjust the signal pulse width; A triode Q1 and a voltage-regulator tube D7 are used for voltage stabilization and then input into the in-phase input end of an operational amplifier AR4, a triode Q2 and a capacitor C6 are used for feeding back signals to the base electrode of a triode Q3, a triode Q4 is used for feeding back signals to the emitting electrode of the triode Q3. Finally, the frequency selective output circuit uses a resistor R16-resistor R18 and a capacitor C8-capacitor C10 to form a frequency selective circuit to screen out a single frequency signal output., so that the frequency of a data signal received by a control terminal in the power transmission real-time monitoring system can be monitored in real time, and signal frequency modulation and voltage stabilization are carried out.

A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.