284 results about "Power management integrated circuit" patented technology

The invention provides a voltage control circuit and a display device.The voltage control circuit comprises a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit, the power-on reset circuit correspondingly outputs a third level signal or a fourth level signal during power-on or power-off, the comparison circuit compares power supply voltages, and the switch control circuit controls the first switch circuit and the second switch circuit. The switch control circuit correspondingly controls the on-off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit, and the power-off voltage can be detected through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit. When voltage rebound occurs in the power-down process, the first switching circuit can be effectively kept switched off, and abnormal restart of the power management integrated circuit is prevented, so that the problem of picture abnormity or splash screen caused by abnormal power-on of the display panel is effectively prevented, and the display quality and the user experience of the display device are improved.

The embodiment of the invention discloses a method and a device for controlling charging, charging equipment and a computer readable storage medium, which are used for performing electrochemical impedance spectroscopy analysis by using a second charging protocol and controlling charging through a power management integrated circuit, so that the precision of the electrochemical impedance spectroscopy analysis can be improved. The method comprises the steps of receiving a first communication frame sent by power supply equipment under the condition of detecting that the power supply equipment is inserted and charging is performed by using a first charging protocol; when it is determined that the second charging protocol is used for charging, a first instruction is sent to the power supply equipment according to the first communication frame; acquiring a plurality of first voltage values and a plurality of first current values for charging by using a second charging protocol, wherein the plurality of first voltage values form a first voltage sequence and the plurality of first current values form a first current sequence; and under the condition that at least one of the first voltage sequence and the first current sequence meets a step response condition, calculating a first battery impedance value, and sending a second instruction to the power supply equipment.

An electronic device includes: an interface; charging circuitry; a power management integrated circuit (PMIC); a processor; a plurality of battery cells comprising a first battery cell and a second battery cell; and switching circuitry to control an electrical connection of the plurality of battery cells, the switching circuitry being connected to the first node and the second node. The switching circuitry includes: a first switch to establish an electrical connection between the first node, and an anode of the first battery cell, based on a control signal received from the processor; a diode including an anode connected to a cathode of the first battery cell, and a cathode connected to an anode of the second battery cell; and a second switch to establish an electrical connection between the second node, and the anode of the first battery cell, in another state different from a state.

The invention relates to the technical field of integrated circuit power supply, in particular to a modular multi-stage distributed power supply architecture and method for a whole wafer computing system, the architecture comprises a computing wafer, a power supply module, a bearing substrate and an integrated heat dissipation system, the computing wafer is integrated with various computing units with different voltage requirements, and the power supply module is connected with the integrated heat dissipation system. The power supply module is integrated with the computing wafer through a high-density interconnection interface, a multi-stage power supply topology is adopted in the power supply module, the power supply module comprises a first-stage central power management unit, a second-stage distributed voltage regulation unit array, a high-density embedded capacitor array and a global multi-domain power management integrated circuit, and the bearing substrate is used for bearing related parts. The integrated heat dissipation system carries out differential heat dissipation according to different heat dissipation densities. According to the invention, global optimization of power supply efficiency, precision and thermal management can be realized, and the complex power supply problem of the whole wafer system can be effectively solved.

The invention provides a compensation output circuit, a driving circuit of a display panel and a display device.The compensation output circuit comprises a hysteresis circuit, a signal amplification circuit and a compensation circuit, and the hysteresis circuit delays first common electrode voltage output by a power management integrated circuit; the first common electrode voltage and the second common electrode voltage are output synchronously, meanwhile, the signal amplification circuit carries out signal amplification on the first common electrode voltage output in a delayed mode and outputs target voltage to the compensation circuit, and the compensation circuit generates compensation voltage according to the target voltage and the second common electrode voltage obtained through feedback. The first common electrode voltage and the second common electrode voltage are synchronously output to the compensation circuit for compensation processing through the hysteresis circuit and the signal amplification circuit, so that generation of voltage spikes and startup splash screen are avoided, and the display effect is improved.

A disclosed power management integrated circuit includes (1) a voltage source electrically coupled to a voltage output of a portion of a processing unit, (2) a prediction circuit electrically coupled to the voltage source, the prediction circuit comprising an artificial neural network (ANN) model trained to predict an inductor current based on a voltage received via the voltage source, and a management circuit configured to manage power usage of the processing unit based on a predicted inductor current received from the prediction circuit, the predicted inductor current predicted via the ANN model based on the voltage received via the voltage source. Various other apparatuses, systems, and methods for improving processor power management via ANNs are also disclosed.

The invention provides a power supply output circuit and a display device, the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power supply output circuit, a first detection circuit, a second detection circuit and a logic control circuit, during dormancy, the comparison circuit stops outputting a first wake-up signal, and the power supply output circuit stops outputting a starting voltage; when the first detection circuit and the second detection circuit stop working, the power consumption of the display device during dormancy is reduced, and when the display device is awakened and low-voltage rebound of the power supply voltage or the power supply voltage occurs, the logic control circuit does not receive the first awakening signal, the second awakening signal and the third awakening signal at the same time, the output of the first enable signal is stopped; and the power management integrated circuit does not work, so that the problems of circuit damage and picture abnormity caused by low-voltage rebound are prevented, and the working safety and the display effect of the circuit are improved.

A display device includes a display panel, a display panel driving circuit, and a power management integrated circuit (PMIC) configured to generate a driving voltage, receive driving setting data from a timing controller, store a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determine a voltage level of the driving voltage based on the driving hexadecimal value. The PMIC divides the driving hexadecimal value into an upper decimal value and a lower decimal value, derives a result decimal value by applying the upper decimal value and the lower decimal value to a first authentication formula, generates a result hexadecimal value based on the result decimal value, compares an authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operates in a normal mode or a protection mode based on a result of the comparison between the authentication hexadecimal value and the result hexadecimal value.

An electronic device includes: an antenna, a PAM including a PA configured to amplify a transmitting signal and a protection circuit, a PMIC configured to supply voltage to the PA, and at least one processor is configured to: provide a first signal, to a NAND gate in the protection circuit, provide to a AND gate in the protection circuit, a second signal indicating a result of a logical operation between the first signal and a bias enable signal for the PA, provide to the AND gate, a third signal indicating whether the transmitting signal is input to the PAM, provide to a switching circuit, a fourth signal indicating a result of logical operation between the second signal and the third signal, identify whether to apply a bias voltage to the PA based on the fourth signal, and transmit the transmitting signal, to the external electronic device, via the antenna.

The utility model relates to the technical field of charging circuits, in particular to a small-capacity battery adjusting protection circuit, which is used for protecting a rechargeable battery when the rechargeable battery is connected to a charging device for charging and comprises a CPU (central processing unit) module, a charging and discharging switching control circuit and a power management integrated circuit. The power management integrated circuit is arranged between the charging device and the rechargeable battery, and the output end of the charging device is electrically connected with the input end of the power management integrated circuit; through the cooperation of the power management integrated circuit, the CPU module and the charging and discharging switching control circuit, the battery state can be accurately monitored in real time, and the over-discharging and over-charging phenomena of the rechargeable battery are effectively avoided, so that the problem of swelling of the rechargeable battery is solved, the service life of the rechargeable battery is prolonged, and the safety performance of equipment is remarkably improved. The battery management efficiency is optimized, more stable and reliable equipment use experience is provided for a user, and meanwhile the battery management system is simple in structure and low in manufacturing cost.

A circuit board apparatus employing a stacked circuit board and with inductor (s) for routing power from a power management integrated circuit (IC) (PMIC) to a secondary circuit board, and related methods of manufacture. The inductor (s) is coupled in a first vertical direction between the first circuit board and the second circuit board as part of a power routing path between the PMIC on the first circuit board and the second electronic component (s) of the second circuit board. In this manner, the PMIC may be shared between the first circuit board and the second circuit board to manage power signals provided to the first electronic component (s) and the second electronic component (s) of the first circuit board. The inductor (s) may also be strategically positioned to provide a shorter power signal routing path to reduce or avoid power performance issues with a reduced impedance between the PMIC and the second electronic component (s).

In an aspect, an integrated circuit (IC) package includes a package substrate including at least a first power node and a second power node; an interposer on the package substrate; and an IC die on the interposer. The interposer may include a dielectric layer and a power management integrated circuit (PMIC) embedded in the dielectric layer, where the PMIC includes a third power node and a fourth power node, and the third power node may be electrically coupled to the first power node. The IC die may include a fifth power node and a sixth power node, where the fifth power node may be electrically coupled to the fourth power node, and the sixth power node may be electrically coupled to the second power node.

Some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. The semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. The discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. During a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.

A multi-power management integrated circuit (PMIC) with a shared output is disclosed herein. More specifically, two or more PMICs can generate a shared output while balancing the current provided by the PMICs without being affected by device and component mismatches and inter-component variations. This balancing is accomplished by providing a current feedback loop and a shared voltage loop to each PMIC when multiple PMICs are active. When only a single PMIC is active, a switch deactivates the shared voltage feedback loop and activates a local voltage feedback loop. The use of multiple PMICs enables higher supply voltages to be provided to power amplifiers in a transmission chain to meet the requirements of emerging wireless standards while also maintaining better efficiency of the transmission chain.

The present invention proposes a voltage control circuit and a display device, wherein the voltage control circuit includes a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit. The power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when the power is turned on or off. The comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly. The switch control circuit controls the on and off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit. Through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected. When a voltage rebound occurs during the power-off process, the first switch circuit can be effectively kept off to prevent the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from abnormally powering on and causing screen abnormalities or flickering problems, thereby improving the display quality and user experience of the display device.

A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

The utility model discloses an RVC camera module and a dynamic vehicle auxiliary line system. The RVC camera module comprises a lens, a sensor, a graphic signal processor ISP, a serializer Serdes, a POC circuit module, a connector and a power management chip PMIC (Power Management Integrated Circuit), the lens is in signal connection with the sensor; the sensor is in signal connection with the image signal processor ISP; the image signal processor ISP is in signal connection with the serializer Serdes; the serializer Serdes is in signal connection with the POC circuit module and the connector respectively; the POC circuit is in signal connection with the power management PMIC; the power management PMIC supplies power to the sensor, the image signal processor ISP and the serializer Serdes respectively. According to the utility model, the dynamic vehicle auxiliary line can be generated in the camera, so that the overall equipment cost of the reversing image system is reduced.

An example method includes, responsive to determining that a button of a mobile computing device has been pressed for longer than a first amount of time, resetting a power management integrated circuit (PMIC); responsive to determining that the button of the mobile computing device has been pressed for longer than a second amount of time that is longer than the first amount of time, electrically disconnecting, at a first time, power sources from the mobile computing device; and electrically reconnecting, at a second time that is after the first time, the power sources to the mobile computing device.

A multi-mode power management integrated circuit (PMIC) is provided. Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analog and digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.

An electronic device may include a wireless communication circuit, a battery, a power management integrated circuit (PMIC) electrically connected to the wireless communication circuit and the battery and including a regulator, and a processor electrically connected to the wireless communication circuit, the battery, and the PMIC. The processor may, responsive to the electronic device satisfying a specified condition, identify a change in a magnitude of a voltage of an output terminal of the regulator for a first time interval, identify a ratio of a time interval during which the change in the magnitude of the voltage of the output terminal satisfies a threshold value with respect to the first time interval, and adjust the magnitude of the voltage of the output terminal in a step-wise manner based on the ratio.

Aspects of the present disclosure relate to techniques and apparatus for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to a boot core or cluster of the SoC based on the BCI signal.

The present application relates to improved heat management in semiconductor devices and methods for manufacturing the same. Disclosed herein are improved memory modules and methods for constructing the same. The memory module includes a substrate having a first surface and a second surface opposite the first surface, the first surface and the second surface each having a center portion, a first array region, and a second array region. The first array region is cooler than the second array region during operation. The memory module also includes a power management integrated circuit attached to the center portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array region. The first semiconductor die has a first performance level for operating parameters at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array region. The second semiconductor die has a second performance level for operating parameters at high temperatures that is better than the first performance level.

The utility model discloses an ink screen drive circuit, which comprises a mainboard, a power management integrated circuit, a power electronic switch, a first conversion circuit and a second conversion circuit, the mainboard is connected with the first conversion circuit and the second conversion circuit, the power management integrated circuit is connected with the first conversion circuit, and the power electronic switch is connected with the second conversion circuit. The power electronic switch is connected with the second conversion circuit, the first conversion circuit is used for converting a control signal provided by a mainboard into a voltage signal suitable for driving the ink screen, and the second conversion circuit is used for converting a power signal provided by the power management integrated circuit into a power signal suitable for driving the ink screen. The power electronic switch is used for controlling on-off of a power supply of the ink screen. According to the utility model, the power supply signal more suitable for driving the ink screen can be provided, so that the problem that the original experience on driving the LCD screen is not suitable for the electronic ink screen is solved.

A method and a computer program product provide for various operations in a computer. The operations may comprise detecting that a power management integrated circuit has experienced a power fault, wherein the power management integrated circuit is included in a memory module that is installed in a slot of a computer. The operations may further comprise powering off the memory module and attempting to access a fault register of the power management integrated circuit in response to detecting the power fault. Still further, the operations may comprise storing a fault flag in non-volatile memory of a management controller in the computer in response to the power management integrated circuit being inaccessible, wherein the fault flag is stored in association with a serial number of the memory module and a slot identifier for the slot of the computer where the memory module is installed.

A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

According to one embodiment, an electronic device may comprise: a power management integrated circuit; at least one processor; a connection terminal; at least one memory for storing identification information of the electronic device; a first transmission line electrically connected to the connection terminal and the power management integrated circuit; a control circuit electrically connected to the at least one memory; and a switching circuit electrically connected between the connection terminal and the control circuit. When a voltage applied, through the first transmission line, from an external electronic device connected to the connection terminal is within a preset first range, the switching circuit changes the state of a switch from a first state to a second state so as to electrically connect the connection terminal to the control circuit and supply power to the control circuit, thereby transmitting the identification information to the external electronic device through the connection terminal.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A power management integrated circuit and a method of operating the power management integrated circuit are disclosed. The power management integrated includes an upper regulator circuit that receives a system voltage as an input and outputs a first output voltage; a lower regulator circuit having the first output voltage as an input; and a Kelvin switch circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switch circuit includes a plurality of switches that connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

The embodiment of the invention relates to the technical field of industrial communication, and particularly discloses a multi-operator link aggregation and intelligent switching router, a communication control method and a PCB radio frequency isolation structure, the multi-operator link aggregation and intelligent switching router comprises a battery, a power management integrated circuit PMIC, a wireless local area network module, a master control MCU and a plurality of mobile communication modules, the plurality of mobile communication modules support a plurality of SIM card slots; the main control MCU is used for periodically acquiring network state parameters from the plurality of mobile communication modules, forming link quality time sequence data and mapping a comprehensive quality score; based on the comprehensive quality score, generating a target working mode instruction according to a preset multi-dimensional decision matrix; and controlling a power management integrated circuit (PMIC) to adjust power supply domain states of the plurality of mobile communication modules based on the target working mode instruction. The system can be suitable for industrial data acquisition and remote control in scenes with complex electromagnetic environments and severe power supply conditions, such as mines, oil fields, remote mountainous areas and warfare areas.