190 results about "Power management integrated circuit" patented technology

The invention relates to the technical field of integrated circuit power supply, in particular to a modular multi-stage distributed power supply architecture and method for a whole wafer computing system, the architecture comprises a computing wafer, a power supply module, a bearing substrate and an integrated heat dissipation system, the computing wafer is integrated with various computing units with different voltage requirements, and the power supply module is connected with the integrated heat dissipation system. The power supply module is integrated with the computing wafer through a high-density interconnection interface, a multi-stage power supply topology is adopted in the power supply module, the power supply module comprises a first-stage central power management unit, a second-stage distributed voltage regulation unit array, a high-density embedded capacitor array and a global multi-domain power management integrated circuit, and the bearing substrate is used for bearing related parts. The integrated heat dissipation system carries out differential heat dissipation according to different heat dissipation densities. According to the invention, global optimization of power supply efficiency, precision and thermal management can be realized, and the complex power supply problem of the whole wafer system can be effectively solved.

The invention provides a power supply output circuit and a display device, the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power supply output circuit, a first detection circuit, a second detection circuit and a logic control circuit, during dormancy, the comparison circuit stops outputting a first wake-up signal, and the power supply output circuit stops outputting a starting voltage; when the first detection circuit and the second detection circuit stop working, the power consumption of the display device during dormancy is reduced, and when the display device is awakened and low-voltage rebound of the power supply voltage or the power supply voltage occurs, the logic control circuit does not receive the first awakening signal, the second awakening signal and the third awakening signal at the same time, the output of the first enable signal is stopped; and the power management integrated circuit does not work, so that the problems of circuit damage and picture abnormity caused by low-voltage rebound are prevented, and the working safety and the display effect of the circuit are improved.

The utility model relates to the technical field of charging circuits, in particular to a small-capacity battery adjusting protection circuit, which is used for protecting a rechargeable battery when the rechargeable battery is connected to a charging device for charging and comprises a CPU (central processing unit) module, a charging and discharging switching control circuit and a power management integrated circuit. The power management integrated circuit is arranged between the charging device and the rechargeable battery, and the output end of the charging device is electrically connected with the input end of the power management integrated circuit; through the cooperation of the power management integrated circuit, the CPU module and the charging and discharging switching control circuit, the battery state can be accurately monitored in real time, and the over-discharging and over-charging phenomena of the rechargeable battery are effectively avoided, so that the problem of swelling of the rechargeable battery is solved, the service life of the rechargeable battery is prolonged, and the safety performance of equipment is remarkably improved. The battery management efficiency is optimized, more stable and reliable equipment use experience is provided for a user, and meanwhile the battery management system is simple in structure and low in manufacturing cost.

A circuit board apparatus employing a stacked circuit board and with inductor (s) for routing power from a power management integrated circuit (IC) (PMIC) to a secondary circuit board, and related methods of manufacture. The inductor (s) is coupled in a first vertical direction between the first circuit board and the second circuit board as part of a power routing path between the PMIC on the first circuit board and the second electronic component (s) of the second circuit board. In this manner, the PMIC may be shared between the first circuit board and the second circuit board to manage power signals provided to the first electronic component (s) and the second electronic component (s) of the first circuit board. The inductor (s) may also be strategically positioned to provide a shorter power signal routing path to reduce or avoid power performance issues with a reduced impedance between the PMIC and the second electronic component (s).

Some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. The semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. The discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. During a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.

The utility model discloses an RVC camera module and a dynamic vehicle auxiliary line system. The RVC camera module comprises a lens, a sensor, a graphic signal processor ISP, a serializer Serdes, a POC circuit module, a connector and a power management chip PMIC (Power Management Integrated Circuit), the lens is in signal connection with the sensor; the sensor is in signal connection with the image signal processor ISP; the image signal processor ISP is in signal connection with the serializer Serdes; the serializer Serdes is in signal connection with the POC circuit module and the connector respectively; the POC circuit is in signal connection with the power management PMIC; the power management PMIC supplies power to the sensor, the image signal processor ISP and the serializer Serdes respectively. According to the utility model, the dynamic vehicle auxiliary line can be generated in the camera, so that the overall equipment cost of the reversing image system is reduced.

A multi-mode power management integrated circuit (PMIC) is provided. Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analog and digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.

Aspects of the present disclosure relate to techniques and apparatus for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to a boot core or cluster of the SoC based on the BCI signal.

The utility model discloses an ink screen drive circuit, which comprises a mainboard, a power management integrated circuit, a power electronic switch, a first conversion circuit and a second conversion circuit, the mainboard is connected with the first conversion circuit and the second conversion circuit, the power management integrated circuit is connected with the first conversion circuit, and the power electronic switch is connected with the second conversion circuit. The power electronic switch is connected with the second conversion circuit, the first conversion circuit is used for converting a control signal provided by a mainboard into a voltage signal suitable for driving the ink screen, and the second conversion circuit is used for converting a power signal provided by the power management integrated circuit into a power signal suitable for driving the ink screen. The power electronic switch is used for controlling on-off of a power supply of the ink screen. According to the utility model, the power supply signal more suitable for driving the ink screen can be provided, so that the problem that the original experience on driving the LCD screen is not suitable for the electronic ink screen is solved.

A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A power management integrated circuit and a method of operating the power management integrated circuit are disclosed. The power management integrated includes an upper regulator circuit that receives a system voltage as an input and outputs a first output voltage; a lower regulator circuit having the first output voltage as an input; and a Kelvin switch circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switch circuit includes a plurality of switches that connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

The embodiment of the invention relates to the technical field of industrial communication, and particularly discloses a multi-operator link aggregation and intelligent switching router, a communication control method and a PCB radio frequency isolation structure, the multi-operator link aggregation and intelligent switching router comprises a battery, a power management integrated circuit PMIC, a wireless local area network module, a master control MCU and a plurality of mobile communication modules, the plurality of mobile communication modules support a plurality of SIM card slots; the main control MCU is used for periodically acquiring network state parameters from the plurality of mobile communication modules, forming link quality time sequence data and mapping a comprehensive quality score; based on the comprehensive quality score, generating a target working mode instruction according to a preset multi-dimensional decision matrix; and controlling a power management integrated circuit (PMIC) to adjust power supply domain states of the plurality of mobile communication modules based on the target working mode instruction. The system can be suitable for industrial data acquisition and remote control in scenes with complex electromagnetic environments and severe power supply conditions, such as mines, oil fields, remote mountainous areas and warfare areas.

Intra-symbol voltage change acceleration in a wireless transmission circuit is disclosed. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage supplied by a power management integrated circuit (PMIC). The RF signal is modulated in multiple modulation symbols, such as orthogonal frequency division multiplex (OFDM) symbols. To prevent distortion (e.g., amplitude clipping) in the RF signal, the PMIC is configured to increase the APT voltage during each of the modulation symbols whenever the RF signal exceeds a predefined power threshold. Further, the PMIC is configured according to various acceleration embodiments to complete each APT volage change within a defined temporal limit (e.g., <1 μs). By supporting intra-symbol voltage change acceleration, the wireless transmission circuit can enable fast APT voltage adaptation to thereby improve operating efficiency of the power amplifier circuit.

The invention belongs to the technical field of intelligent networked automobile electronics, and particularly relates to an intelligent vehicle-mounted terminal, which comprises an SiP core module, a main processor bare crystal, a high-bandwidth memory stack, a nonvolatile storage bare crystal, a power management integrated circuit bare crystal, a Beidou double-frequency positioning navigation bare crystal, an inertial measurement unit and a wireless communication bare crystal are integrated in the SiP core module, wherein the high-bandwidth memory stack, the nonvolatile storage bare crystal, the power management integrated circuit bare crystal, the Beidou double-frequency positioning navigation bare crystal, the inertial measurement unit and the wireless communication bare crystal are vertically stacked on the main processor bare crystal through a silicon through hole technology. The heat dissipation system comprises a vapor chamber, a heat dissipation fin group arranged on the vapor chamber and a centrifugal fan; and the metal shell is used for accommodating the SiP core module and the heat dissipation system, and an external interface is arranged on the metal shell. Functional units such as calculation, storage, communication, positioning and inertial navigation are integrated, the size is greatly reduced, the reliability is improved, an active heat dissipation scheme that the vapor chamber is combined with the centrifugal fan is adopted, and performance degradation caused by overheating is avoided.

A device may include a first front-end module (FEM) configured to receive a supply voltage, the first FEM comprising a power management integrated circuit (PMIC) coupled to a voltage line. A device may include a second FEM coupled to the PMIC via the voltage line, the PMIC configured to distribute voltage to the second FEM via the voltage line.

Electronic device and method for managing power The invention relates to an electronic device comprising a power management integrated circuit (PMIC) for managing power from an energy harvester, comprising: a storage unit, an internal DC-DC converter embedded within the PMIC, optimized for a first, lower power range; and an external DC-DC converter controlled by the PMIC, optimized for a second, higher power range. Both DC-DC converters have an input and an output. According to the invention, both the outputs of the internal and external DC-DC converters are connected in parallel to the storage unit and the power paths of the external DC-DC converter are located outside of the PMIC. Further according to the invention, the PMIC is configured to automatically switch between the internal and external DC-DC converters as active converter to extract energy from the energy harvester or to allow them to run simultaneously to extract energy from the energy harvester based on the power level provided by the energy harvester.

A power management circuit operable with a reduced voltage range is provided. Herein, a power management integrated circuit (PMIC) is configured to generate an envelope tracking (ET) voltage whereby a power amplifier circuit can amplify a radio frequency (RF) signal for transmission. Specifically, the power management circuit can be configured according to various embodiments to achieve the reduced voltage range by applying a combination of load modulation and supply modulation across a larger voltage range (e.g., a peak-to-peak voltage range) required for amplifying the RF signal between a peak-to-peak power range (a.k.a. minimum to maximum power range). By dynamically reducing the voltage range of the RF signal, the PMIC and / or the power amplifier circuit in the power management circuit can operate with an improved efficiency to thereby provide an improvement in the user experience.

This application is directed to providing rail voltages for an electronic system. In some examples, an electronic system includes a first chiplet and a second chiplet. Each of the first chiplet and second chiplet include a plurality of voltage regulation units configured to provide a voltage regulator set. The first chiplet also includes a reference circuit electrically coupled to the voltage regulator set and configured to generate a reference voltage. Further, the first voltage regulator set of the first chiplet is configured to generate a rail voltage based on the reference voltage from the reference circuit. In addition, the voltage regulator set of the first chiplet is configured to provide the rail voltage to a power rail, and provide the reference voltage to the regulator set of the second chiplet to generate the same or different rail voltage.

A PMIC controls multiple power supply circuits. Nonvolatile memory supports repeated writing and has multiple pages. A memory control circuit selects one from among the multiple pages of the nonvolatile memory and writes internal data that indicates an internal state of the power supply management circuit to the write target page. The memory control circuit selects an already-erased page as the write target page and writes the internal data to it, and erases pages other than the write target page.

Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.

A driving circuit for an audio power amplifier and an electronic device are provided. The driving circuit includes an audio codec, an audio power amplifier (PA), a power management integrated circuit (PMIC), a transistor, a speaker, and a motor. The transistor is connected in series with the motor to form a combined body, the speaker is connected in parallel with the combined body to form a two-in-one device, the audio PA is connected in series with the two-in-one device, the PMIC is connected in series with the two-in-one device, and the audio codec is connected in series with the audio PA. In the technical solutions provided in embodiments of the disclosure, a power amplifier can drive both the motor and the speaker, so that a power amplifier may be omitted and the power consumption and cost of the electronic equipment may be reduced.

A semiconductor memory module is disclosed. The semiconductor memory module includes a memory printed circuit board (PCB) including a plurality of first connectors configured to be connectable with an external device, a second connector, and a third connector, memory devices mounted on the memory PCB and connected with the plurality of first connectors, and a power management integrated circuit mounted on the memory PCB, receiving a first voltage through the second connector, generating a second voltage from the first voltage, and providing the second voltage to the plurality of memory devices. The power management integrated circuit adjusts the second voltage according to a difference between a signal received through the third connector and the second voltage.

This application is directed to feedback for power management of a memory die using shorting. A memory device can short a first rail to a voltage source for communicating feedback about a supply voltage to a power management component, such as a power management integrated circuit of a memory system. The memory device can detect a condition of one or more voltage rails coupled with the array of memory cells for delivering power. The memory device can short a first rail of the network of components for delivering power to a voltage source based on detecting the condition. In some cases, the memory device can generate a feedback signal across the first rail of the network of components for delivering power based on shorting the first rail.

The invention belongs to the technical field of display, and particularly relates to a voltage division circuit, a display panel and a driving method of the display panel. The inverting input end of the comparator is connected with the power management integrated circuit, the in-phase input end of the comparator is connected with a reference voltage, and the output end of the comparator is connected with the input end of the controller; the input end of the first voltage dividing module is connected with the first output end of the controller; the input end of the second voltage dividing module is connected with the second output end of the controller; wherein when the comparison result output by the comparator indicates that the comparison result is a high-level voltage signal, the controller controls the output end of the first voltage division module to be communicated with the target output end; and when the comparison result output by the comparator indicates that the comparison result is a low-level voltage signal, the controller controls the output end of the second voltage division module to be communicated with the target output end. Through the voltage division circuit and reference voltage updating, the splash screen problem caused by the surge current is solved.

An electrocaloric heat dissipation device is formed by inserting metal layer-pyroelectric layer-metal layer (MPM) structures between the metallization layers in a metal interconnect. Electric fields are alternately applied and relaxed to induce temperatures of the pyroelectric layers to cycle and drive heat transfer. The heat dissipation device may be placed adjacent a hot spot in a power management integrated circuit (PMIC) and is particularly useful when the PMIC is in a 3D package. In some embodiments, the MPM structures are inserted around circuit wiring. Interconnects for the heat dissipation device may replace dummy metal wiring.

A multi-mode power management device is provided. In embodiments disclosed herein, the multi-mode power management device may be configured to operate in different power management modes across a wide modulation bandwidth range (e.g., 80 KHz to 200 MHz or more). The multi-mode power management device includes a power management integrated circuit (PMIC) and an envelope tracking integrated (ET) circuit (ETIC) implemented in a separate die. The PMIC is configured to generate a low frequency current and a low frequency voltage. The ETIC is configured to generate a pair of ET voltages. Depending on the power management mode, the multi-mode power management device may selectively output one or more of the ET voltage and the low frequency voltage to different stages (e.g., a driver stage and an output stage) of a power amplifier circuit, therefore, the optimal efficiency and linearity of the power amplifier circuit can be maintained across the wide modulation bandwidth range.

A single-input, multiple-output (SIMO) voltage circuit in a wireless device is provided. Herein, the SIMO voltage circuit is configured to concurrently generate multiple voltages for amplifying multiple signals based on a reference voltage. In an embodiment, the reference voltage is provided by a power management integrated circuit (PMIC) and multiplexed to indicate respective targets of the voltages. Specifically, the SIMO voltage circuit includes multiple holding capacitors, each of which is repeatedly discharged and recharged to maintain a respective one of the voltages during a voltage generation cycle(s). The SIMO voltage circuit also includes multiple local control loops each configured to regulate a respective one of the voltages to thereby match the respective target indicated by the reference voltage. As such, the SIMO voltage circuit can simultaneously supply the voltages based on a single PMIC, thus making it possible to support multiple load circuits with a smaller footprint.

A PMIC includes a controller configured to determine, based on a configuration stored in the memory, a power on mode, when the power on mode indicates a dynamic power on operation, execute the dynamic power on operation by: determining, of the plurality of channels, a first channel associated with a first dynamic sequence number that is a lowest dynamic sequence number of the plurality of dynamic sequence numbers, enabling the first channel, monitoring the first channel to determine whether the first channel is in a first regulated state, and while monitoring the first channel, determining, of the plurality of channels, a second channel associated with a second dynamic sequence number of the plurality of dynamic sequence numbers, when the power on mode indicates a time based power on operation: iterating a slot counter through the plurality of slot numbers.