31 results about "Power management integrated circuit" patented technology

A multi-voltage power management integrated circuit (PMIC) is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits each configured to generate and maintain a respective one of multiple modulated voltages based on a battery voltage and a respective one of multiple reference voltages. Contrary to using multiple voltage-current modulation circuits, such as direct-current-direct-current (DC-DC) converters, to generate the multiple reference voltages, the multi-voltage PMIC is configured to share a single voltage-current modulation circuit among the multiple voltage modulation circuits. As such, the multi-voltage PMIC can concurrently support multiple load circuits (e.g., power amplifier circuits) with a significantly reduced footprint.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A power management integrated circuit and a method of operating the power management integrated circuit are disclosed. The power management integrated includes an upper regulator circuit that receives a system voltage as an input and outputs a first output voltage; a lower regulator circuit having the first output voltage as an input; and a Kelvin switch circuit connected between the upper regulator circuit and the lower regulator circuit. The Kelvin switch circuit includes a plurality of switches that connect any one of a plurality of upper regulators included in the upper regulator circuit to any one of a plurality of lower regulators included in the lower regulator circuit.

Electronic device and method for managing power The invention relates to an electronic device comprising a power management integrated circuit (PMIC) for managing power from an energy harvester, comprising: a storage unit, an internal DC-DC converter embedded within the PMIC, optimized for a first, lower power range; and an external DC-DC converter controlled by the PMIC, optimized for a second, higher power range. Both DC-DC converters have an input and an output. According to the invention, both the outputs of the internal and external DC-DC converters are connected in parallel to the storage unit and the power paths of the external DC-DC converter are located outside of the PMIC. Further according to the invention, the PMIC is configured to automatically switch between the internal and external DC-DC converters as active converter to extract energy from the energy harvester or to allow them to run simultaneously to extract energy from the energy harvester based on the power level provided by the energy harvester.

A semiconductor memory module is disclosed. The semiconductor memory module includes a memory printed circuit board (PCB) including a plurality of first connectors configured to be connectable with an external device, a second connector, and a third connector, memory devices mounted on the memory PCB and connected with the plurality of first connectors, and a power management integrated circuit mounted on the memory PCB, receiving a first voltage through the second connector, generating a second voltage from the first voltage, and providing the second voltage to the plurality of memory devices. The power management integrated circuit adjusts the second voltage according to a difference between a signal received through the third connector and the second voltage.

An electrocaloric heat dissipation device is formed by inserting metal layer-pyroelectric layer-metal layer (MPM) structures between the metallization layers in a metal interconnect. Electric fields are alternately applied and relaxed to induce temperatures of the pyroelectric layers to cycle and drive heat transfer. The heat dissipation device may be placed adjacent a hot spot in a power management integrated circuit (PMIC) and is particularly useful when the PMIC is in a 3D package. In some embodiments, the MPM structures are inserted around circuit wiring. Interconnects for the heat dissipation device may replace dummy metal wiring.

This invention relates to the field of medical device technology, and more particularly to an implantable cerebrospinal fluid flow monitoring device and system based on wireless charging. The device includes a flat, elliptical housing with a fluid channel extending through its long axis. An upper interface is connected to one end of the fluid channel. A lower interface is fixedly connected to the other end of the housing, and this lower interface is connected to the other end of the fluid channel. A flow sensing module is fitted into the middle of the fluid channel. The square ceramic substrate of the flow sensing module is embedded in a groove in the inner wall of the channel, and its flush design with the inner wall avoids interference with fluid flow. A first temperature sensing chip and a second temperature sensing chip, symmetrically arranged on the upstream and downstream sides, work in conjunction with a micro-heating chip in the middle to ensure accurate flow detection. A wireless charging receiving coil is embedded inside the outer wall of one side of the housing to reduce internal module shielding interference. Combined with a solid-state lithium battery and a power management integrated circuit, this improves charging efficiency and battery life.

A semiconductor device package may include a package substrate, mold material formed over the package substrate, and a mold-embedded inductor that is embedded in the mold material. The mold-embedded inductor may be coupled to a die, such as a power management integrated circuit die, which may also be embedded in the mold material. The mold-embedded inductor may be formed by forming conductive traces and an inductor core in the mold material. For example, an active mold packaging (AMP) process and corresponding laser direct structuring (LDS) processes may be performed to form openings in the mold material and to activate surfaces of the mold material to facilitate subsequent plating of conductive material. Activated surfaces of the mold material may have micro-rough texture and may include bulk conductive material formed via the application of laser energy to additives in the mold material during the LDS process(es).

This application provides a boot method, apparatus, electronic device, and storage medium. The method includes: moving a low-latency communication engine firmware loading and power management integrated circuit into the boot loading stage, and booting during the main core's concurrent idling period in the boot loading stage; completing peripheral initialization in the boot loading stage to obtain shared peripheral initialization artifacts, which include: code segment, data segment, and uninitialized data segment; mapping the shared peripheral initialization artifacts to the same fixed address space as the classic automotive open system architecture platform application in the boot loading stage; deleting the initialization operation of the classic automotive open system architecture platform application, allowing the classic automotive open system architecture platform application to operate on the shared peripheral initialization artifacts. This application enables rapid booting of the classic automotive open system architecture platform and rapid booting of the ECU.

A computing system includes a reconfigurable logic device having a plurality of reconfigurable regions, a PMIC configured to independently control power to respective reconfigurable regions, and a controller coupled to the PMIC. The controller determines, based on at least one of a task indication, a workload condition, or a control command, a subset of the reconfigurable regions to be powered, and causes the PMIC to supply power to each reconfigurable region in the subset and to withhold power from at least one reconfigurable region outside the subset. In some implementations, the controller selects a configuration bitstream associated with a target task and determines the subset based on the bitstream. The system may use sensor telemetry and device-reported task status to update the subset during operation.

Embodiments of this application provide a control method and apparatus for an electronic device, and relate to the field of terminal technologies. The method includes: receiving a second operation of a user at a second moment, where the second operation is an operation of enabling an AON service; in response to the second operation, powering on a second interface in an AON camera by using a first PMIC, where the second moment is after the first moment; and powering on a third interface in the AON camera at a third moment. In this way, the electronic device may supply power to the AON camera by using the first PMIC instead of a specific power management chip, so that applicability of performing power management on the AON camera is improved, and costs are reduced. In addition, in this solution, flexible power management may be performed based on an actual requirement for the AON service. For example, the electronic device may separately power on the second interface and the third interface when enabling the AON service.

The invention relates to a stacked power converter assembly comprising: a substrate; one or more integrated circuits, such as power management integrated circuits, arranged on top of the substrate; one or more passive electrical components stacked on top of the one or more integrated circuits; one or more electrical elements configured to electrically connect the one or more passive electrical components with the substrate; and one or more thermal guides arranged and connected between the one or more passive electrical components and the substrate, wherein the one or more thermal guides are configured to conduct heat; wherein the one or more integrated circuits and the one or more passive electrical components are configured to perform power conversion of an input voltage and / or current to an output voltage and / or current. The invention also discloses a second aspect of a stacked power converter assembly and a method of assembling a stacked power converter assembly.

The power management integrated circuit includes a DC-DC converter configured to generate an internal voltage and output an internal power supply voltage based on the internal voltage. The DC-DC converter includes: a first switch connected between an external power supply voltage and a second node from which the internal voltage is output; a second switch connected between the second node and ground; and a third switch connected between the second node and the external power supply voltage via a resistor. When the internal voltage is normal, the DC-DC converter generates an internal voltage with a level between a first voltage and a second voltage lower than the first voltage by repeatedly switching the first and second switches on and off. When the internal voltage exceeds the first voltage, the DC-DC converter reduces the internal voltage by repeatedly switching the second and third switches on and off.

This disclosure relates to a charging circuit, electronic device, charging method, and charging apparatus. The charging circuit includes: a charging interface and a battery cell; a charge pump circuit connected to the charging interface and the battery cell; a power management integrated circuit connected to the charge pump circuit and the battery cell; and a control circuit connected to the charge pump circuit and the power management integrated circuit, at least for controlling the charge pump circuit and the power management integrated circuit to simultaneously charge the battery cell when the charging circuit is in fast charging mode. Embodiments of this disclosure achieve fast charging while reducing material costs.

Aspects of the present disclosure are directed to techniques and apparatuses for implementing a power-on (PON) sequence in a computer system. A power management integrated circuit (PMIC) receives a boot circuit indicator (BCI) signal from a computer system. The BCI signal identifies a circuit of the computer system to be enabled in a power-on (PON) sequence. The PMIC provides power to the boot core or cluster of the SoC based on the BCI signal.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and / or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

The application provides a common voltage output circuit and a display device. The common voltage output circuit comprises a driving chip, a load adjusting circuit, a comparison circuit and a load control circuit. When the driving chip obtains initial data of a common electrode through communication, the driving chip generates an initial common electrode voltage. The comparison circuit compares the initial common electrode voltage with a threshold voltage and generates a comparison signal when the initial common electrode voltage exceeds the threshold voltage. The load control circuit generates a load adjusting signal according to the comparison signal. The load adjusting circuit reduces the voltage at the common electrode end from a first current to a second current according to the load adjusting signal, thereby reducing the output current of the driving chip and reducing the load output of a power management integrated circuit. The power management integrated circuit does not appear to be powered off at low voltage, thereby avoiding the black screen phenomenon of the display panel and improving the display reliability during the burning test or the driving power-on.

A power management integrated circuit (PMIC) includes a dynamic voltage scaling (DVS) block configured to generate an output voltage signal, and a DVS monitoring block including a DVS monitoring code generator, and a safety monitoring unit configured to receive a DVS code and detect an error in the DVS code. The DVS block is configured to generate the output voltage signal based on the DVS code obtained by reflecting a DVS trim code in the DVS regulation code, and the DVS trim code is determined by a characteristic of a first digital-to-analog converter (DAC) included in the DVS block. The DVS monitoring code generator is configured to generate the DVS monitoring code obtained by reflecting a DVS monitoring trim code in the DVS regulation code, and the DVS monitoring trim code is determined by a characteristic of a second DAC included in the DVS monitoring block.

An electronic device of the present disclosure comprises: a speaker; a display disposed on the front surface of the electronic device; a cover disposed on the rear surface of the electronic device; a printed circuit board including radio frequency (RF) circuits including at least one of a power amplifier or a power management integrated circuit (IC), spaced apart from the speaker; a battery spaced apart from the printed circuit board; a first shielding sheet corresponding to at least a partial area of the battery and the printed circuit board, disposed between the display and the printed circuit board, and configured to shield a magnetic field generated by the RF circuits, from facing the front surface; and a second shielding sheet corresponding to at least a partial area of the battery and the printed circuit board, disposed between the cover, the battery, and the printed circuit board, including an opening in an area adjacent to the RF circuits, and configured to radiate, through the opening, the magnetic field generated by the RF circuits.

To help reduce the amount of time before a safety power management integrated circuit (PMIC) releases a processing system from a safety state, the safety PMIC includes a first digital circuitry that first configures a voltage threshold comparator and then enables a voltage regulator to provide power to the rest of the PMIC. Additionally, concurrently with the rest of the PMIC powering on, the safety PMIC includes a second digital circuitry that is distinct from the first digital circuitry and that performs a logic built-in self-test (LBIST) for a safety logic circuitry configured to monitor the voltage threshold comparator.

A power management integrated circuit includes a DC-DC converter configured to generate an internal voltage and output an internal power supply voltage based on the internal voltage. The DC-DC converter includes a first switch connected between an external power supply voltage and a second node from which the internal voltage is output, a second switch connected between the second node and a ground, and a third switch connected between the second node and the external power supply voltage through a resistor. When the internal voltage is a normal voltage, the DC-DC converter generate the internal voltage having a level between a first voltage and a second voltage lower than the first voltage by repeatedly turning on and off the first and second switches. When the internal voltage exceeds the first voltage, the DC-DC converter decreases the internal voltage by repeatedly turning on and off the second and third switches.

Systems and techniques for pin cutouts in memory modules (e.g., Dual In-line Memory Modules (DIMMs)) are described. A memory module includes one or more memory integrated circuits mounted on a printed circuit board. The memory module also includes at least one additional component, including, for example, a power manager integrated circuit, buffers, and inductors. The memory module also includes one or more rows of pins to provide an electrical connection to a motherboard. One or more rows include a pin cutout wherein some pins are removed or not placed in the row. The pin cutout allows a component to be mounted on the PCB in the foregone board area.

This invention relates to the field of power management integrated circuit technology, specifically a current-mode step-down DC-DC converter and its control method. The converter includes an internal voltage VCC generation circuit (REG), an oscillation circuit (OSC), a slope compensation circuit (SLOPE), an error amplifier (EA), a sample-and-hold circuit (SAMPLE & HOLD), a PWM module, and a drive circuit (DRIVE). Through this structure and the corresponding control method, this invention can eliminate subharmonic oscillations, making the system more stable across the entire duty cycle range. Simultaneously, it can avoid glitches and remove the minimum duty cycle limitation.

The present invention relates to a memory module having an electronic fuse which protects devices within the memory module by shutting off excessive current or voltage in an electrical overstress condition in which the excessive current or voltage is applied, the memory module comprising: a memory device array composed of a DDR SDRAM; a register clock driver chip which distributes signals received from a memory controller to the memory device array; a power management integrated circuit chip which distributes and supplies input power to components including the memory device array and an RCD; a serial configuration recognition chip which stores initial device information; and an electronic fuse which shuts off the input power when the input power is under electrical overstress, wherein the memory module may further comprise an electronic fuse integrated package in which the register clock driver chip or the power management integrated circuit chip and the electronic fuse are embedded in a single package.

The application discloses a self-powered intelligent clothing system and method based on friction nanogenerator technology, and belongs to the field of flexible electronics and intelligent wearing technology. The system comprises a clothing body, a power generation module, an energy management module, an energy storage module and a functional load module integrated on the clothing body. The power generation module comprises a plurality of friction nanogenerator units for converting mechanical energy of human body movement into electric energy; the energy management module comprises a rectifier circuit and a power management integrated circuit for AC / DC conversion and impedance matching. The energy storage module is electrically connected with the energy management module and is used for storing electric energy. The functional load module is powered by the energy storage module. The application efficiently collects human kinetic energy through the heterogeneous integrated multi-mode TENG, and realizes stable storage by using a special energy management circuit, finally drives the functional load, realizes self-powered and active health intervention of the clothing, and significantly improves wearing comfort and system endurance.

An apparatus includes a plurality of core devices, each configured to operate at a plurality of voltage levels. The apparatus also includes a power management integrated circuit (PMIC) including a plurality of power supplies, each power supply corresponding to one of the voltage levels. A first power supply, corresponding to a first voltage level, is selectively coupled to a first core device configured to operate at the first voltage level. A second power supply, corresponding to a second voltage level, is selectively coupled to a first core device configured to operate at the second voltage level.

The utility model belongs to the technical field of electronic device heat management, disclose a kind of power management integrated circuit device with radiating fin structure, including base, chip main body and lower heat-conducting sheet, chip main body and lower heat-conducting sheet are connected in the top of base, the scheme is through optimizing heat dissipation structure, using the combination of integrally formed lower heat-conducting sheet, radiating fin and upper heat-conducting sheet, the thermal resistance between each component is effectively reduced, the efficiency that heat spreads and releases from chip main body outward is improved, make structure simplify and facilitate installation;Through using heat-conducting film, docking block and serpentine cooling channel etc. Design, further improve heat transfer efficiency and heat dissipation capacity;Through the connection with external cooling liquid circulating system, can actively assist heat dissipation, enhance the thermal stability and reliability under high-power operation, ensure that chip can work stably under high heat flux density condition, with significant heat dissipation performance and structural advantages.

A power management integrated circuit and an operating method thereof are provided. The power management integrated circuit (PMIC) includes a dynamic voltage scaling (DVS) block configured to generate an output voltage signal, and a DVS monitoring block including a DVS monitoring code generator and a safety monitoring unit configured to receive a DVS code and detect an error in the DVS code. The DVS block is configured to generate the output voltage signal based on a DVS code obtained by reflecting a DVS trim code in a DVS regulation code, and the DVS trim code is determined by characteristics of a first digital-to-analog converter (DAC) included in the DVS block. The DVS monitoring code generator is configured to generate a DVS monitoring code obtained by reflecting a DVS monitoring trim code in the DVS regulation code, and the DVS monitoring trim code is determined by characteristics of a second DAC included in the DVS monitoring block.

The present disclosure generally relates to improved wait time notifications from SSDs to host systems. Rather than assuming on when to restart an SSD after an asynchronous event notification (AEN) is sent, issuing a cool-off wait time. When an SSD is overheating, an AEN is sent from the SSD. An AEN may either be a warning event or a critical event. Once the AEN is received, a host may issue a banner with a cool-off wait time. The cool-off wait time is a predetermined time that will begin if the SSD is not detected by host systems. A non-detectable SSD means that the SSD is in a thermal shut down mode, which is initiated by a PMIC. In the thermal shut down mode, the cool-off wait timer will begin at host side. After the time has elapsed the SSD can then be restarted either manually by user or automatically by host.