352 results about "Power management integrated circuit" patented technology

The present invention discloses a boost converter power stage circuit, comprising: an organic light-emitting diode power management integrated circuit unit, a switched capacitor converter, and a boost converter, wherein, a flying capacitor is used to boost the voltage of the inductor to twice the voltage, and then the positive voltage of the output voltage source is boosted, and then use the switched capacitor converter to output the voltage in order to obtain the conversion of the negative voltage.

The invention provides a voltage control circuit and a display device.The voltage control circuit comprises a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit, the power-on reset circuit correspondingly outputs a third level signal or a fourth level signal during power-on or power-off, the comparison circuit compares power supply voltages, and the switch control circuit controls the first switch circuit and the second switch circuit. The switch control circuit correspondingly controls the on-off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit, and the power-off voltage can be detected through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit. When voltage rebound occurs in the power-down process, the first switching circuit can be effectively kept switched off, and abnormal restart of the power management integrated circuit is prevented, so that the problem of picture abnormity or splash screen caused by abnormal power-on of the display panel is effectively prevented, and the display quality and the user experience of the display device are improved.

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

The embodiment of the invention discloses a method and a device for controlling charging, charging equipment and a computer readable storage medium, which are used for performing electrochemical impedance spectroscopy analysis by using a second charging protocol and controlling charging through a power management integrated circuit, so that the precision of the electrochemical impedance spectroscopy analysis can be improved. The method comprises the steps of receiving a first communication frame sent by power supply equipment under the condition of detecting that the power supply equipment is inserted and charging is performed by using a first charging protocol; when it is determined that the second charging protocol is used for charging, a first instruction is sent to the power supply equipment according to the first communication frame; acquiring a plurality of first voltage values and a plurality of first current values for charging by using a second charging protocol, wherein the plurality of first voltage values form a first voltage sequence and the plurality of first current values form a first current sequence; and under the condition that at least one of the first voltage sequence and the first current sequence meets a step response condition, calculating a first battery impedance value, and sending a second instruction to the power supply equipment.

An electronic device includes: an interface; charging circuitry; a power management integrated circuit (PMIC); a processor; a plurality of battery cells comprising a first battery cell and a second battery cell; and switching circuitry to control an electrical connection of the plurality of battery cells, the switching circuitry being connected to the first node and the second node. The switching circuitry includes: a first switch to establish an electrical connection between the first node, and an anode of the first battery cell, based on a control signal received from the processor; a diode including an anode connected to a cathode of the first battery cell, and a cathode connected to an anode of the second battery cell; and a second switch to establish an electrical connection between the second node, and the anode of the first battery cell, in another state different from a state.

An electronic device including an organic light emitting display device is provided. The electronic device includes the organic light emitting display device and a display power management integrated circuit (PMIC). The organic light emitting display device includes a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels, and a display driver IC (DDI) for driving the display panel. The display PMIC includes a first regulator that outputs a first voltage changed in magnitude from an input voltage input to the display PMIC, and a second regulator that outputs a second voltage phase-inverted and changed in magnitude from the input voltage.

The invention relates to the technical field of integrated circuit power supply, in particular to a modular multi-stage distributed power supply architecture and method for a whole wafer computing system, the architecture comprises a computing wafer, a power supply module, a bearing substrate and an integrated heat dissipation system, the computing wafer is integrated with various computing units with different voltage requirements, and the power supply module is connected with the integrated heat dissipation system. The power supply module is integrated with the computing wafer through a high-density interconnection interface, a multi-stage power supply topology is adopted in the power supply module, the power supply module comprises a first-stage central power management unit, a second-stage distributed voltage regulation unit array, a high-density embedded capacitor array and a global multi-domain power management integrated circuit, and the bearing substrate is used for bearing related parts. The integrated heat dissipation system carries out differential heat dissipation according to different heat dissipation densities. According to the invention, global optimization of power supply efficiency, precision and thermal management can be realized, and the complex power supply problem of the whole wafer system can be effectively solved.

The utility model provides a voltage detection circuit of an embedded mainboard, comprising a power management integrated circuit PMIC, a micro control unit MCU, a watchdog circuit and a micro processing unit MPU. The power management integrated circuit PMIC is connected with the micro control unit MCU and the micro processing unit MPU to send the voltage generated after startup to the micro control unit MCU and the micro processing unit MPU. An IO port of the micro control unit MCU is connected to the watchdog circuit, and an output end of the watchdog circuit is connected to the micro processing unit MPU. When the micro control unit MCU detects various voltages generated by the PMIC, the IO port connected to the watchdog outputs a low level, the watchdog circuit is in a reset state and controls the micro processing unit MPU to be in a reset state; when the micro control unit MUC completes the detection of all voltages and the detection is normal, the IO port connected to the watchdog outputs a high level to drive the micro processing unit MPU to start normally, thereby ensuring the effectiveness and consistency of the normal startup of the embedded system CPU.

A power management apparatus operable with multiple configurations is disclosed. In embodiments disclosed herein, the power management apparatus can be configured to concurrently generate multiple modulated voltages based on a configuration including a single power management integrated circuit (PMIC) or a configuration including a PMIC and a distributed PMIC. Regardless of the configuration, the power management apparatus employs a single switcher circuit, wherein multiple reference voltage circuits are configured to share a multi-level charge pump (MCP). As a result, it is possible to reduce footprint of the power management apparatus while improving isolation between the multiple modulated voltages.

A power management integrated circuit includes an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage, a self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition for the internal output transistor and providing a gate voltage to a gate terminal of the internal output transistor and a clamp circuit outputting, as the internal output voltage, a first clamp voltage having a uniform level in a first overvoltage clamp mode and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamp circuit outputs the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode.

The invention provides a compensation output circuit, a driving circuit of a display panel and a display device.The compensation output circuit comprises a hysteresis circuit, a signal amplification circuit and a compensation circuit, and the hysteresis circuit delays first common electrode voltage output by a power management integrated circuit; the first common electrode voltage and the second common electrode voltage are output synchronously, meanwhile, the signal amplification circuit carries out signal amplification on the first common electrode voltage output in a delayed mode and outputs target voltage to the compensation circuit, and the compensation circuit generates compensation voltage according to the target voltage and the second common electrode voltage obtained through feedback. The first common electrode voltage and the second common electrode voltage are synchronously output to the compensation circuit for compensation processing through the hysteresis circuit and the signal amplification circuit, so that generation of voltage spikes and startup splash screen are avoided, and the display effect is improved.

The invention discloses a voltage and current detection device for a power management integrated circuit, and relates to the technical field of voltage and current detection.The voltage and current detection device comprises a placement plate and further comprises a dismounting device.An installation frame is fixedly installed at the top of the placement plate, and voltage and current detection equipment is arranged in the installation frame; a mounting groove is formed in the front side of the voltage and current detection equipment, the dismounting device comprises a speed reduction frame, a speed reduction plate, a speed reduction hole, a speed reduction rod, a mounting plate, a positioning groove, a fixing rod and an L-shaped plate, and the mounting plate slowly moves upwards to drive the voltage and current detection equipment to move upwards and eject the voltage and current detection equipment; limiting of the voltage and current detection equipment is recovered through the L-shaped plate, installation of the voltage and current detection equipment is completed, the complexity of technicians during operation can be reduced through the simplified disassembly and installation process, and therefore the continuity of current and voltage detection is improved.

A disclosed power management integrated circuit includes (1) a voltage source electrically coupled to a voltage output of a portion of a processing unit, (2) a prediction circuit electrically coupled to the voltage source, the prediction circuit comprising an artificial neural network (ANN) model trained to predict an inductor current based on a voltage received via the voltage source, and a management circuit configured to manage power usage of the processing unit based on a predicted inductor current received from the prediction circuit, the predicted inductor current predicted via the ANN model based on the voltage received via the voltage source. Various other apparatuses, systems, and methods for improving processor power management via ANNs are also disclosed.

The invention provides a power supply output circuit and a display device, the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power supply output circuit, a first detection circuit, a second detection circuit and a logic control circuit, during dormancy, the comparison circuit stops outputting a first wake-up signal, and the power supply output circuit stops outputting a starting voltage; when the first detection circuit and the second detection circuit stop working, the power consumption of the display device during dormancy is reduced, and when the display device is awakened and low-voltage rebound of the power supply voltage or the power supply voltage occurs, the logic control circuit does not receive the first awakening signal, the second awakening signal and the third awakening signal at the same time, the output of the first enable signal is stopped; and the power management integrated circuit does not work, so that the problems of circuit damage and picture abnormity caused by low-voltage rebound are prevented, and the working safety and the display effect of the circuit are improved.

A display device includes a display panel, a display panel driving circuit, and a power management integrated circuit (PMIC) configured to generate a driving voltage, receive driving setting data from a timing controller, store a driving hexadecimal value corresponding to the driving setting data in a first internal register, and determine a voltage level of the driving voltage based on the driving hexadecimal value. The PMIC divides the driving hexadecimal value into an upper decimal value and a lower decimal value, derives a result decimal value by applying the upper decimal value and the lower decimal value to a first authentication formula, generates a result hexadecimal value based on the result decimal value, compares an authentication hexadecimal value corresponding to the authentication data received from the timing controller with the result hexadecimal value, and selectively operates in a normal mode or a protection mode based on a result of the comparison between the authentication hexadecimal value and the result hexadecimal value.

An electronic device includes: an antenna, a PAM including a PA configured to amplify a transmitting signal and a protection circuit, a PMIC configured to supply voltage to the PA, and at least one processor is configured to: provide a first signal, to a NAND gate in the protection circuit, provide to a AND gate in the protection circuit, a second signal indicating a result of a logical operation between the first signal and a bias enable signal for the PA, provide to the AND gate, a third signal indicating whether the transmitting signal is input to the PAM, provide to a switching circuit, a fourth signal indicating a result of logical operation between the second signal and the third signal, identify whether to apply a bias voltage to the PA based on the fourth signal, and transmit the transmitting signal, to the external electronic device, via the antenna.

The utility model relates to the technical field of charging circuits, in particular to a small-capacity battery adjusting protection circuit, which is used for protecting a rechargeable battery when the rechargeable battery is connected to a charging device for charging and comprises a CPU (central processing unit) module, a charging and discharging switching control circuit and a power management integrated circuit. The power management integrated circuit is arranged between the charging device and the rechargeable battery, and the output end of the charging device is electrically connected with the input end of the power management integrated circuit; through the cooperation of the power management integrated circuit, the CPU module and the charging and discharging switching control circuit, the battery state can be accurately monitored in real time, and the over-discharging and over-charging phenomena of the rechargeable battery are effectively avoided, so that the problem of swelling of the rechargeable battery is solved, the service life of the rechargeable battery is prolonged, and the safety performance of equipment is remarkably improved. The battery management efficiency is optimized, more stable and reliable equipment use experience is provided for a user, and meanwhile the battery management system is simple in structure and low in manufacturing cost.

A display device comprises a display panel, a power management integrated circuit, a source electrode driving circuit and a common voltage module located outside the display panel and the power management integrated circuit. The source electrode driving circuit is electrically connected with the display panel and the power management integrated circuit respectively; the common voltage module is used for providing a common voltage signal for a common electrode of the display panel, and the common voltage signal and a shell of the display device are equipotential; the power management integrated circuit is used for providing a positive voltage source and a negative voltage source for the source electrode driving circuit; the source electrode driving circuit is used for generating a positive-polarity or negative-polarity analog data signal of the display panel, a power supply used by the positive-polarity analog data signal is the positive voltage source, and a power supply used by the negative-polarity analog data signal is the negative voltage source.

The invention discloses a display device and a control method thereof, and relates to the technical field of display. The method comprises the following steps: in response to a startup instruction, refreshing a picture required to be displayed by a display panel according to a first refresh rate; and in response to meeting the target condition, refreshing a picture required to be displayed by the display panel according to a second refresh rate, wherein the first refresh rate is smaller than the second refresh rate. According to the embodiment of the invention, a relatively small refresh rate is adopted in the startup process, the charging time of the thin film transistor in the startup process can be prolonged, and particularly for a low-temperature scene, the thin film transistor can be ensured to be normally started by prolonging the charging time, so that the display device is ensured to be normally started. Moreover, a temperature compensation circuit does not need to be introduced to compensate the grid conduction voltage of the thin film transistor, the problem that the display device cannot be normally started in a low-temperature scene can be solved based on the existing power management integrated circuit, and the cost of the display device is effectively saved.

A circuit board apparatus employing a stacked circuit board and with inductor (s) for routing power from a power management integrated circuit (IC) (PMIC) to a secondary circuit board, and related methods of manufacture. The inductor (s) is coupled in a first vertical direction between the first circuit board and the second circuit board as part of a power routing path between the PMIC on the first circuit board and the second electronic component (s) of the second circuit board. In this manner, the PMIC may be shared between the first circuit board and the second circuit board to manage power signals provided to the first electronic component (s) and the second electronic component (s) of the first circuit board. The inductor (s) may also be strategically positioned to provide a shorter power signal routing path to reduce or avoid power performance issues with a reduced impedance between the PMIC and the second electronic component (s).

An apparatus has a power management integrated circuit (PMIC) comprising a number of power supplies. The apparatus also has a power multiplexor coupled to each of the power supplies. The apparatus still further has a number of core devices. At least one of the core devices is coupled to the power multiplexor to receive power from at least one of the power supplies. The apparatus has a machine learning model configured to control selection of the power supply (ies) based on current utilization of each of the power supplies, and an amount of current consumed by the core device(s).

In an aspect, an integrated circuit (IC) package includes a package substrate including at least a first power node and a second power node; an interposer on the package substrate; and an IC die on the interposer. The interposer may include a dielectric layer and a power management integrated circuit (PMIC) embedded in the dielectric layer, where the PMIC includes a third power node and a fourth power node, and the third power node may be electrically coupled to the first power node. The IC die may include a fifth power node and a sixth power node, where the fifth power node may be electrically coupled to the fourth power node, and the sixth power node may be electrically coupled to the second power node.

Some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. The semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. The discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. During a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.

A multi-power management integrated circuit (PMIC) with a shared output is disclosed herein. More specifically, two or more PMICs can generate a shared output while balancing the current provided by the PMICs without being affected by device and component mismatches and inter-component variations. This balancing is accomplished by providing a current feedback loop and a shared voltage loop to each PMIC when multiple PMICs are active. When only a single PMIC is active, a switch deactivates the shared voltage feedback loop and activates a local voltage feedback loop. The use of multiple PMICs enables higher supply voltages to be provided to power amplifiers in a transmission chain to meet the requirements of emerging wireless standards while also maintaining better efficiency of the transmission chain.

The present invention proposes a voltage control circuit and a display device, wherein the voltage control circuit includes a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit. The power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when the power is turned on or off. The comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly. The switch control circuit controls the on and off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit. Through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected. When a voltage rebound occurs during the power-off process, the first switch circuit can be effectively kept off to prevent the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from abnormally powering on and causing screen abnormalities or flickering problems, thereby improving the display quality and user experience of the display device.

A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

The utility model discloses an RVC camera module and a dynamic vehicle auxiliary line system. The RVC camera module comprises a lens, a sensor, a graphic signal processor ISP, a serializer Serdes, a POC circuit module, a connector and a power management chip PMIC (Power Management Integrated Circuit), the lens is in signal connection with the sensor; the sensor is in signal connection with the image signal processor ISP; the image signal processor ISP is in signal connection with the serializer Serdes; the serializer Serdes is in signal connection with the POC circuit module and the connector respectively; the POC circuit is in signal connection with the power management PMIC; the power management PMIC supplies power to the sensor, the image signal processor ISP and the serializer Serdes respectively. According to the utility model, the dynamic vehicle auxiliary line can be generated in the camera, so that the overall equipment cost of the reversing image system is reduced.

Systems and methods for front-end linearization using information from a baseband circuit are disclosed. In one aspect, a baseband circuit provides information to a front-end module that uses the information to adjust operating parameter settings such as how an analog predistortion (APD) circuit or power management integrated circuit behaves to provide more linear operation of the front-end module across the frequencies of interest. In exemplary aspects, the front-end module may receive raw information from which the front-end module determines what changes should be made. In alternate exemplary aspects, the baseband circuit provides instructions or coefficients that are then used by the front-end module to make the changes. In either event, the front-end module may optimize operation to reduce power consumption and provide more linear operation so that the transceiver may better operate within the parameters of a given wireless protocol.

An example method includes, responsive to determining that a button of a mobile computing device has been pressed for longer than a first amount of time, resetting a power management integrated circuit (PMIC); responsive to determining that the button of the mobile computing device has been pressed for longer than a second amount of time that is longer than the first amount of time, electrically disconnecting, at a first time, power sources from the mobile computing device; and electrically reconnecting, at a second time that is after the first time, the power sources to the mobile computing device.

A multi-mode power management integrated circuit (PMIC) is provided. Specifically, the multi-mode PMIC can be provided in a wireless communication device to generate an output voltage, which can be an envelope tracking (ET) voltage or an average power tracking (APT) voltage, for amplifying a radio frequency (RF) signal. According to an embodiment disclosed herein, the PMIC replaces a conventional all-analog control circuit with a multi-input hybrid control circuit that includes both analog and digital circuitries. By incorporating the digital circuitry to perform certain processing tasks digitally, it is possible to improve efficiency and reduce the footprint of the multi-mode PMIC.