283 results about "Power routing" patented technology

A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.

A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.

A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps. Preferably, the conductor plate is composed of a multilayer structure of two or more layers, and each conductor plate is used in power-supply wiring or ground wiring.

A system for encouraging the use of renewable energy sources and suitable for the conservation of energy resources through the efficient management of energy storage and delivery includes connections to a power source, an energy storage subsystem, and a power grid. The system includes a power routing subsystem coupled to the source and grid, and adapted to operate in a bypass mode, in which energy is transferred from the source to the grid. The system includes a conversion subsystem coupled to the routing and storage subsystems, and switchable in substantially real-time between a storage mode, in which energy is transferred from the routing to the storage subsystem, and a generation mode, in which energy is transferred from the storage to the routing subsystem for delivery to the grid. The system also includes a controller for directing the modes based at least in part on a market factor.

A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional signals allow optimization of power distribution for powering attached devices, and for detecting and handling illegal connection configurations. In another approach, improvements are realized through use of alternative signaling techniques which eschew reflective and high-speed common-mode signaling. Described are various configuration, media and signal-protocol combinations, including implementations containing embedded hubs. Methods ensuring reliable system behavior are also described, including determination of extension path delay and use of topology-enforcement hubs. In other approaches, further improvements are realized by allowing information exchanges to take longer than the nominal timeout period, or by allowing host requests to be delayed for transmission until the extended bus is available for use.

A semiconductor integrated circuit having a substantially rectangular standard cell divided by first borderlines opposed to other standard cells longitudinally adjacent to the standard cell and second borderlines opposed to other standard cells laterally adjacent to the standard cell, the standard cell has: a p-type MOS transistor having first diffused regions and a first gate electrode; an n-type MOS transistor having second diffused regions and a second gate electrode with STI disposed for device isolation between the n-type MOS transistor and the p-type MOS transistor substantially in parallel with the first borderlines; dummy p-type MOS transistors having third gate electrodes disposed on the second borderlines so as to be adjacent to the first diffused regions of the p-type MOS transistor, the third gate electrodes being connected to power supply wiring so as to turn off the dummy p-type MOS transistors; and dummy n-type MOS transistors having fourth gate electrodes disposed on the second borderlines so as to be adjacent to the second diffused regions of the n-type MOS transistor, the fourth gate electrodes being connected to ground wiring so as to turn off the dummy n-type MOS transistors.

For a display device having a solar cell and a power buffer for keeping stored electric power, a display system which has a low-power drive mode, self-contained power and no need for recharging or power wiring is provided. The display system includes a solar cell using a thin-film semiconductor, a power storage element for temporarily storing the produced power, a driving circuit, a matrix display unit, a display rewrite instruction unit for inputting screen rewrite and a control circuit and starts rewriting a display when power sufficient to rewrite an image screen is stored in the solar cell. The display device having remarkable portability and no limited battery life, which controls a display mode depending on the power produced by the solar cell, can display even when power generation is low and allows self-contained power even if the storage element has a small capacity, can be obtained.

A safety device for regulating electrical power to a cooking appliance, comprising a control module having a power routing means, a power supply means, a load current sensing means for detecting a load current to the cooking appliance and a power relay means for controlling the electrical current to the cooking appliance, and a sensor module located adjacent to the cooking appliance for observation by an appliance operator and connected to the control module. The sensor module governs the production of the electrical current to the cooking appliance, and has a monitoring means, a distance sensing means, a timer means for showing elapsed cooking time, and a light emitting means. The monitoring means is responsive to outputs of the distance sensing means and includes a timer assembly programmed to a predetermined period of time for responding to the distance sensing means detecting the presence of the appliance operator.

Provided is a display device including: a substrate; a plurality of display elements defining a display area on the substrate and each including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode; a power supply wiring disposed outside the display area; an organic insulating layer on the power supply wiring and having an opening exposing the power supply wiring; a power supply electrode layer partially disposed on the organic insulating layer and including a plurality of holes over the organic insulating layer, wherein a first portion of the power supply electrode layer overlaps the power supply wiring and a second portion of the power supply electrode layer overlaps the opposite electrode; a plurality of protrusions spaced apart from each other and respectively covering at least some of the plurality of holes; and an encapsulation layer covering the plurality of display elements.

The invention provides a control method for low power consumption of a network camera supplied by a battery. The method includes following steps: firstly, a power supply module and a master control module are in a standby mode, a sensing module is in a normal work mode, and other modules are in a power-down mode; secondly, when the sensing module detects the invasion of someone, the master control module switches the standby mode to a work mode, and the other modules are turned on; thirdly, video signals are acquired by a video acquisition module, and audio signals are simultaneously acquired by an audio acquisition module; fourthly, the audio and video signals are transmitted to a local storage module via the master control module, or the audio and video signals are sent to a cloud platform via a wireless transmission module; and fifthly, recording is realized via a cloud server and warning information is forwarded to an APP of a user mobile terminal. According to the control method, the problem of power supply wiring of the household network camera is solved, the average power consumption of the equipment is reduced via the reduction of the power consumption in a non-usage period of the camera, and the service lifetime of the battery is extended via process optimization.

A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power wiring regions are formed with reference to grids that exist from a cell edge every basic cell width in the X-direction. Input signal terminals and an output signal terminal are each arranged so as to include at least one wiring connecting portion outside the auxiliary power wiring regions. This makes it possible to wire wiring other than signal wiring in the auxiliary power wiring region. When a functional circuit block is constructed by arranging unit cells in a matrix, auxiliary power wiring regions are formed at a pitch of the basic cell width, through the functional circuit block in the Y-direction.

An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.

To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized.

Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.

A computer-aided design method of an integrated circuit includes: calculating current dissipation consumed by logic elements, in a ladder network embracing a plurality of current paths connected between subject first- and second-potential-level power supply wiring; analyzing a tolerable electro-migration current of the subject first-potential-level power supply wiring; analyzing an interval voltage drop between a control point and a specific position on the subject first-potential-level power supply wiring; and comparing a summation of through-currents flowing the logic elements from the control point to the specific point, with the tolerable electro-migration current, and comparing the interval voltage drop with a tolerable voltage drop to determine an optimum location of a via configured to supply power from the subject first-potential-level power supply wiring to the logic elements.