65 results about "Power routing" patented technology

A base plate system includes a base plate with a surface to support an accessory and a power box mounted to the base plate. The power box includes at least one power outlet. An electrical connector connects the power box to a power source to be able to provide power to the accessory via the at least one power outlet.

A power routing system includes a base plate having a surface to support an accessory, a power source configured to provide power to the accessory, the power source having at least one first power outlet, and a power connection member mounted to the base plate. The power connection member includes at least one second power outlet. An adaptor is associated with the power source such that an electrical connector can connect the at least one first power outlet to the power connection member to power the accessory via the at least one second power outlet.

An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source / drain region on the fin-type active region, a first conductive plug arranged on the source / drain region and electrically connected to the source / drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.

The disclosure provides a computing power providing method, a computing power requesting method, a tunnel endpoint device, a computing power system and a storage medium, wherein the computing power providing method comprises: a first tunnel endpoint device sends a general routing encapsulation (GRE) protocol computing power notification message to a second tunnel endpoint device, the information carried by the GRE protocol computing power notification message comprises computing power information, and the first tunnel endpoint device provides computing power service based on a computing power service request message sent by the second tunnel endpoint device. The disclosure transmits computing power information through a GRE protocol message, so that the tunnel endpoint device performs computing power scheduling according to the computing power information carried by the GRE protocol message, meets the computing power scheduling demand in the GRE network, determines the computing power routing according to the computing power information in the GRE network, realizes the rationalization of computing power scheduling, effectively saves network resources, and improves the use experience of users.

The application provides a computing power network state updating method and device, equipment and a storage medium, relating to the technical field of computers, which comprises generating a computing power state table through a self-defined routing strategy algorithm in response to service registration information sent by an edge management system; periodically acquiring updated computing power state information of a computing service node in the edge management system according to the Internet Protocol address of a computing power routing exit node, updating the computing power state table according to the updated computing power state information to obtain an updated computing power state table; determining at least one computing power routing exit node corresponding to a service request according to the updated computing power state table in response to a service request sent by a client; sending a network state query measurement message to the at least one computing power routing exit node to acquire an updated network state table, updating a local network state table according to the updated network state table to obtain an updated network state table.

This invention relates to the field of power Internet of Things and smart distribution network monitoring technology, and discloses a smart scheduling system for highway charging resources. The system includes: a dual-end source-side three-level rectification and busbar construction module, which constructs a bipolar three-wire DC transmission busbar between two service areas; a cross-regional transmission line impedance identification and status sensing module, which calculates the distributed inductance and capacitance parameters of long cables in real time; a terminal multi-port adaptive power routing module, which physically selects the voltage level to suit vehicle demand through a switch matrix; and a distributed parameter resonance locking and drive control module, which locks the operating frequency to the line's intrinsic resonant frequency and uses distributed parameters to achieve soft switching. This invention achieves long-distance energy exchange and voltage adaptive matching through cross-regional interconnection and multi-level routing, and transforms line parasitic parameters into resonant elements, reducing transmission losses.

Integrated circuit devices with memory circuits formed between topside BEOL (back end of line) metal layers are described. The memory circuits include active regions and source / drains that can be formed in the spaces between topside metal layers. In certain instances, the memory circuits are formed in between metal layers furthest away from substrate. The memory circuits connect to signal and power routing either above or below the transistors. In various instances, the active regions of the memory circuits are formed by thin channel materials.

This invention discloses a boundary computing power routing scheduling method and system based on OAM information publishing. The method includes: acquiring a computing request to be processed and node awareness data sent by multiple computing power routes; the computing power routes are communicatively connected to multiple computing power nodes and determine the node awareness data based on communication interaction; determining the scheduling route corresponding to the computing request from the multiple computing power routes based on the node awareness data; determining the node scheduling strategy corresponding to the scheduling route based on the computing request and the node awareness data corresponding to the scheduling route; generating an OAM information message based on the computing request and the node scheduling strategy, and sending the OAM information message to the corresponding computing power node through the scheduling route. Therefore, this invention can achieve accurate task scheduling based on real-time awareness data, thereby effectively improving the processing efficiency and response speed of computing requests among multiple computing power nodes.

Integrated circuit devices with power switch circuits formed between topside BEOL (back end of line) metal layers are described. The power switch circuits include active regions and source / drains that can be formed in the spaces between topside metal layers. In certain instances, the power switch circuits are formed in between metal layers furthest away from substrate. The power switch circuits connect to control signal and power routing either above or below the transistors. In various instances, the active regions of the power switch circuits are formed by thin channel materials.

A method includes forming a package component, the package component comprising: an interposer comprising a first redistribution structure; integrated circuit dies attached to the first redistribution structure; forming a package substrate, forming the package substrate comprising: forming a second redistribution structure and a third redistribution structure over opposite sides of a substrate core; singulating the substrate core to form component substrates; attaching a first component substrate and a second component substrate to a carrier, the first component substrate and the second component substrate being laterally displaced by a gap; and forming a bonding layer over the first component substrate and the second component substrate; attaching the package component to the package substrate; and forming external connectors over the package substrate, the external connectors being configured to electrically couple a signal routing, a power routing, or a ground routing of the integrated circuit dies to an another package component.

The invention provides a computing power route notification method, device and equipment, and the method comprises the steps: receiving a first service message which comprises a first service feature; if a flow table matched with the first service feature does not exist and a first mapping table item matched with the first service feature exists in a mapping table, a second type of computing power routing is sent to an exit node of the computing power routing, and the second type of computing power routing comprises a first CS-ID corresponding to the first service feature; receiving a third type of computing power routing sent by the computing power routing exit node, wherein the third type of computing power routing comprises the computing power magnitude of each computing power service node in the plurality of computing power service nodes; a target computing power service node is selected based on the computing power magnitude of each computing power service node, a flow table matched with the first service feature is established, and the flow table comprises path information; and sending the first service message to the target computing power service node through the path information. According to the scheme, the utilization efficiency of computing resources is improved.

The application provides a computing power routing method for AGI reasoning network, relates to the field of AGI computing power routing, and comprises the following steps: collecting physical operation state parameters of different types of nodes in the AGI reasoning network, constructing a hot area distribution, and establishing an association with a reasoning stage; outputting a physical bearing state set and a hot drift association result; statistically analyzing resource occupation characteristics of the reasoning stage and matching the resource occupation characteristics with the hot area distribution; reconstructing physical pressure and generating a bearing decay mark; outputting a physical constraint reasoning set and a bearing change result; identifying a reasoning stage to be released, matching a migration target node, completing context migration, and generating a reasoning release constraint; outputting a physical constraint routing result and a reasoning stage release mapping set; determining whether the node is out of a hot accumulation state and restores bearing capacity; executing a reasoning stage backflow and updating a physical constraint routing; and outputting an AGI reasoning computing power routing result, so that the AGI reasoning efficiency and stability are improved, and the computing power resource utilization rate is significantly improved.

The invention relates to the technical field of electrified railway traction power supply systems, in particular to a railway power regulator integrated with cooperative energy routing, which adopts a double-direct-current bus framework, and the overall topology is divided into three core layers, namely a power routing layer, an isolation conversion layer and a source storage interface layer; a control method of a railway power regulator integrated with cooperative energy routing comprises the following steps: operation state sensing: based on a distributed data acquisition architecture, acquiring parameters at a frequency of 10kHz, preprocessing acquired data, and constructing a real-time state matrix; energy flow priority self-adaptive decision making: based on the real-time state matrix, performing intelligent switching among three operation modes by adopting a decision making mechanism combining hierarchical threshold judgment and multi-objective optimization; and dynamic coordination control and smooth switching: according to the operation mode determined by the decision, calling a corresponding core control algorithm to execute control, and realizing seamless switching between modes through a weighted smoothing strategy based on a Sigmoid function to suppress voltage impact and power abrupt change.

The invention is suitable for the technical field of processors, and particularly relates to a self-adaptive power supply wiring method and system of a processor and related equipment. According to the invention, multiple power supply network schemes are established according to the unit density of different areas of the processor chip; selecting one of a plurality of power supply network schemes as a reference scheme, and preliminarily placing units of the processor chip based on the reference scheme; performing regional division on the initial power supply network based on the size of the reference scheme; counting the number of standard units or the equivalent unit area in each physical area unit and calculating the corresponding unit density to obtain the area unit density corresponding to the plurality of physical area units; and adjusting the layout and wiring of the physical region units into a corresponding power supply network scheme based on the density of the region units, so as to realize the self-adaptive power supply wiring of the processor chip. Compared with the prior art, winding resources of areas with different densities can be saved, and the occupation of a power supply network on wiring tracks and metal resources is remarkably reduced.

Provided is a control board for a vehicle-mounted electric compressor, which can suppress or eliminate an increase in electromagnetic noise when a capacitor unit is not connected between a power supply wiring and a ground wiring. The present invention is provided with: a separation pattern (43) having a power supply pad (46), a ground pad (47), and a GND pad (48), the separation pattern (43) being separated from a power supply wiring (27), a GND wiring (28), and a ground wiring (37); a power source-side pad (51) provided on the power source wiring (27); a ground-side pad (52) provided on the ground wiring (37); and a GND-side pad (53) provided on the GND wiring (28), the power supply pad (46) being connectable to the power supply-side pad (51) by means of a solder (61), the GND pad (48) being connectable to the GND-side pad (53) by means of a solder (61), and the ground pad (47) being connectable to the ground-side pad (52) by means of a capacitor unit (38A).

The present application provides a computing power routing advertisement method and apparatus, and a device. The method comprises: receiving a first service packet, the first service packet comprising a first service feature; if there is no flow table matching the first service feature, and a mapping table comprises a first mapping entry matching the first service feature, sending a second-type computing power route to a computing power routing egress node, the second-type computing power route comprising a first CS-ID corresponding to the first service feature; receiving a third-type computing power route sent by the computing power routing egress node, the third-type computing power route comprising a computing power metric value of each computing power service node among a plurality of computing power service nodes; selecting a target computing power service node on the basis of the computing power metric value of each computing power service node, and establishing a flow table matching the first service feature, the flow table comprising path information; and sending the first service packet to the target computing power service node by means of the path information. The solution of the present application improves the utilization efficiency of computing resources.

A liquid discharge apparatus includes a head including a discharge section that discharges liquid by a drive signal, and a drive circuit substrate coupled to the head, in which the drive circuit substrate includes a drive circuit that outputs the drive signal, a first power supply wiring that couples a power supply circuit and the head, and a first overcurrent protection circuit provided on the first power supply wiring, the first overcurrent protection circuit has a first mode that puts the power supply circuit and the head in a conductive state and a second mode that puts the power supply circuit and the head in a non-conductive state, the first overcurrent protection circuit switches from the first mode to the second mode when a current flowing through the first power supply wiring is equal to or higher than a predetermined value.

The application provides a computing power routing method and device, a node device and a network device. The method comprises: obtaining first information, wherein the first information comprises first metric information related to computing power resources; dividing a plurality of nodes in a network into a plurality of routing planes according to the first information, wherein each routing plane corresponds to a routing reference information; and transmitting plane information of the plurality of routing planes and the corresponding routing reference information to the network. By publishing the first information in the network, the first information comprising the first metric information related to the computing power resources, the routing nodes in the network can divide the plurality of nodes in the network into a plurality of routing planes according to the obtained first metric information, and can provide end-to-end differentiated services for users with diversified computing power requirements.

The invention relates to the technical field of network resource scheduling and artificial intelligence, and provides a computing power routing method based on multi-intelligence collaboration, which comprises a satellite, an unmanned aerial vehicle, a ground base station, a user terminal and other multi-layer heterogeneous nodes. Network nodes are dynamically networked through a wireless link, and node movement, topology change and multi-hop communication are supported. Each node has certain computing power and storage capability, and can cooperatively complete data processing and task distribution. The core routing nodes are deployed in a network backbone in a distributed manner and are responsible for intelligent routing and resource scheduling. The system integrates key technologies such as link quality quantification, distributed election, reinforcement learning of intelligent agents, virtual wireless interface simulation, flow control and route issuing. The method provided by the invention supports large-scale simulation, dynamic routing optimization and computing power resource collaboration, is suitable for scenes such as satellite internet, unmanned aerial vehicle clusters, emergency communication and intelligent transportation, and realizes wide-area, intelligent and high-reliability communication and computing power services.

Chip packages are described herein that includes integrated passive devices embedded in a core of a substrate of the chip package, such as a package substrate or an interposer, that shield routings coupled to inductors from adjacent through-substrate conductive paths (e.g., vias). In one example, a chip package includes an integrated circuit (IC) die mounted to a substrate. A core of the substrate has a plurality of inductor routing vias, a plurality of signal transmission vias, and a plurality of ground and power routing vias. A first integrated passive device (IPD) is disposed in the core and separates at least one of the plurality of inductor routing vias from an adjacent via, the adjacent via being one of the plurality of signal transmission vias or one of the plurality of ground and power routing vias.

This invention discloses a distributed multi-user computing power routing strategy formulation method for space-based computing power networks. The method involves: first, constructing a satellite element network composed of satellites and functional modules; then, modeling user services as a Directed Acyclic Graph (DAG) model, and determining the computing strategy by mapping the DAG to the corresponding functions in the space-based computing power network; next, modeling the satellite computing power resource allocation problem when different users initiate services on different access satellites as a distributed potential game process, enabling the formulation of multi-user computing power routing strategies with minimal user losses; finally, using a distributed self-learning iterative algorithm, solving the mapping strategy of the Nash equilibrium point, and using this strategy as the optimal computing power routing strategy in the final space-based computing power network. This invention can connect satellite computing power, realize the scheduling of satellite computing power resources, and solve the problem of computing power resource preemption and conflict in multi-user, multi-task access satellite computing power networks.

The invention discloses a satellite network computing power routing method suitable for multi-stream cooperative computing, and mainly solves the problems that in the prior art, transmission and computing resource scheduling are separated, and multi-stream competition lacks global coordination, so that the overall task completion time delay is high. According to the implementation scheme, the method comprises the following steps: discretizing a physical time-varying satellite network topology into a plurality of time slices along a time dimension, and constructing a satellite network time expansion graph; a transmission path is planned for each cooperative node on the premise that all data flow bandwidths are met, the total time from the beginning of transmission of a first data packet to the completion of transmission of a last data packet is minimized, and the optimal transmission time slot number and a corresponding path set are output; and on the basis of the time expansion graph and the transmission path set, calculating node idle time of each to-be-scheduled data stream is evaluated in real time, the minimum data stream is selected for priority scheduling, and the optimal total task completion time and a transmission and calculation resource scheduling scheme of each data stream are output. According to the method, the total completion time delay of the multi-stream cooperative computing task can be remarkably reduced, the satellite network computing power resource utilization rate is improved, and the method can be used for multi-stream cooperative task routing planning.

Embodiments of the present disclosure provide a packet forwarding method and apparatus. The method comprises: receiving a service identification table generated on the basis of service forwarding types and service identifiers and sent by a control plane; receiving a computing power request packet sent by a terminal; on the basis of a service identifier in the computing power request packet, matching a service identifier in the service identification table; and on the basis of the matching result, performing general routing and forwarding or computing power routing and forwarding on the computing power request packet. By means of the present disclosure, the problems of the high intrusiveness and high resource overhead of computing power routing systems in the related art is solved.

The present disclosure relates to the field of semiconductor, and discloses an internal power supply structure, a semiconductor device and an internal power supply monitoring method. The internal power supply structure comprises a power supply generation circuit, an internal power supply wiring, a first switch circuit, an internal power supply monitoring wiring and a pad. The power supply generation circuit is coupled with the internal power supply wiring at an output end and is configured to generate an internal voltage; the internal power supply wiring is coupled with the internal power supply monitoring wiring through the first switch circuit and is configured to transmit the internal voltage; and the internal power supply monitoring wiring is coupled with the pad and is configured to transmit the internal voltage to the pad when the first switch circuit is turned on. In this way, the internal voltage is led out to the pad when the first switch circuit is turned on, so as to facilitate monitoring of the internal voltage generated by the power supply generation circuit. When the first switch circuit is not turned on, the internal voltage is prevented from being transmitted to the internal power supply monitoring wiring, interference possibly caused by the internal power supply monitoring wiring is eliminated, and inaccurate internal voltage is avoided.

An apparatus includes a package. The package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of bump interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects, the plurality of pillar interconnects being in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of bump interconnects; and a plurality of sidewall interconnects, the plurality of sidewall interconnects being coupled to the encapsulation layer and the metallization portion.

The application discloses a computing power routing method for a white box switch. The application aims at the basic function of a network switch, adds a computing power routing module, and realizes a routing mechanism based on computing power optimization. First, the state of a network card is listened to, and computing power routing information captured by a network chip is written into a switch database, the database publishes relevant information to a service process, the service process recalculates routing after obtaining the computing power routing information from the database, and updates routing table items, so that computing power routing is realized. By introducing computing power routing, the computing resources of each node in the network can be maximally utilized, and the resource utilization rate is improved. The optimization capability enables the network to more efficiently utilize limited resources under the premise of ensuring performance, reduces network operation cost, and provides important support for distributed computing and edge computing.

This invention discloses an elevator energy management method considering device lifespan and energy saving optimization in the field of power supply, distribution, and energy storage technology, comprising the following steps: S1, establishing an elevator energy management system, including a voltage regulator G. V (s), voltage regulator G V (s) and PWM controller G d (s) connected, PWM controller G d (s) and isolated bidirectional DC / DC converter G p (s) connected, isolated bidirectional DC / DC converter G p (s) output voltage reference value U * With voltage regulator G V (s) Connected; S2, Calculate and select the parameters of the components and output filters of the elevator energy management system; S3, Establish a peak-transient dual-mode prediction method; S4, Establish a power routing collaborative optimization method; S5, Establish an elevator operating condition identification method; S6, Establish a joint scheduling method based on grid time-of-use pricing information. Applicable to urban high-rise buildings and universities with frequent start-stop operations, this method optimizes charging and discharging control strategies to achieve efficient recovery and utilization of elevator operating energy, while simultaneously improving the reliability of the elevator system.

This application relates to a computing power routing determination method, apparatus, and mobile core network. The method includes: receiving computing power messages reported by computing power nodes in a computing power network; the computing power messages including computing power resource information and computing power cost information of the computing power nodes; determining computing power routing information corresponding to the computing power nodes based on the computing power resource information and the computing power cost information; and transmitting the computing power routing information to a target network element in the mobile core network through a computing service control interface corresponding to the computing service control network element, so that the target network element determines a computing power route with the computing power nodes based on the received computing power routing information. This method enables the computing service control network element to perform centralized resource management of the computing power network based on the received computing power resources and computing power costs, ensuring a balanced allocation of computing resources.

A method of designing a layout of a semiconductor integrated circuit, including receiving input data defining the semiconductor integrated circuit; determining a first layout of the semiconductor integrated circuit by performing a placement and routing (P&R) procedure based on the input data, wherein the first layout includes a plurality of blocks, a plurality of standard cells, a plurality of power wirings, a plurality of ground wirings, a plurality of clock wirings, and a plurality of signal wirings; selecting a target region of the first layout, wherein the target region is capable of accommodating at least one additional power wiring and at least one additional ground wiring; and determining a second layout of the semiconductor integrated circuit by modifying the first layout to include the at least one additional power wiring and the at least one additional ground wiring in the target region.