3 results about "Place and route" patented technology

Embodiments of the present disclosure relate to methods, devices, media and program products for layout mapping. Some embodiments of the present disclosure provide a method for layout mapping. In the method according to the present disclosure, constraint information for layout and routing is extracted from the original layout and original circuit to be mapped, and a new circuit under a new process is automatically laid out and routed based on the extracted constraint information to obtain a new layout for implementing the new circuit. In this way, the scheme according to the present disclosure avoids the misalignment, overlap and design rule checking problems caused by direct replacement of hierarchy or parameterized cells in the conventional scheme to the greatest extent, so that the workload of the designer can be greatly reduced.

One method includes: generating a netlist for a circuit design; and predicting a first compilation time for the circuit design by applying a first machine learning model to the netlist. The method further includes predicting a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist. The method also includes adjusting the logic of the circuit design according to the first placement and routing strategy.

This invention discloses a method for designing a radiation-resistant test chip to evaluate various single-event effects, comprising: design data preparation; chip placement and routing: constructing test chain circuits based on the design data, placing and routing each test chain circuit, exporting placement and routing data after passing preliminary design rule checks, and extracting parasitic parameter files based on the placement and routing data; static timing analysis: performing timing analysis based on the current placement and routing data and parasitic parameter files to determine if there are timing violations. If so, return to the previous step for redeposition and routing; otherwise, proceed to the next step; physical verification: using physical verification tools to perform DRC design rule checks and LVS comparisons. If errors are found, return for redeposition and routing; otherwise, proceed to the next step; formal verification: determining whether the logical functions of the netlist files before and after placement and routing are completely equivalent. If not, return for redeposition and routing; if equivalent, the design ends.