33 results about "Place and route" patented technology

The invention discloses an automatic layout generation method based on an experience module and a related device, and relates to the technical field of computers.The method comprises the steps that a template file is extracted, an independent device is generated based on the template file, and an experience module library is constructed based on the independent device; determining coordinate mapping and size constraints of the device, and performing multi-channel chip canvas hierarchical construction based on the coordinate mapping and size constraints of the device to obtain multi-channel chip canvas hierarchical representation; based on the empirical module library and the multi-channel chip canvas hierarchical representation, a reinforcement learning model is used for layout wiring, a target layout is obtained, and the reinforcement learning model comprises a state generation model, a value network and a strategy network. Layout and wiring of devices can be controlled more accurately, stray capacitance and resistance are effectively reduced, and the performance and reliability of an analog integrated circuit are effectively improved.

Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.

The present invention discloses an automatic layout generation method. First, for a process library PDK specified by an analog circuit or a mixed-analog circuit, a cell library compiler AcellGen is used to generate the minimum analog unit Acell of each circuit component required for automatic layout. Then, each parameterized unit Pcell in a schematic diagram constructed using the parameterized unit Pcell is replaced with the corresponding minimum analog unit Acell. Then, based on the currently obtained schematic diagram, a corresponding circuit netlist is generated, and the Acell used in the schematic diagram is placed in the same schematic to extract a GDS file. Finally, based on the circuit netlist, GDS and the minimum analog unit of each circuit component required for automatic circuit layout, an automatic place and route tool (PNR) is used to perform final layout generation. The method has the advantages that it can be used for the layout design of analog circuits or mixed-analog circuits, the layout area is small, and no manual intervention is required when performing layout design on analog circuits or mixed-analog circuits, so the efficiency is high.

An embodiment method of forming a layout plan of an integrated circuit (IC) device includes obtaining a placement of a plurality of digital circuit cells in a region of a layout plan; obtaining an initial placement of one or more thermal sensing resistor cells in a subset of a plurality of metallization layers and a subset of a plurality of via layers of the layout plan; obtaining a routing plan based on a clock tree synthesis and the initial placement of the one or more thermal sensing resistor cells; performing a thermal analysis based on the placement of the plurality of digital circuit cells and the routing plan to identify one or more areas of interest in the region of the layout plan; and obtaining a refined placement of the one or more thermal sensing resistor cells respectively over the one or more areas of interest.

A simultaneous placement and routing based method and apparatus for incremental design optimization, and a computer device. The method includes according to a net-list file and a core constraint file acquired after logic synthesis, sequentially placing modules, each including units, on an initial coarse grid and simultaneously performing routing of each module and a placed module; performing iterative verification on placement and routing of the modules, and adjusting an illegal module and simultaneously adjusting routing of the illegal module according to a verification result, until requirements of the core constraint file are met; refining the grid, dividing each module into a plurality of sub-modules, and performing simultaneous placement and routing on the sub-modules in a refined grid; performing iterative verification and simultaneously adjusting placement and routing of illegal sub-modules; and repeating the above steps, until the iterative verification meets the requirements of the core constraint file and timing convergence.

The invention discloses a domain controller PCIe (Peripheral Component Interconnect Express) signal layout and wiring method, a PCB (Printed Circuit Board) and a vehicle. The method comprises the following steps: setting a standard impedance value of a PCIe 3.0 wire to be 80 omega, and setting the length of the PCIe 3.0 wire to be within 3000 mils; wiring of PCIe3.0 routing is set to be inner-layer routing, the routing width is 5.6 mil, and the distance between differential lines is 5.4 mil. According to the method disclosed by the invention, the layout and the wiring of the PCIe3.0 routing are limited in various aspects, so that the layout and the wiring of the PCIe3.0 routing can well cope with a complicated vehicle-mounted environment, and effective transmission and processing of the PCIe3.0 signal are ensured. And the reliability of the corresponding PCB is improved. And furthermore, the reliability and the safety of the whole vehicle are improved. The invention is mainly used in the technical field of vehicles.

The invention is suitable for the technical field of processors, and particularly relates to a self-adaptive power supply wiring method and system of a processor and related equipment. According to the invention, multiple power supply network schemes are established according to the unit density of different areas of the processor chip; selecting one of a plurality of power supply network schemes as a reference scheme, and preliminarily placing units of the processor chip based on the reference scheme; performing regional division on the initial power supply network based on the size of the reference scheme; counting the number of standard units or the equivalent unit area in each physical area unit and calculating the corresponding unit density to obtain the area unit density corresponding to the plurality of physical area units; and adjusting the layout and wiring of the physical region units into a corresponding power supply network scheme based on the density of the region units, so as to realize the self-adaptive power supply wiring of the processor chip. Compared with the prior art, winding resources of areas with different densities can be saved, and the occupation of a power supply network on wiring tracks and metal resources is remarkably reduced.

A method of forming an integrated circuit (IC) includes generating a netlist of a first circuit, generating a first cell layout of the first circuit, and placing the first cell layout, by an automatic placement and routing (APR) tool, in a first region of a layout design. The first circuit is configured as a non-functional circuit, and includes a first and second pin that are electrically disconnected from each other. Generating the netlist of the first circuit includes labelling the first and second pin as a first set of to be connected pins, and designating the first set of to be connected pins as a common group of pins that are to be connected together. Placing the first cell layout by the APR tool includes connecting the first set of to be connected pins in the common group of pins together, thereby changing the first circuit to a second circuit.

Embodiments of the present disclosure relate to methods, devices, media and program products for layout mapping. Some embodiments of the present disclosure provide a method for layout mapping. In the method according to the present disclosure, constraint information for layout and routing is extracted from the original layout and original circuit to be mapped, and a new circuit under a new process is automatically laid out and routed based on the extracted constraint information to obtain a new layout for implementing the new circuit. In this way, the scheme according to the present disclosure avoids the misalignment, overlap and design rule checking problems caused by direct replacement of hierarchy or parameterized cells in the conventional scheme to the greatest extent, so that the workload of the designer can be greatly reduced.

A control apparatus includes a memory, and a processor coupled to the memory. The processor is configured to execute a process including reading, when information about a first process executed by a first circuit logic corresponding to a first template satisfies a given condition, a second template for a second circuit logic that executes a second process related to the first process from a storage area to obtain a read second template, the first circuit logic being set in a rewritable circuit area provided in a programmable logic circuit, the first circuit logic being implemented by writing the first template of which a circuit design synthesis has been completed and of which placement and routing have been already determined, into the circuit area; and writing the read second template into the circuit area to set the second circuit logic that executes the second process in the circuit area.

Disclosed is a method for automating optimal placement and routing of transistors, in which in order to minimize a layout area, diversify a layout structure, and achieve routing optimization, electrical connection information of transistors constituting a circuit and parameters of the transistors are used to primarily place the transistors, heuristic-based pattern optimization and priority are determined, and then the transistors are placed and routed in an optimized state according to the above determination.

An example method includes extracting a plurality of sub-cells based on netlist data; generating a first plurality of layout elements corresponding to the plurality of sub-cells; performing virtual placement of the first plurality of layout elements to obtain at least one virtually placed layout, the first plurality of layout elements corresponding to a plurality of layout elements that at least one template contains; selecting, based on evaluating the at least one virtually placed layout, a first template from the at least one template; and placing and routing the first plurality of layout elements based on the first template.

A design for a programmable integrated circuit (IC) is synthesized and includes an inference engine and a data transformer. A portion of the design including the data transformer is designated as a dynamic function exchange (DFX) module. The inference engine is excluded from the DFX module. The design is implemented, by placing and routing, such that the DFX module is confined to a defined physical area of the programmable integrated circuit. An abstract shell for the design specifying boundary connections of the DFX module as placed and routed is generated. A locked version of the design as placed and routed with the DFX module removed is generated. The method includes implementing a different data transformer as a further DFX module for the design using the abstract shell.

A processing device obtains an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device executes a machine learning model (304) to calculate a probability distribution function on a historical device placement library, the probability distribution function estimates the suitability of each historical device placement in the library of historical device placement for placing and routing the set of devices specified in the input. The processing device presents (306) a graphical representation of a defined number of historical device placement from the library of historical device placement, the historical device placement being estimated to be suitable for placement and routing of the set of devices based on the probability distribution function.

A method for automatically placing and routing processing elements (PEs), where each PE has a limited connectivity to its neighbors. The method may obtain placement primitive (PP) location window information, the location window information defining possible locations of a group of PPs within a coarse-grained reconfigurable array (CGRA). The method may obtain hardware constraints regarding the array of PEs, the hardware constraints comprise local connectivity constraints and remote connectivity constraints. The method may receive a computation graph (CG) that represents mathematical expressions to be calculated by the array of PEs. The method may determine a location of the PEs of the array of PEs based on the CG, the PP location window information, and hardware constraints.

The embodiment of the invention provides an integrated circuit, an implementation and modification method thereof, an implementation device, equipment and a medium. The implementation method comprises the following steps: arranging a plurality of standby unit groups in a layout area, wherein each standby unit group in the plurality of standby unit groups comprises at least one first standby unit; after the plurality of standby unit groups are arranged, arranging a plurality of functional units in the layout area; performing first multi-layer wiring on the plurality of functional units; and after the first multi-layer wiring of the plurality of functional units is completed, performing second multi-layer wiring on the plurality of spare unit groups, the second multi-layer wiring including wiring to a first part of a preset metal layer above the bottom layer in the layout area. According to the method, customized layout and wiring of the standby unit group are realized, the iteration time is reduced, the number of physical design rule checks is reduced, and the influence on a static time sequence is small.

Methods and systems related to parallel computing using heterogeneous networks of computational nodes are disclosed herein. A method for executing a complex computation on a heterogeneous set of computational nodes linked together by a set of links in a network is disclosed. The method includes compiling, using a table of bandwidth values for the set of links in the network, a set of instructions for routing data for the execution of the complex computation. The method also includes configuring a set of programmable controllers on the heterogeneous set of computational nodes with the set of instructions. The method also includes executing the set of instructions using the set of programmable controllers. The method also includes routing data through the network to facilitate the execution of the complex computation by the heterogeneous set of computational nodes and in response to the execution of the instructions.

A method for automatic placement and routing of processing elements (PEs), wherein each PE has limited connectivity to its neighbors. The method may receive information about the position of placement primitives (PPs), wherein the location window information defines possible positions of a group of PPs within a coarse-grained reconfigurable architecture (CGRA). The method may receive hardware constraints related to the array of PEs, wherein the hardware constraints include local connectivity constraints and remote connectivity constraints. The method may receive a computation graph (CG) representing mathematical expressions to be computed by the array of PEs. The method may determine a location of the PEs of the array of PEs based on the CG, the PP location window information, and the hardware constraints.

The invention provides a method for forming a layout plan of an integrated circuit device, a processing device for forming the layout plan of the integrated circuit device, and a non-transitory computer readable storage medium. The method comprises the following steps: obtaining a layout of a plurality of digital circuit units in a layout plan area; obtaining an initial layout of one or more thermal sensing resistor units in the plurality of metallization layer subsets and the plurality of through hole layer subsets in the layout plan; obtaining a routing plan based on the clock tree synthesis and the initial layout of the one or more thermal sensing resistance units; performing a thermal analysis based on the layout of the plurality of digital circuit units and the routing plan to identify one or more regions of interest in the layout plan region; and obtaining fine layouts of the one or more thermal sensing resistor units on the one or more regions of interest, respectively.

One method includes: generating a netlist for a circuit design; and predicting a first compilation time for the circuit design by applying a first machine learning model to the netlist. The method further includes predicting a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist. The method also includes adjusting the logic of the circuit design according to the first placement and routing strategy.

The application relates to the technical field of electronic engineering, and particularly discloses a precise delay locking method and device based on programmable logic, which comprises the following steps: dividing the logic design of a programmable logic device into a static region and a dynamic region; the static region comprises preset delay resources and signal generation logic about the delay resources; the dynamic region comprises functional logic capable of being upgraded; a top-level design comprising the static region and an initial version dynamic region is created, and the static region in the top-level design is subjected to layout and wiring; the layout and wiring results of the static region in the top-level design are locked; when the functional logic in the dynamic region needs to be upgraded, the upgraded dynamic region is subjected to layout and wiring, and the layout and wiring results of the static region are reused. The above-mentioned partition processing mode meets the requirement of high-precision signal generation on delay stability and retains the flexibility advantage of the programmable logic device in functional upgrading.

A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

The present application describes a system with a cost estimation tool for placing and routing a logical edge onto a reconfigurable processor and a method of operating such a cost estimation tool. The method comprises receiving an operation unit graph comprising the logical edge between a logical producer unit and a logical consumer unit and a tentative assignment of the logical edge, the logical producer unit, and the logical consumer unit to a physical link, a physical producer unit, and a physical consumer unit of the reconfigurable processor. The method further comprises determining a realized bandwidth consumption of the tentative assignment based on determining an upper bandwidth limit of the logical edge, determining an end-to-end bandwidth, determining a scaling factor of the realized bandwidth, and determining congestion estimation of the physical link.

The invention discloses a regionalization design method for improving PCB design efficiency and consistency, and the method comprises the following steps: creating and defining a plurality of regionalization design units based on a function modular structure of a circuit in a printed circuit board design environment; configuring a design rule for the regionalized design unit; completing layout and wiring design in a source regionalization design unit; and mapping and multiplexing layout and wiring information in the source regionalization design unit into one or more target regionalization design units through format copying operation. The method has the advantages that the completed module layout and wiring design can be quickly reused for other modules of the same structure through the format copying function, the manual layout and wiring time is greatly saved, repeated labor is avoided, and the problem of the consistency between the efficiency of complex printed circuit board design and physical implementation is practically solved through the method.

The invention relates to the field of FPGA technology, and discloses an LUT Pack method and device based on back-end feedback guide optimization, and the method comprises the steps: generating an initial configuration file in a logic synthesis stage; executing a first-time implementation process, carrying out layout and wiring on the target circuit design, and collecting physical information after layout and wiring; based on the collected physical information, optimizing and updating constraint parameters in the initial configuration file to generate an updated configuration file; and taking the updated configuration file as input, executing the next iteration process until a preset convergence condition is met, and finally outputting the optimized hardware design data. According to the method, a closed-loop feedback and iterative optimization mechanism based on real physical information of back-end layout wiring is introduced to realize dynamic adaptive adjustment of the LUT packaging strategy, so that the contradiction that the resource utilization rate and the time sequence performance are difficult to consider at the same time is overcome, and global optimization balance is obtained between the area efficiency and the circuit performance.

To provide a control apparatus, a control method, and a decentralized processing system for improving processing efficiency of a programmable logic circuit.SOLUTION: In a system 1, an optimization device 4 comprises a control unit configured to: read a second template of a second circuit logic for executing second processing related to first processing from a storage region when information related to the first processing executed by a first circuit logic satisfies a predetermined condition, the first circuit logic being set in a rewritable circuit area 70 included in a programmable logic circuit 7 and being realized by writing a first template in which a synthesis of a circuit design has been completed and an arrangement wiring has been determined into the circuit area 70; and set the second circuit logic for executing the second processing into the circuit area 70 by writing the read second template into the circuit area 70.SELECTED DRAWING: Figure 5

In an integrated circuit, a method of flattened placement and / or routing of multiple transistors using an artificial intelligence (Al) model, comprising the steps of receiving an input consisting of a circuit schematic and features; performing supervised or unsupervised learning of the Al model, to produce a predicted placement and / or routing by the Al model; using a cost function for optimizing transistor placement and / or routing. An optimal placement and / or routing is generated by iteratively running cycles of placement and / or routing, based on the Al model; assigning a value to each placement and / or routing combination, according to the cost function and recording the placements and / or routings and value information across the performed iterations until meeting a predetermined metric or exceeding a predetermined number of iterations or elapsed time; ranking each of the generated placements and / or routing according to the cost function; selecting the k-top (k=l,2,....) placement and / or routing combinations.

The invention relates to the technical field of electronic engineering, and particularly discloses a precise delay locking method and device based on programmable logic, and the method comprises the steps: dividing the logic design of a programmable logic device into a static region and a dynamic region; wherein the static region comprises a preset delay resource and a signal generation logic related to the delay resource; the dynamic area comprises function logic capable of being upgraded; creating a top layer design comprising a static region and an initial version dynamic region, and carrying out layout wiring on the static region in the top layer design; locking layout and wiring results of a static region in the top layer design; and when the function logic in the dynamic region needs to be upgraded, carrying out layout and wiring on the upgraded dynamic region, and reusing the layout and wiring results of the static region. According to the partition processing mode, the requirement of high-precision signal generation for delay stability is met, and the flexibility advantage of the programmable logic device in the aspect of function upgrading is reserved.

This invention discloses a method for designing a radiation-resistant test chip to evaluate various single-event effects, comprising: design data preparation; chip placement and routing: constructing test chain circuits based on the design data, placing and routing each test chain circuit, exporting placement and routing data after passing preliminary design rule checks, and extracting parasitic parameter files based on the placement and routing data; static timing analysis: performing timing analysis based on the current placement and routing data and parasitic parameter files to determine if there are timing violations. If so, return to the previous step for redeposition and routing; otherwise, proceed to the next step; physical verification: using physical verification tools to perform DRC design rule checks and LVS comparisons. If errors are found, return for redeposition and routing; otherwise, proceed to the next step; formal verification: determining whether the logical functions of the netlist files before and after placement and routing are completely equivalent. If not, return for redeposition and routing; if equivalent, the design ends.

Placement of macros of a circuit design includes mapping the macros to types of sub-circuits of an integrated circuit (IC). The IC includes anchors and instances of each type of the types of sub-circuits. The macros are grouped based on couplings of the macros to the anchors specified in the circuit design. Each group includes one or more macros, and the one or more macros in each group are all coupled to the same set of one or more anchors. A location is selected from alternative locations for each group of macros based on a distance of the location from the same set of anchors. Each location includes one or more instances of one or more types of the types of sub-circuits. The circuit design is placed and routed after selecting the location for each group, and implementation data is generated for making an IC that implements the circuit design.