Apparatus and methods for providing in-chip microtargets for metrology or inspection

Abstract

Disclosed are techniques and apparatus for providing metrology or inspection targets in-chip. That is, targets are integrated within the product device or die area. In general terms, the present invention provides techniques for enabling inspection or metrology on targets within the die or active area. Said in another way, target structures are inserted within the die or active area. In one embodiment, a set of rules are provided for integrating test structures within the die. For example, these rules may be implemented by one or more design engineers or by place-and-route tools which automatically generate the die layout pattern and thereafter insert the target structures into the die layout pattern based on these rules. Location data of each target is then retained during the layout generation and provided to one or more inspection or metrology tools and / or metrology engineers so that each target may be found and then inspected or measured.

Description

CROSS REFERENCE TO RELATED PATENT APPLICATION[0001]This application claims priority of U.S. Provisional Patent Application No. 60 / 484,627 filed 2 Jul. 2003 by Avi Cohen et al., which application is incorporated herein by reference in its entirety for all purposes.BACKGROUND OF THE INVENTION[0002]The present invention relates generally to the field of semiconductor metrology and inspection. More specifically, it relates to techniques for providing targets for metrology and / or inspection.[0003]Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the device must be defect free prior to shipment of the device to the end users or customers.[0004]Typically, defects are detected within special test structures or targets, rather...

AI Technical Summary

Benefits of technology

[0018]In another aspect, the invention pertains to a computer system operable to generate a semiconductor layout pattern that is representative of a semiconductor die and a plurality of target structures. The computer system includes one or more processors and one or more memory configured to perform one or more of the above method operations. In yet another aspect, the invention pertains to a computer program product for generating a semiconductor layout pattern that is representative of a semiconductor die and a plurality of target structures. The computer program product includes at least one computer readable medium and computer program instructions stored within the at least one computer readable product configured to perform one or more of the above described inventive procedures.

[0019]These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.

Problems solved by technology

Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon.

Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the device must be defect free prior to shipment of the device to the end users or customers.

Typically, defects are detected within special test structures or targets, rather than the active device or die itself.

It has been undesirable to utilize active area space for nonfunctioning structures because engineers are constantly striving to maximize active feature density.

Unfortunately, a test structure positioned in the scribe line does not best represent product function or typically variations across the field of the lithography (or exposure) tool.

Accordingly, defects captured or measured within the targets may not be a good indicator of defects within the product area or die itself.

In a specific case, the lithography tool usually contains aberrations in its lens system which result in feature misalignments or pattern placement errors across the field.

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