The invention relates to the field of
integrated circuit chip rear-end design, in particular to an advanced process standard unit row lattice point
layout planning method, which comprises the following steps: S1, module initialization and
layout planning; s2, adjusting a
macro cell; s3, checking and verifying; and S4, finally adjusting and optimizing. According to the design
layout requirement rule of the standard unit, the script provided by the embodiment of the invention is used for quickly and accurately carrying out standard unit row lattice point
layout planning on the module; a back-end design implementation engineer only needs to operate the script according to the embodiment of the invention in a module initialization stage and a
floorplan design stage to quickly and accurately complete the
layout planning of the row lattice points of the
standard cell, so that the layout design of the
chip standard cell can meet the requirement rule of a FinFET process on the row lattice points of the
standard cell; and the back-end layout and wiring design of the
chip is ensured to be smoothly advanced, so that the chip can be smoothly tapped out.