The invention discloses a method for realizing periodic online self-test of a network
chip digital component and a
chip architecture. The method comprises the following steps: S1, adding a TestPattern generator, a TestPattern response processor, a configuration and state memory sandbox, sandbox mapping logic and output check value logic on the basis of a
chip functional architecture; s2, a TestPattern sequence is generated through a TestPattern generator, each TestPattern in the TestPattern sequence comprises a message, configuration and expected
checksum information, for each TestPattern, the corresponding configuration is updated to a configuration and state storage sandbox, meanwhile, the TestPattern is notified to respond to the expected
checksum information of a processor, and then the corresponding message is sent to a first functional unit of the chip; s3, the messages of the TestPattern sequentially pass through the corresponding functional units according to the
processing sequence, when memory access operation is encountered, the memory access operation is mapped to the configuration and state storage sandbox through sandbox mapping logic, read-write operation is executed on the configuration and state storage sandbox, output check sums of the corresponding functional units are obtained through output check value logic, and the output check sums of the corresponding functional units are obtained; the output check sum of the last functional unit is sent to the TestPattern response processor; s4, the TestPattern response processor judges whether a random hardware fault exists or not based on the expected
checksum information and the obtained checksum, namely the output checksum of the last functional unit; and S5, all Patterns of the TestPattern sequence are completed in the FDTI, and the TestPattern sequence is executed in a circulating manner.