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88 results about "Temporal logic" patented technology

In logic, temporal logic is any system of rules and symbolism for representing, and reasoning about, propositions qualified in terms of time (for example, "I am always hungry", "I will eventually be hungry", or "I will be hungry until I eat something"). It is sometimes also used to refer to tense logic, a modal logic-based system of temporal logic introduced by Arthur Prior in the late 1950s, with important contributions by Hans Kamp. It has been further developed by computer scientists, notably Amir Pnueli, and logicians.

Disaster information spatial-temporal database

The invention provides a disaster information spatial-temporal database, which comprises three disaster information databases including a disaster current simulation database, a disaster process database and a disaster historical database, wherein a unified coding module carries out layered coding on the received disaster information data, an attribute data management module and a space position management module guide in disaster information attribute data and space position data to the corresponding disaster information database, the disaster information data is transmitted among all disaster information databases through a logic conversion module, a spatial-temporal database index module builds updating index for the disaster information spatial-temporal database according to the time sequence, the logic conversion module and the spatial-temporal database index module form the basis of the disaster information spatial-temporal database, and the preparation is made for the disaster attribute management and maintenance, spatial-temporal logic index conversion and maintenance, statistics data entry, index and spatial-temporal inquiry. The disaster information spatial-temporal database solves the problems of lower work efficiency and high data redundancy during the realization of spatial-temporal data storage, management and historical review.
Owner:SHANGHAI NORMAL UNIVERSITY

Temporal logic robustness assessment method for information physical fusion system

ActiveCN104657610AEasy to understand the operation processGuaranteed correctnessSpecial data processing applicationsModel testingWork time
The invention provides a temporal logic robustness assessment method for an information physical fusion system. The method comprises the following steps of: firstly, capturing and abstracting the dynamic characteristics of the information physical fusion system by adopting a temporal logic, converting the information physical fusion system into an user-defined system model, and expressing a limited track of the system by use of a temporal logic formula; secondly, verifying the established model by virtue of a model testing technology so as to ensure the correctness of the model, feeding back a counter-example, namely a forged track which does not conform to the formula, in the system to users; finally, performing robustness assessment by adopting an optimization method according to the track and temporal logic standard of the system, setting time domain intervals according to a certain method and a certain procedure, obtaining the robustness values of different state sequences under different sampling points, and feeding back a finally-calculated robustness value which represents the whole system to the users. The linear working time and the constant memory usage are realized, the memory space can be saved, the working time of the system is reduced, and the efficiency of the system is improved.
Owner:NANJING UNIV OF POSTS & TELECOMM

Dynamic accident deduction simulation-based failure mode and influence analysis method

The invention discloses a dynamic accident deduction simulation-based failure mode and influence analysis method. According to the method, in allusion to characteristics of analyzed objects, a function box of each module at the lowest agreed layer is constructed to construct a function box map; being different from the traditional operation of adding failure rates and carrying out reliability analysis on function modules, the method is characterized by constructing a dynamic accident deduction simulation model which comprises elements such as state, event and the like for internal behaviors ofeach function box, connecting all the function boxes into a whole through constructing logic and time relationships between the function boxes, and finally simulating dynamic operation processes of systems through a dynamic discrete event simulation method so as to find out failure events and generation probabilities of the systems and then carry out further failure influence and hazard analysis.The method disclosed by the invention is capable of solving the problem that the traditional failure mode and influence analysis method cannot carry out temporal logic analysis and combined functionfailure analysis.
Owner:CHINA AERO POLYTECH ESTAB

Bipolar half-sine current generating device and method for full-ATEM (airborne transient electromagnetic system)

The invention provides a bipolar half-sine current generating device and method for a full-ATEM (airborne transient electromagnetic system). The bipolar half-sine current generating device comprises a master control circuit, wherein a driving circuit is located between the master control circuit and an overshoot suppression circuit, connected with the master control circuit and the overshoot suppression circuit and used for generating an overshoot suppression temporal logic signal and providing a driving control signal for the overshoot suppression circuit; a trigger circuit is located between the master control circuit and an H inverter bridge, connected with the master control circuit and the H inverter bridge and used for generating a trigger control signal from an H-bridge inverting temporal logic signal; the H inverter bridge is connected with a power supply and used for outputting a bipolar square signal according to a constant-voltage signal of the power supply and the trigger control signal; the overshoot suppression circuit is connected with a series resonance circuit and used for supplying energy release access to oscillation waveform at the tail of current waveform contained in the series resonance circuit and eliminating the oscillation waveform at the tail of the current waveform; the series resonance circuit is connected with the H inverter bridge and used for generating bipolar half-sine current waveform meeting the current waveform requirement according to the bipolar square signal and eliminating oscillation at the tail of the current waveform by using the overshoot suppression circuit.
Owner:INST OF ELECTRONICS CHINESE ACAD OF SCI

Deadlock detection verification method

The invention discloses a deadlock detection verification method, which comprises the following steps: extracting the state and the state transferring relationship of a progress to be extracted; establishing different deadlock detection templates; independently writing the state and the state transferring relationship of the progress as well as a modeling attribute into an XML (Extensive Markup Language) configuration file according to categories; reading the XML configuration file, and selecting the corresponding deadlock detection template to carry out model detection: generating a temporal logic expression CTL (Computing Tree Logic), and converting the state and the state transferring relationship of the progress as well as the temporal logic expression CTL into a SMV (Symbolic Model Verification) model; and executing the SMV model, analyzing a truth value of the temporal logic expression CTL in an execution result, and judging whether a design document contains deadlock or not. The deadlock detection verification method automatically analyzes the input of the relevant information of the deadlock detection to automatically select and convert the corresponding template into a prototype of the SMV model, lowers a deadlock detection difficulty, is free from the restriction of software development languages, can carry out deadlock detection on a design scheme in a system design stage and reduces unnecessary losses if being compared with a situation that the deadlock is found in a software development stage.
Owner:SICHUAN UNIV
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