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Deadlock detection verification method

A deadlock detection and verification method technology, applied in the field of deadlock detection and verification, can solve the problems of large and complex models, difficult manual construction, etc., and achieve the effect of reducing difficulty and reducing unnecessary losses

Inactive Publication Date: 2015-11-04
SICHUAN UNIV
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Problems solved by technology

For model checking, due to the huge interleaving state space between concurrent software processes, the model is too large and complex to be constructed manually

Method used

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specific Embodiment

[0044] Use an example of a synchronous mutex to complete the analysis of the deadlock detection step: There are two stonemasons carving a statue on the same production line, but there is only one set of tools. If the stonemason is free, he can continue to rest or prepare for work. After the preparation work is completed, if the tool can be used, then he can go to the production line to work. After a stage of work is completed, he can choose to rest or continue working. If he chooses to rest, he will put down the tool in his hand, and another mason can pick it up. Go to work.

[0045] (1) Analyze system design documents and abstract the system. This embodiment is an example of a synchronous mutual exclusion lock. By analyzing the design requirements in the example, it is obtained that there are two processes (workers), and the working states of the processes are divided into three states: idle state, ready state, and working state. The initial state is the idle state, and it i...

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Abstract

The invention discloses a deadlock detection verification method, which comprises the following steps: extracting the state and the state transferring relationship of a progress to be extracted; establishing different deadlock detection templates; independently writing the state and the state transferring relationship of the progress as well as a modeling attribute into an XML (Extensive Markup Language) configuration file according to categories; reading the XML configuration file, and selecting the corresponding deadlock detection template to carry out model detection: generating a temporal logic expression CTL (Computing Tree Logic), and converting the state and the state transferring relationship of the progress as well as the temporal logic expression CTL into a SMV (Symbolic Model Verification) model; and executing the SMV model, analyzing a truth value of the temporal logic expression CTL in an execution result, and judging whether a design document contains deadlock or not. The deadlock detection verification method automatically analyzes the input of the relevant information of the deadlock detection to automatically select and convert the corresponding template into a prototype of the SMV model, lowers a deadlock detection difficulty, is free from the restriction of software development languages, can carry out deadlock detection on a design scheme in a system design stage and reduces unnecessary losses if being compared with a situation that the deadlock is found in a software development stage.

Description

technical field [0001] The invention relates to the technical field of software design, in particular to a deadlock detection and verification method. Background technique [0002] Deadlock is a relatively common software design defect in concurrent systems, and it is also a very typical problem that needs attention in solving concurrent security. The occurrence of deadlock will cause the program to wait indefinitely or consume resources severely, causing the entire system to be paralyzed without available resources, seriously affecting system security and reliability. [0003] The SMV tool is a model checking tool software developed by Dr. L.McMillan of the CMU School of Computer Science in 1992. It is based on the symbolic model checking (Symbolic Model Checking) technology and is currently a common tool for analyzing finite state systems that is widely popular in the world. , There are multiple versions of SMV, such as: CMU-SMV, Cadence-SMV, NuSMV, etc. [0004] The met...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
Inventor 杨秋辉代声馨张琼宇孙琳何洋杜伊
Owner SICHUAN UNIV
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