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Symbolized model detection method

A technology of model detection and detection method, applied in the intersection of integrated circuits and reliable systems, can solve problems such as limited versatility, achieve the effect of extensive and comprehensive reliability, and overcome the problem of state space explosion

Inactive Publication Date: 2007-08-08
JIANGSU UNIV
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  • Description
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Problems solved by technology

But its versatility is still relatively limited, because it has two main disadvantages:
[0015] 1. Only full-name attributes can be verified. For attributes that contain both full-name operators and existence operators, this method is helpless

Method used

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  • Symbolized model detection method

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example

[0054] At present, the verification method we invented has been used in the reliability verification of the JTAG debugger TapScope and the signal converter composed of 5 timers. Take them as examples below to describe our inventive method in detail.

[0055] 1. One of the verification examples: the reliability verification of the JTAG debug analyzer TapScope

[0056] TapScope is a debugging analysis tool for debugging boundary-scan links. It can be used to debug boundary-scan chains of any length composed of devices conforming to the IEEE1149.1 boundary-scan standard. It can also be used as a learning tool to help Students quickly understand and master boundary-scan technology.

[0057] 1. Structure of TapScope and TAP controller

[0058] TapSope debugging analyzer includes hardware circuit board modules and software modules running on PC. The hardware circuit board module mainly includes three parts, namely: the level conversion module of the input signal, the PCI bus inte...

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Abstract

This symbol model detection method is a method to make the model testing practical; the main principle is to use Boolean formula quantitative determination to instead of the CTL model testing. Their method: 1.) extract state machine M of the tested system and the attributes of the tested tree temporal logic description; 2.) taking border k as the form parameters, describe k sector semantics of the attributes f; 3.) taking border k as the form parameters, convert the k sector semantic of attribute f to quantify Boolean formula [M, f] k: 4.) progressive determine whether the system M meets the reliable attribute f: the approach integrates the advantages of symbol model testing based on binary decision diagram and bounded model checking based proposition equitation meeting judgment, also overcomes their shortcomings, which are not dependent on the sort of Boolean variables, or dependent on the property to verify the full name attribute.

Description

technical field [0001] The invention is a solution for symbolization technology applied to hardware reliability verification, which is mainly used to solve the reliability problem of large-scale integrated circuits, and belongs to the cross-technical field of integrated circuits and reliable systems. Background technique [0002] With the increasing complexity of computer software and hardware systems, how to ensure their correctness and reliability has become an increasingly urgent problem. For concurrent systems, this problem is even more difficult due to their inherent non-determinism. In the past few decades, researchers from various countries have made great efforts to solve this problem and made important progress. Among the many theories and methods proposed for this purpose, model checking stands out for its simplicity and high degree of automation. [0003] The research on model checking began in the early 1980s, when Clarke, Emerson and others proposed the comput...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 周从华鞠时光肖铁军
Owner JIANGSU UNIV
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