Parallel RTL synthesis method based on multi-FPGA system and storage medium

Abstract

The invention discloses a parallel RTL synthesis method based on a multi-FPGA system and a storage medium. The parallel RTL synthesis method based on the multi-FPGA system comprises the following steps: traversing each instance of a tested design according to a top node to create a hierarchical tree; traversing the hierarchical tree in parallel to uniquely process each module, and recording a hash value of the module after uniquely processing; taking modules as units, performing parallel refinement and logic mapping on each module, and converting a tested design corresponding to each module into a gate-level circuit from an RTL (Register Transfer Language); combining the gate-level circuits corresponding to the modules into a whole to form a hierarchical netlist; counting resources consumed by the hierarchical netlist, and automatically selecting a hypergraph unit according to resource constraints; and performing segmentation by adopting a segmentation tool to form a netlist corresponding to each FPGA. According to the method, parallel comprehensive processing of the RTL is realized, a large-scale integrated circuit can be dealt with, and meanwhile, the simulation verification efficiency can be improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit simulation, in particular to a method for parallel synthesizing RTL. Background technique [0002] The system simulation verification efficiency of pure software-based large-scale integrated circuits is very low, which will greatly increase the chip development cycle, especially for large-scale integrated circuit chips with advanced processes above 14 nanometers, which is intolerable. Therefore, the industry recommends the use of hardware simulation acceleration technology based on multi-FPGA systems to speed up the system simulation verification of chips. [0003] RTL synthesis is to convert the RTL-level code of the hardware description language into a gate-level netlist, which is a necessary step for RTL-based design simulation verification. In the prior art, the entire RTL-level code corresponding to the large-scale integrated circuit Input it into the corresponding tool to get the...

AI Technical Summary

Problems solved by technology

[0006] In order to solve the technical problem of low processing efficiency of RTL design corresponding to large-scale integrated circuits in the prior art, the present invention proposes a parallel RTL synthesis method and storage medium based on a multi-FPGA system

Images