The application belongs to the field of integrated circuits, and specifically provides a low-
power consumption enhanced reading type 11T CNFET
SRAM cell circuit to solve the problems of
slow speed, low stability, high
power consumption and the like in the prior art; the application comprises N-type carbon nanometer
field effect transistors MN1-MN9 and P-type carbon nanometer
field effect transistors MP1-2, on the basis of a conventional 6T
SRAM cell circuit, a dynamic load structure composed of transistors MN7, MN8 and MN9, and a high-resistance differential readout circuit composed of transistors MN3, MN4, MN5 and MN6; the adoption of P-type transistors realizes a bistable latch structure to reduce holding and writing
power consumption, eliminate path competition phenomena caused by data flipping during writing, and improve writing speed; during reading, a
resistive load tube is turned on to eliminate charge accumulation and ensure data storage stability; the high-resistance differential readout circuit reduces
voltage disturbance of a storage node caused by
bit line load; meanwhile, the differential writing / reading circuit can suppress common-mode
noise and external interference on the
bit line, reduce the
probability of error sampling, and enhance overall anti-interference capability.