569results about How to "Increase write speed" patented technology

Thin film transistors including an oxide semiconductor containing indium, gallium, and zinc are easily arranged in a matrix over a large substrate and have small characteristic variations. With amplifier circuits and driver circuits of display elements which include the thin film transistors including an oxide semiconductor containing indium, gallium, and zinc with small characteristic variations, intensity distribution of light received by the photodiodes arranged in a matrix is converted into electrical signals with high reproducibility and output, and the display elements arranged in a matrix can be uniformly driven.

A memory including memory cells having active and passive layers may store multiple information bits. The active layer may include an organic polymer that has a variable resistance based on the movement of charged species (ions or ions and electrons) between the passive layer and the active layer. The passive layer may be a super-ionic material that has high ion and electron mobility. The active layer may be self-assembled from a monomer in a liquid or gas.

The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. In an exemplary embodiment of the write sequence for the multi-state memory during a program/verify cycle sequence of the selected storage elements, at the beginning of the process only the lowest state of the multi-state range to which the selected storage elements are being programmed is checked during the verify phase. Once the first storage state is reached by one or more of the selected elements, the next state in the sequence of multi-states is added to the verify process. This next state can either be added immediately upon the fastest elements reaching this preceding state in the sequence or after a delay of several program cycles. The adding of states to the set being checked in the verify phase continues through the rest of the set of multi-states in sequence, until the highest state has been added. Additionally, lower states can be removed from the verify set as all of the selected storage elements bound for these levels verify successfully to those target values and are locked out from further programming.

A hierarchical data-storage system has a volatile storage medium, a first non-volatile storage medium, and a controller including a ranking engine tracking data writes to each of the memory mediums. Each medium is associated with a pre-set capacity threshold, and the controller, upon the volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the volatile medium, copies the data in those blocks to the non-volatile medium, and marks those blocks as available for new data writes, and the controller, upon the non-volatile medium reaching its pre-set threshold, identifies one or more blocks of data as least-frequently written to the non-volatile medium, and marks those blocks as available for new data writes from the volatile medium.

A magnetic memory device comprises a magnetic tunnel junction (MTJ) connecting to a bit line to a sense line through an isolation transistor. The MTJ includes a ferromagnetic layer having a magnetic hard axis. An assist current line overlies the bit line and is insulated from the bit line. The MTJ is switchable between a first, relatively high resistance state and a second, relatively low resistance state. The assist current line applies a magnetic field along the magnetic hard axis in the ferromagnetic layer, independently of current flow through the MTJ for assisting switching of the MTJ between the first and second states.

A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.

The invention provides a high-performance reliable solid-state disk realizing method. The method includes: (1), dividing all flash memory chips in a solid-state disk into groups and forming an RAID (redundant array of independent disks) 4-level flash array in each group by N successive flash chips; (2), receiving and storing data through a cache; (3), judging whether the cache is filled up or not, if yes, entering the step (4), and if not, returning to the step (2); (4), extracting N-1 data blocks from the cache and computing check values of the N-1 data blocks; making up the N-1 data blocks and the check values into filled stripe data and writing back the flash array; returning to the step (2). The flash chips in the solid-state disk are used for establishing the RAID4-level physical array to assure data reliability. Faults at different levels including page level, block level, or even chip level can be processed. Besides, writing-in performance is improved by writing of filled stripes and sequence, and spatial and performance loss resulted from data errors can be reduced to the utmost.

The invention discloses a face recognition method based on an intelligent card, which comprises the following steps: acquiring and transmitting face data; judging the quality of the face data; adjusting the brightness for the face data with qualified quality; extracting face features, and transmitting the face features to the intelligent card by an encrypted way; and comparing the face images, anddetermining whether the identification passes or not. The invention also discloses a face recognition system which comprises a face detection module, a data safety communication module, a face imagequality judging module, a face image brightness adjusting module, a face feature extracting module and a face verification module. By adopting the system and the method of the invention, the defect ofthe reduction of the recognition effect caused by attitude deviation is eliminated, and the recognition rate is greatly improved. In addition, in the process of comparing the face images, the writingspeed, the reading speed and the operating speed of the compressed face image data are quick, thereby meeting the requirements of various real-time application conditions.

We investigate error-correcting codes for a novel storage technology, which we call the rank-modulation scheme. In this scheme, a set of n cells stores information in the permutation induced by the different levels of the individual cells. The resulting scheme eliminates the need for discrete cell levels, and overshoot errors when programming cells (a serious problem that reduces the writing speed), as well as mitigates the problem of asymmetric errors. In this discussion, the properties of error correction in rank modulation codes are studied. We show that the adjacency graph of permutations is a subgraph of a multi-dimensional array of a special size, a property that enables code designs based on Lee-metric codes and L₁-metric codes. We present a one-error-correcting code whose size is at least half of the optimal size. We also present additional error-correcting codes and some related bounds.

A semiconductor memory of the present invention comprises: a static-type memory cell constituted of a pair of access transistors formed with NMOS transistors, a pair of drive transistors formed with NMOS transistors, and a pair of load transistors formed with PMOS transistors. Further, it comprises a substrate bias control unit which applies bias for increasing access speed to a substrate of any of the transistors when making access to the memory cell through adjusting electric current flown to a memory storage node in a common junction point of the three types of transistors. A substrate potential which is appropriate for reading-out, writing, memory-storing operation and low leak is applied.

A mass storage device having at least one flash memory device and DRAM or SRAM-based cache within a package, and which comprises co-processor means within the package for performing compression and decompression of cached data before writing the cached data to the flash memory device.

The invention provides a high-speed multi-beam parallel laser direct-writing device applying to micro-nano processing. The device consists of an inscribing light source modulation module, an inscribing optical header, an out-of-focus detection module, an illuminating and monitoring module, a sample displacement table and a master control module. The device greatly improves inscribing speed by multi-beam laser parallel high-speed inscribing. A multi-beam inscribing sub-system can be combined with sample tables with different motion modes to form inscribing devices with different functions according to the requirement of actual application.

The embodiment of the invention provides a login method and a login system of a cross-domain server. The login method comprises the steps that: a first domain server obtains feature information according to a first login request when receiving the first login request of a second domain server sent by a client; the first domain server sends a login token generation request to the second domain server; the second domain server generates a login token by utilizing the feature information according to the generation request; the second domain server sends the login token and a login address to the first domain server; the first domain server embeds the login token into the login address to obtain a credit login address; the first domain server returns a request response to the client; the second domain server receives a second login request of the second domain server sent by the client when redirecting to the credit login address; and the second domain server adopts the feature information to perform login operation when judging that at least part of information contained in the second login request matches with the feature information. The login method and the login system enlarge the range of application.

A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.

The invention discloses an HBase (hadoop database) data usability and durability method based on remote log backup. The method is characterized in that when a data node of the HBase is written, the log record is first encapsulated through a distributive system, the log is backed up to a preliminarily-designated remote node through a network, the usability and durability of the data can be guaranteed, on the basis of the data, a great amount of user data and log record are temporarily stored in a memory, and the data persisting process in the data processing process is reduced; when the data node of the HBase is idle, the data in the memory is persisted to a file system, the storage pressure of the memory can be alleviated, the frequency of the persistence process in the writing process can be reduced, and the data writing time performance can be improved. By adopting the method, the usability and durability of the data can be guaranteed, the data writing speed can be greatly increased, and the system performance is improved.

A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.

A semiconductor device is provided in which a transistor which supplies a current to a load (an EL pixel and a signal line) can supply an accurate current without being affected by a variation. A voltage of each terminal of a transistor is controlled by using a feedback circuit using an amplifier circuit. A current Idata is inputted from a current source circuit to a transistor and a gate-source voltage (a source potential) required for the transistor to flow the current Idata is set by using the feedback circuit. The feedback circuit is controlled to operate so that a drain potential of the transistor becomes a predetermined potential. Then, a gate voltage required to flow the current Idata is set. By using the set transistor, an accurate current can be supplied to the load (an EL element and a signal line). As a drain potential can be controlled, the kink effect can be reduced.

The invention discloses a novel static random access memory (SRAM) storage unit preventing a single particle from turning. The storage unit comprises a first input/output port, a first potential turning recovery driving circuit, a voltage retaining circuit, a second potential turning recovery driving circuit and a second input/output port which are connected in series with one another sequentially. An automatic recovery function for voltage turning when a sensitive node is impacted by a high-energy particle can be realized; according to a simulation result of a TSMC 0.18 mu_m process, a turning threshold value LETth is more than 500 MeV/(mg.cm<2>); compared with the conventional storage unit preventing the single particle from turning, the SRAM storage unit has the characteristic of high writing speed; the recovery time can be effectively shortened; by adopting a unidirectional clock and a small-clock amplitude, a clock network is relatively simple and relatively high in reliability; the clock is only connected with the gate of a read-write transistor, and the clock load is relatively small; and the sensitive node can be used for reinforcing multi-node turning of the single particle, which is caused by drains positioned on a P-type tube and an N-type tube..

The embodiment of the invention provides a data backup method and device, and relates to the field of data storage. The method and the device solve the problem of I/O (input/output) performance reduction due to COW (copy on write) processing in the prior art, and have the advantage that the data write-in speed is accelerated. The method adopting the scheme comprises the following steps that a write operation instruction is received, wherein the write operation instruction includes first data to be written in and a logic address of the first data to be written in; the first data to be written in is written into a high-speed cache; when the first data to be written in is written into the high-speed cache, first data to be backed up is obtained from the logic address of the first data to be written in, so that the first data to be backed up is written into a storage space used for storing a snapshot, wherein the first data to be written in is read from the high-speed cache, the first data to be written in is written into the storage space corresponding to the logic address of the first data to be written in.