103 results about "Unit group" patented technology

A linear displacement sensor based on electric field self-coupling, comprising a moving scale base (1) and a fixed scale base (2). One or more paired electrode units are provided on the side surface of the moving scale base (1) facing the fixed scale base (2); each paired electrode unit comprises at least three sensing electrode groups spaced in the length direction of the moving scale base (1); each sensing electrode group comprises one excitation electrode (1-1) and one sensing electrode (1-2) spaced in the length direction of the moving scale base (1). A plurality of modulation unit groups arranged in the length direction of the fixed scale base (2) are provided on the side surface of the fixed scale base (2) facing the moving scale base (1); in the length direction of the fixed scale base (2), all the paired electrode units on the moving scale base (1) can respectively correspond to the same number of adjacent modulation unit groups on the fixed scale base (2); each modulation unit group comprises one modulation unit F(2-1) and one modulation unit G(2-2); the modulation unit F(2-1) can correspond to at least one sensing electrode group in the paired electrode units in the length direction of the fixed scale base (2).

The invention discloses a photovoltaic module. The photovoltaic module comprises a battery unit group and a connecting structure, the battery unit group comprises a plurality of battery strings which are connected in series and / or in parallel; the connection structure comprises a bypass strip, the bypass strip is arranged between adjacent battery unit groups, the bypass strip comprises a first non-lead-out part, a second non-lead-out part and a lead-out part, the lead-out part is connected between the first non-lead-out part and the second non-lead-out part, and the lead-out part extends in the direction away from the first non-lead-out part and the second non-lead-out part. The lead-out part, the first non-lead-out part and the second non-lead-out part are integrally formed. Therefore, the leading-out part is formed on at least part of the bypass strip, the structure of the bypass strip is simplified, compared with the design of multiple leading-out ends of the bypass strip, the welding procedure can be reduced through one leading-out end, and the installation difficulty can be reduced when the leading-out part is connected with the junction box. And meanwhile, the bypass strip is integrally formed, so that the thickness of the non-lead-out part is prevented from being increased, and the risk of cracking the battery pieces on the battery string is effectively reduced.

The invention discloses a ferroelectric memory, a reading method and electronic equipment, the ferroelectric memory comprises a plurality of word lines, a plurality of bit lines and a plurality of ferroelectric memory units, a first ferroelectric memory unit and a second ferroelectric memory unit which are connected with the same word line form a unit group, so that a plurality of unit groups are divided; in any unit group, at least one bit line is arranged between the bit line connected with the first ferroelectric storage unit and the bit line connected with the second ferroelectric storage unit, so that the bit line between the bit lines connected with the first ferroelectric storage unit and the second ferroelectric storage unit is used as a shielding line, the problem of mutual coupling when the bit lines read signals is solved, and the signal reading efficiency is improved. And the signal reading accuracy is improved. Moreover, in the two adjacent unit groups connected to the same word line, the bit line connected with the first ferroelectric storage unit in one unit group is adjacent to the bit line connected with the second ferroelectric storage unit in the other unit group, so that the density of the ferroelectric storage units can be improved.

The application discloses a power distribution network scheduling method and system, and a computer program product, and belongs to the technical field of smart grids, and comprises the following steps: dividing a power distribution network into multiple power distribution network levels according to voltage grades, collecting data of each power distribution network level, setting a minimum total cost of virtual power plant output as a target function, and constructing an optimization model; starting from a lower power distribution network level, sequentially and independently calculating power flow of each power distribution network level, equivalently taking first-end injected power of the lower power distribution network level as corresponding node load of an upper level, outputting power flow operation conditions of each power distribution network level, establishing a power flow checking constraint model, judging whether the safety operation checking constraint is met, if yes, solving the optimization model by using an optimization algorithm to obtain the minimum total cost and corresponding output values of an output unit group, and if not, reassigning data to perform a new round of optimization. The application considers inverse-level dynamic coupling modeling of grid connection of new power generation units, and provides an integrated solution for dynamic safety and economic scheduling of the power distribution network.

The present disclosure provides a fault processing method and device applied to a data processing apparatus, equipment and a medium, relates to the technical field of computers, and particularly relates to the fields of data processing, fault processing and chip technology. The implementation scheme is as follows: a plurality of unit groups are determined based on the grid-shaped topology of the data processing apparatus; it is determined whether each data processing unit is a faulty unit; for each unit group, in response to determining that the unit group does not include a faulty unit, the unit group is determined to be a valid group; in response to determining that the number of valid groups meets a preset condition, a configuration operation is sequentially performed on the plurality of unit groups, the configuration operation comprising: for each unit group, in response to determining that the unit group includes a faulty unit that is not placed in a bypass state, a plurality of data processing units in the unit group are placed in a bypass state, wherein the data input port and the data output port of the data processing unit placed in the bypass state are in short-circuit connection; and in response to determining that the number of valid groups does not meet the preset condition, the data processing apparatus is determined to be a faulty apparatus.

A display substrate and a display device, the display substrate comprising a display area (91) and a peripheral area, the peripheral area comprising a circuit area (92), the display area comprising: a plurality of sub-pixels (1), a plurality of data lines (11) extending along a first direction (991), and a plurality of gate lines (12) extending along a second direction (992); the circuit area (92) comprising a plurality of driving unit groups, the circuit area (92) comprising a first sub-area (921) and a second sub-area (922) opposite on both sides of the display area (91) along the first direction (991), the first sub-area (921) comprising a plurality of multiplexing unit groups, and the second sub-area (922) comprising a plurality of test unit groups, the driving unit (4) being configured to provide a driving signal to the gate line (12), the multiplexing unit (2) being configured to provide a data signal to the data line (11), and the test unit (3) being configured to provide a test signal to the data line (11); in the first sub-area (921), the driving unit groups and the multiplexing unit groups are arranged alternately; and in the second sub-area (922), the driving unit groups and the test unit groups are arranged alternately.

The invention discloses an automatic batch detection method for multifunctional meters. The method comprises the following steps: (1) constructing a detection system by adopting a standard source, a current relay, a communication relay and a control system, and establishing a detection unit group; (2) detecting system line connection; (3) address setting: in the address setting process, addresses are allocated to all the to-be-tested multifunctional meters in sequence, and the to-be-tested multifunctional meters are in an online state; and (4) power-on test: the control system compares detection data with standard data output by the standard source to judge whether an error is within an allowable range, namely whether the product is qualified. The device has the advantages that addresses of newly-installed multifunctional meters can be automatically modified in sequence through the on-off mode of the relays, the address conflict problem is effectively prevented, and the number of detection instruments can be set through the on-off mode of the relays.

Embodiments of the present application provide a control channel unit determination method and device, and a storage medium, wherein the control channel unit determination method comprises: selecting part of resource unit groups in N resource unit groups to form a control channel unit, and forming a control channel unit by at least one of the following ways: for a physical downlink control channel (PDCCH) based on a demodulation reference signal (DMRS), when the mapping between a control channel unit (CCE) and a resource element group (REG) is distributed mapping, at least the following principle is satisfied: M REGs are equally spaced or discretely spaced in the frequency domain to form a CCE, wherein M is the number of REGs contained in K RBs in a transmission time interval, K is a positive integer, and N is a positive integer; for a PDCCH based on a cell reference signal (CRS), when the mapping between a CCE and a REG is distributed mapping, at least the following principle is satisfied: a group of REGs equally spaced or discretely spaced in the frequency domain form a CCE in a single symbol.

The utility model belongs to the technical field of service life testing, and particularly relates to a reciprocating mechanism for testing a linear guide rail pair. The grooves matched with the guide rails are formed in the connecting blocks of the double-cylinder shafts, the guide rails are clamped and fixed in the grooves, external screws are tightened, then the connecting block on the other side and the guide rails are fixed, and due to the fact that the double-cylinder shafts and the fixing mechanism do reciprocating motion, the guide rails are very convenient to install; the number of the balancing rods is two, the two balancing rods are respectively fixed on the inner walls of the opposite fixing mechanisms, the fixing mechanisms on the two sides are provided with holes, the balancing rods are arranged in the holes, the balancing rods vibrate in the holes, the service life of the double-cylinder shaft is guaranteed, and meanwhile the influence of vibration on the guide rail pair testing unit group is small.

The present invention provides a display panel and a preparation therefor. The display panel at least includes a plurality of pixel unit groups, each of the pixel unit groups includes a plurality of pixel units, each of the pixel units includes a plurality of sub-pixels, and each of the sub-pixels has a functional layer. For the display panel provided by the present invention, the functional layers of multiple sub-pixels with a same color of the plurality of sub-pixels in each of the pixel unit groups are arranged in a first direction and connected with each other, which reduces precision requirements for ink output of each nozzle during an ink jet printing process and reduces a thickness difference of the functional layers of each column of the sub-pixels arranged in a printing direction, thereby effectively preventing generation of lateral Suji Mura during display of the display panel.

The invention provides a photoresist development simulation method, a computer readable storage medium and a computer program product.The photoresist development simulation method comprises the steps that a photoresist development model is divided into grids, and whether photoresist resin makes contact with a development solvent or not is judged according to the occupancy state of grid points of the grids, the method for determining the occupancy state of the lattice points of the grid comprises the following steps: constructing a sphere in a photoresist developing model, taking a unit group of photoresist resin as a sphere center of the sphere, and taking the sum of the Van der Waals radius of the unit group of the photoresist resin and the Van der Waals radius of a developing solvent as a radius of the sphere; and traversing the sphere, and if the lattice points are surrounded by the sphere, adding 1 to the occupancy state of the lattice points. According to the developing simulation method for judging whether the photoresist resin is in contact with the developing solvent or not through the Van der Waals radius of the photoresist resin and the Van der Waals radius of the developing solvent, the influence of the permeation behavior of the developing solvent in the photoresist resin on photoresist developing is accurately and effectively reflected; and the method has guiding significance for researching the influence of different resin structures on the photoresist developing result.

The utility model provides a multi-station variable-pitch boxing manipulator, and belongs to the technical field of automatic packaging equipment. The multi-station grabbing device comprises a material receiving frame, a linear guide mechanism is arranged on the material receiving frame, at least one multi-station grabbing unit set is arranged on the linear guide mechanism, each multi-station grabbing unit set comprises N grabbing units distributed in the linear direction of the linear guide mechanism, N is larger than or equal to 3, one grabbing unit is linearly fixed on the linear guide mechanism, and the other grabbing unit is linearly fixed on the linear guide mechanism. The other grabbing units are movably connected with the linear guide mechanism; every two adjacent grabbing units are connected with the two ends of the corresponding displacement pull rod correspondingly, and one grabbing unit and one end of the corresponding displacement pull rod move linearly in a limited mode. The two grabbing units located at the two ends of the N grabbing units are connected with the two ends of the linear driver correspondingly. A packaging box with a smaller size is allowed to be used, and the space utilization rate of a production line is increased; idle stroke can be eliminated, the takt efficiency is high, and the material boxing efficiency is greatly improved; and the device can adapt to materials with different dimensions.

The application discloses a Transformer large model reasoning task driving method and device and a medium, relates to the field of artificial intelligence, and realizes the improvement of reasoning throughput and the reduction of first word delay when executing a reasoning task at low deployment cost. A plurality of computing unit groups are assigned to a plurality of reasoning tasks, shared model parameters are obtained from an external memory and broadcast to each computing unit group for input projection, key-value cache data is obtained, and the key-value cache data is written back to the external memory; the attention calculation result is output projected and fed forward network pipeline calculated; the key-value cache data of each reasoning task is obtained from the external memory and broadcast to the corresponding computing unit group, so that each computing unit group performs attention calculation on the assigned reasoning task according to the key-value cache data. The application can reduce the dependence on high-cost high-bandwidth storage while improving the reasoning throughput and reducing the first word delay.

The application discloses a sample container supporting device, a sample container marking system based on the device and a marking method thereof. The sample container supporting device comprises a plurality of container supporting unit groups, the long edges of the container supporting unit groups are in contact with each other, and the container supporting unit groups are connected with each other through hinges. The container supporting unit group comprises a plurality of container supporting units, the side surfaces of the container supporting units are in contact with each other and are fixedly connected, thereby forming the container supporting unit group. The marking system comprises the sample container supporting device and a visual positioning laser marking instrument. The sample container is marked by using the application, the area and accuracy of the code spraying are improved, the code spraying work of multiple batches and large quantities can be completed, repeated loading, unloading and arrangement are not needed, the marking steps are reduced, the preparation and finishing work before and after the marking are reduced, and the working efficiency of the sample container marking is greatly improved.

The application discloses a kind of methods for supporting efficient verifiable query oriented to blockchain, using the disk friendly verifiable structure based on vector commitment, for the characteristics of only append write of state log, with disk block as unit organization and construction verifiable structure, and introduce vector commitment in cryptography to traditional Merkle hash tree, realize the constant level of proof size, to solve the problem that the proof overhead increases with the data to be proved when traditional Merkle hash tree is used to prove.At the same time, for the above-mentioned verifiable structure, the corresponding persistent storage scheme is proposed, combining Merkle hash tree and the characteristics of disk, solving the problem that the original Merkle hash tree is difficult to realize efficient persistence.Under as little additional storage as possible, strong reading and proof performance is realized.

An OLED display panel (100) and a display apparatus having same. The OLED display panel (100) includes a substrate (1), a pixel layer (2) and a separating and supporting layer (3). The pixel layer (2) includes a plurality of pixel-unit groups (21). The separating and supporting layer (3) includes a plurality of supporting-block groups (31). The thickness of the supporting blocks (311) is greater than the thickness of the third sub-pixels (211c). When the third sub-pixels (211c) are formed by evaporation by using a mask (101), the supporting blocks (311) are suitable to support between the substrate (1) and the mask (101), to isolate the substrate (1) and the mask (101). The supporting-block groups (31) are disposed on at least one side of the third sub-pixel (211c) of each of the pixel-unit groups (21) in the first direction.

The invention relates to the technical field of power electronic devices, in particular to a test platform of a high-frequency transformer and a control method, and the test platform comprises a primary side function unit group and a secondary side function unit group which are symmetrical in structure; the primary side function unit group and the secondary side function unit group are respectively provided with a plurality of function units; the input end of each functional unit in the primary side functional unit group is connected with an alternating current power supply; the output ends of the functional units in the primary side functional unit group are connected in series or in parallel and are used for being connected with a primary side winding of the to-be-tested high-frequency transformer; the input end of each functional unit in the secondary side functional unit group is connected with an alternating current power supply; the output ends of the functional units in the secondary functional unit group are connected in series or in parallel and are used for being connected with a secondary winding of the to-be-tested high-frequency transformer; the function unit is used for responding to the adjusting signal and outputting a target test waveform, and the technical problem that an existing test device is difficult to meet the test requirement of the high-capacity high-frequency transformer is solved.

The invention discloses a network following type energy storage unit grouping and dragging test method and system. The method comprises the steps that the real-time total charging and discharging power of a first energy storage unit group and the real-time total charging and discharging power of a second energy storage unit group are obtained; adjusting the real-time charging and discharging power of the plurality of energy storage units in the first energy storage unit group according to a first preset power distribution principle, so that the adjusted total charging and discharging power of the first energy storage unit group is equal to the real-time total charging and discharging power of the second energy storage unit group in the current control period; and adjusting the real-time charging and discharging power of the plurality of energy storage units in the second energy storage unit group according to a second preset power distribution principle, so that the adjusted total charging and discharging power of the second energy storage unit group is equal to the real-time total charging and discharging power of the first energy storage unit group in the current control period. Through power mutual aid and dynamic coordination control of the two groups of energy storage units, internal power self-balance of the test system at the branch box is realized, and the problem of power grid impact caused by overlarge charging and discharging power is avoided.

The application provides a clock tree synthesis method, comprising: obtaining a plurality of synchronous unit groups of a same target clock source; each of the synchronous unit groups comprises at least one synchronous unit; for each of the plurality of synchronous unit groups, a virtual clock source is set at a side of each synchronous unit in the synchronous unit group away from the target clock source along a common path of the synchronous unit to the target clock source; and a layout and routing tool is used to make clock delays of each synchronous unit in the synchronous unit group to the virtual clock source equal. By setting a virtual clock source on the synchronous unit groups belonging to different functional targets under the same clock source, the synchronous unit groups belonging to different functional targets under the same clock source can be synthesized independently, instead of starting from the clock source, so that the quality of the clock tree on the chip is greatly improved.

The application discloses a kind of based on specific group of units balance adjustment safety correction auxiliary decision-making method and device, obtain safety correction auxiliary decision-making basic data;According to basic data, eliminate equipment overrun quantity, and obtain unit output adjustment quantity;After equipment overrun quantity elimination succeeds, calculate group of units adjustment demand according to unit output adjustment quantity;According to group of units adjustment demand, carry out group of units within unit output balance adjustment;After adjustment succeeds, the unit output of group of units within adjusted is warehoused, simultaneously sent to AGC tracking execution.The safety correction auxiliary decision-making method and device based on specific group of units balance adjustment provided by the application provide auxiliary decision-making method for the rapid adjustment of group of units output plan under new type power system uncertainty scenario.

Embodiments of the present application provide a display panel and a display device, which relate to the technical field of display and are used for improving the pixel aperture ratio of the display panel. The first unit group and the second unit group in the display panel are arranged alternately in the first direction, the first unit group comprises a plurality of first units arranged in the second direction, and the second unit group comprises a plurality of second units arranged in the second direction; the first unit and the second unit each comprise a first sub-pixel, a second sub-pixel and a third sub-pixel; the shape of at least one of the first sub-pixel, the second sub-pixel and the third sub-pixel comprises an arc edge; in the first unit, the first sub-pixel and the third sub-pixel are arranged in the first direction, and the second sub-pixel is located on one side of the first sub-pixel and the third sub-pixel in the second direction; in the second unit, the first sub-pixel and the third sub-pixel are arranged in the first direction, and the second sub-pixel is located on the other side of the first sub-pixel and the third sub-pixel in the second direction.

The invention relates to a circuit layout method and device, computer equipment, a storage medium and a program product. The circuit layout method comprises the following steps: on the basis of a signal flow algorithm, combining circuit units meeting preset connection rules of the same type in a circuit topological structure diagram to form a unit group; different array arrangement forms of the circuit units of each unit group are determined, a plurality of local layout schemes are obtained, and each array arrangement form forms one local layout scheme; performing permutation and combination on the different local layout schemes corresponding to the plurality of unit groups to obtain a plurality of global layout schemes to be selected; and determining a target global layout scheme based on the plurality of to-be-selected global layout schemes. The full-process automation of layout design is realized, the layout efficiency is obviously improved, and the layout result is more in line with the design intention.

The invention provides a KV cache mapping method and system for computing large model decoding acceleration in an RRAM, and mainly solves the problems of insufficient KV cache computing parallelism and large cross-array communication overhead in a large model decoding stage. Request-level mapping: grouping and sorting KV caches according to attention heads, dynamically distributing the KV caches to a module unit group with the largest free space, triggering transverse expansion when resources are insufficient, and reserving 30% of space for dynamic addition; in-header fine-grained mapping: dividing a K / V matrix of a single decoder of a single header into four parts, respectively mapping the four parts to four array groups of a processing unit, and forcing K / V slices of blocks of the same decoder to be bound to the same array group; the slices of different decoders fill the array group in sequence, and parallel conflicts are eliminated; and four-array parallel computing: realizing sum operation acceleration by copying query vectors, slicing dot products and stipulating.

An element mounting system includes a plurality of production lines that produce mounting boards on which elements are mounted, one or more supply devices, and a management device that manages the supply devices. Each production line has a supply unit group arranged by a plurality of element supply units on which feeders that are element supply elements are mounted. The supply devices are movable along a plurality of movement paths that pass through the supply unit groups of the production lines. The supply devices move on the movement paths and perform a supply operation of supplying the feeders that are supply targets to each element supply unit belonging to the supply unit group based on the recovery of the feeders that run out of elements. The management device sets a group element run-out scheduled time for each of the supply unit groups of the production lines and allocates the supply devices in order from early to late of the group element run-out scheduled times, thereby determining a supply-time movement path of the supply devices. Then, the management device moves the supply devices along the supply-time movement path and causes the supply devices to perform the supply operation.

This invention provides an adaptive tuning method and system for LSM-Tree key-value indexes. The method includes: configuring a load-aware module on the index receiving side; acquiring load data through the load-aware module and calculating the write load intensity in the load data; calculating and updating the maximum lazy layer based on the write load intensity; adjusting the storage index balancing strategy and tiering strategy adapted to the write load intensity using the maximum lazy layer based on the actual write load intensity; configuring multiple Bloom filter units for shards, generating Bloom filter unit groups, calculating the bit length index of the Bloom filter unit groups for shards, and controlling the number of Bloom filter unit functions based on the adaptation relationship between the bit length index of the Bloom filter unit groups and the actual write load; and embedding the index into the storage index for key-value access based on the adapted storage index balancing strategy and tiering strategy, and the adapted Bloom filter units.

The utility model discloses a ceramic membrane assembly and a unit group applying the ceramic membrane assembly, and belongs to the field of beer filtration, the ceramic membrane assembly comprises a water receiving chassis, twelve single membrane groups and two empty membrane groups, the top of the water receiving chassis is provided with a frame, the twelve single membrane groups are connected in series through six communicating pipes, and the two empty membrane groups are communicated with the frame. The inner wall of each single membrane group is fixedly connected with a clear liquid outlet a, the side wall of the water receiving chassis is provided with a booster pump, the input end of the booster pump is fixedly connected with a membrane group inlet, the output end of the booster pump is fixedly connected with a flow guide channel, and two clear liquid upper outlet pipelines are communicated between the two empty membrane groups and the twelve single membrane groups. The inner wall of the upper clear liquid outlet pipeline is fixedly connected with a lower clear liquid outlet pipeline; by arranging twelve groups of single membrane groups and adopting a 2-serial * 6-parallel topological structure, and arranging two empty membrane groups at the tail end, the volume in the circulating pipe is effectively enlarged, the water hammer is reduced, the filtering time is prolonged, and the filtering efficiency is ensured.

The present application relates to a heat dissipation buckle structure, having a frame, a heat sink, a cover; the frame upper side has an opening and an abutting portion, the lower side periphery extends a plurality of supports and jointly defines a reciprocating space, and the opening and the reciprocating space are mutually communicated, and the supports are arranged on the side of a heat source; the heat sink has an upper side and a lower side, and at least one through hole is arranged at the four corners, the heat sink is arranged in the reciprocating space of the frame, and the upper side protrudes out of the opening; a plurality of screw lock assemblies with elastic components are correspondingly arranged in the through holes, and the heat sink is arranged above the heat source; the cover is correspondingly arranged on the upper side of the frame, at least one folded edge is vertically arranged on the side of the cover, and the folded edge has an abutting portion; the operating unit group is arranged on the upper side of the heat sink, the abutting portion of the cover can be moved by the operating unit group, the cover can be shielded from the screw lock assembly, and the heat sink can be close to or away from the heat source.

The application provides a semiconductor test structure and a preparation method thereof, and belongs to the technical field of semiconductors. A to-be-tested unit group comprises at least one to-be-tested unit. The to-be-tested unit comprises an active region, a gate structure and a source-drain epitaxial layer. The gate structure is located on a channel region of the active region, and the source-drain epitaxial layer is located in a source region and a drain region of the active region. The widths of all the active regions along a first direction are equal. The sum of the areas of all the channel regions in each to-be-tested unit group is equal. From the first to-be-tested unit group to the nth to-be-tested unit group, the widths of the active regions, the channel regions and the gate structures along a second direction gradually increase, and the widths of each source region and drain region along the second direction are equal. The application can effectively monitor edge defects of the gate structure, thereby avoiding problems in high-temperature life tests of devices and shortening the development time.

The invention discloses a matrix block storage method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps: obtaining the number of non-zero sub-matrix blocks of each candidate recovery unit group and the overwriting frequency of each non-zero sub-matrix block; and based on the overwriting frequency, sorting the non-zero sub-matrix blocks to obtain an overwriting frequency sorting value of each non-zero sub-matrix block. For each non-zero sub-matrix block, a candidate recovery unit group of each non-zero sub-matrix block can be determined according to an overwriting frequency sorting value of the non-zero sub-matrix block and the number of the non-zero sub-matrix blocks of each candidate recovery unit group, and the non-zero sub-matrix blocks are stored in the corresponding candidate recovery unit groups. Therefore, the non-zero sub-matrix blocks with different overwriting frequencies are placed in different candidate recovery unit groups, the non-zero sub-matrix blocks with higher overwriting frequencies can be recovered more frequently, but most of the data are to-be-covered data, namely, the proportion of junk data is lower, so that the generation of the junk data can be reduced.

The present application provides an address mapping unit that efficiently looks up a data descriptor of a cache unit. The address mapping unit comprises a plurality of register groups, the plurality of register groups correspond to a plurality of data block descriptor groups, the plurality of data block descriptor groups correspond to a plurality of cache unit groups, and each cache unit group comprises at least one cache unit; each register group comprises a group base address register, a group base index register and a data block descriptor mode register, and the address mapping unit accesses one of the plurality of register groups according to a group serial number of a cache unit group where the cache unit index is located to obtain a first group base address, a first group base index and a first data block descriptor mode; and calculating a data descriptor address corresponding to the cache unit index according to the cache unit index, the first group of base addresses, the first group of base indexes and the first data block descriptor mode. According to the application, mapping from the cache unit index to the data descriptor address can be realized based on the address mapping unit, hardware resources are reasonably utilized, and the cost is controlled.