Ferroelectric memory, reading method and electronic equipment

Abstract

The invention discloses a ferroelectric memory, a reading method and electronic equipment, the ferroelectric memory comprises a plurality of word lines, a plurality of bit lines and a plurality of ferroelectric memory units, a first ferroelectric memory unit and a second ferroelectric memory unit which are connected with the same word line form a unit group, so that a plurality of unit groups are divided; in any unit group, at least one bit line is arranged between the bit line connected with the first ferroelectric storage unit and the bit line connected with the second ferroelectric storage unit, so that the bit line between the bit lines connected with the first ferroelectric storage unit and the second ferroelectric storage unit is used as a shielding line, the problem of mutual coupling when the bit lines read signals is solved, and the signal reading efficiency is improved. And the signal reading accuracy is improved. Moreover, in the two adjacent unit groups connected to the same word line, the bit line connected with the first ferroelectric storage unit in one unit group is adjacent to the bit line connected with the second ferroelectric storage unit in the other unit group, so that the density of the ferroelectric storage units can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a ferroelectric memory, a reading method and an electronic device. BACKGROUND

[0002] Ferroelectric memory (FeRAM) is a non-volatile memory, and has the advantages of high-speed reading and writing, high-density storage, low power consumption and radiation resistance, and can be widely applied to electronic devices.

[0003] The ferroelectric memory can include a plurality of ferroelectric memory cells, and the signals read out from the plurality of ferroelectric memory cells can be input to a comparator through a multiplexer, so as to identify the read-out signals as '1' or '0' by using the comparator. Generally, the ferroelectric memory cells are connected to the comparator through bit lines, and when the signals of the plurality of ferroelectric memory cells are read at the same time, the signals read out by the adjacent bit lines can be mutually coupled, which affects the identification result. SUMMARY

[0004] The present application provides a ferroelectric memory, a reading method and an electronic device, so as to improve the mutual coupling problem of the signals read out by the adjacent bit lines, and improve the accuracy of signal reading.

[0005] In a first aspect, an embodiment of the present application provides a ferroelectric memory, which includes a plurality of word lines, a plurality of bit lines, and a plurality of ferroelectric memory cells, wherein each of the plurality of ferroelectric memory cells is connected to one of the plurality of word lines and one of the plurality of bit lines. And the ferroelectric memory cells connected by any word line can include alternately arranged first ferroelectric memory cells and second ferroelectric memory cells, one first ferroelectric memory cell and one second ferroelectric memory cell connected by the same word line form a cell group, thereby dividing a plurality of cell groups, and in any cell group, the bit line connected by the first ferroelectric memory cell and the bit line connected by the second ferroelectric memory cell are separated by at least one bit line. Therefore, for any cell group, when the first ferroelectric memory cell and the second ferroelectric memory cell are read, the bit line between the bit line connected by the first ferroelectric memory cell and the bit line connected by the second ferroelectric memory cell can be used as a shielding line, thereby reducing the mutual coupling problem of the signals read out by the bit lines, and improving the accuracy of signal reading. And in the adjacent two cell groups connected to the same word line, the bit line connected by the first ferroelectric memory cell in one cell group is adjacent to the bit line connected by the second ferroelectric memory cell in the other cell group, based on which the density of the ferroelectric memory cells can be improved.

[0006] In some embodiments, in any unit group, a bit line connected to the first ferroelectric memory cell and a bit line connected to the second ferroelectric memory cell are separated by a bit line. In this way, the number of bit lines can be reduced as much as possible.

[0007] In some embodiments, the plurality of word lines includes a first word line and a second word line adjacent to each other, the first ferroelectric memory cell connected to the first word line corresponds to the second ferroelectric memory cell connected to the second word line one by one, and the corresponding first ferroelectric memory cell and the corresponding second ferroelectric memory cell are connected to the same bit line. In this way, the corresponding first ferroelectric memory cell and the corresponding second ferroelectric memory cell can share the same bit line, and the number of bit lines used can be further reduced.

[0008] In some embodiments, each ferroelectric memory cell includes a transistor and a ferroelectric capacitor, wherein the gate of the transistor is connected to the corresponding word line, the first pole of the transistor is connected to the corresponding bit line, and the second pole of the transistor is connected to the ferroelectric capacitor. In this way, the transistor can be controlled to be turned on and turned off to write and read the information stored in the ferroelectric capacitor. In addition, the plurality of word lines can extend in a first direction and be arranged in a second direction, and the plurality of bit lines can extend in the second direction and be arranged in the first direction, so that the word lines and the bit lines are arranged in a perpendicular arrangement. Based on this, the channel of the transistor in each ferroelectric memory cell can also be arranged to extend in the second direction, so that the channel of each transistor does not need to be additionally inclined, and the process difficulty can be reduced.

[0009] For example, the transistor can be a horizontal transmission transistor (for example, Fin Field Effect Transistor (FinFET), Gate all around Field Effect Transistor (GAAFET)), or a vertical transmission field effect transistor (Vertical Transport Field Effect Transistor (VTFET)).

[0010] For example, the ferroelectric capacitor can have a first electrode, a second electrode, and a ferroelectric functional layer arranged between the first electrode and the second electrode. In some embodiments, the ferroelectric capacitor can be a stacked structure, and in other embodiments, the ferroelectric capacitor can also be a columnar electrode, for example, the second electrode is a columnar electrode, the ferroelectric functional layer surrounds the bottom and the sidewall of the second electrode, and the first electrode surrounds the ferroelectric functional layer.

[0011] Exemplarily, the channel has a channel region, and a first source-drain region and a second source-drain region located on two sides of the channel region, the first source-drain region is connected to a corresponding bit line, the second source-drain region is connected to a first electrode of the ferroelectric capacitor, and a corresponding word line covers the channel through a gate dielectric layer to form a gate electrode. In this way, the gate electrode can be formed by using the word line, so that the gate electrode does not need to be formed by using other additional structures, thereby reducing the area occupied by the gate electrode. It can be understood that the first source-drain region and the second source-drain region can be heavily doped regions, so as to facilitate signal transmission.

[0012] In some embodiments, the channels of the transistors connected to the same bit line can be arranged in sequence along the second direction, so that the part of the channels can be arranged closely, thereby reducing the area occupied by the channels.

[0013] In some embodiments, the ferroelectric capacitors connected to the transistors connected to the same bit line can be arranged in sequence along the second direction. In this way, the ferroelectric capacitors connected to all the transistors connected to the same bit line can be arranged in sequence along the second direction, and the ferroelectric capacitor in each ferroelectric storage unit can be arranged correspondingly to the second source-drain region connected thereto, so as to arrange the ferroelectric capacitors uniformly.

[0014] In some embodiments, in order to further improve the density of the ferroelectric storage unit, when the plurality of word lines include adjacent first word lines and second word lines, the first ferroelectric storage units connected to the first word lines can correspond to the second ferroelectric storage units connected to the second word lines, the first source-drain regions of the transistors in the first ferroelectric storage units and the second ferroelectric storage units corresponding to each other can be arranged in the same region, so that the first source-drain regions of the transistors in the first ferroelectric storage units and the second ferroelectric storage units corresponding to each other are shared, thereby further reducing the area occupied by the channels, and the channels of the transistors connected to adjacent two bit lines can be arranged in a staggered manner.

[0015] Exemplarily, the plurality of word lines, the plurality of bit lines, and the plurality of ferroelectric storage units are arranged on a substrate, and the substrate can be a semiconductor substrate or a substrate of other insulating material.

[0016] In some embodiments, the second source-drain region connected to any ferroelectric capacitor and the normal projection of the substrate on the second source-drain region can have an overlapping region. In this way, the ferroelectric capacitors connected to all the transistors connected to the same bit line can be arranged in sequence along the second direction, and the ferroelectric capacitor in each ferroelectric storage unit can be arranged correspondingly to the second source-drain region connected thereto, so as to arrange the ferroelectric capacitors uniformly.

[0017] In some embodiments, the ferroelectric memory further comprises a plurality of plate lines, the plate lines are arranged at a layer between the layer where the word lines are arranged and the layer where the bit lines are arranged, and the second electrode of the ferroelectric capacitor in each ferroelectric memory cell is connected to a plate line of the plurality of plate lines. In this way, the plate line can be used to transmit signals to the second electrode of the ferroelectric capacitor.

[0018] In some embodiments, the ferroelectric capacitor of the first ferroelectric memory cell and the second ferroelectric memory cell in any cell group can be connected to the same plate line, so that part of the memory cells share the same plate line, thereby reducing the number of plate lines.

[0019] In some embodiments, the ferroelectric capacitors in different cell groups connected to the same word line can also be connected to different plate lines, in this way, signals can be transmitted to adjacent cell groups by different plate lines, so that all or part of the ferroelectric memory cells can be read when any word line is selected, thereby improving the degree of freedom of the read operation.

[0020] In some embodiments, in order to further reduce the number of plate lines, when the plurality of word lines comprises adjacent first word lines and second word lines, the plurality of cell groups connected to the first word lines comprises a first cell group, the plurality of cell groups connected to the second word lines comprises a second cell group, and the bit line connected to the first ferroelectric memory cell in the second cell group is between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first cell group, thereby the ferroelectric capacitors in the first cell group and the second cell group connected to different word lines can share the same plate line, and the number of plate lines can be further reduced.

[0021] In some embodiments, when the plate line is connected to a plurality of ferroelectric capacitors, due to the staggered arrangement of the transistor channels, sufficient space can be reserved for the plate line to be arranged in an inclined direction. Based on the staggered arrangement of the channels, the ferroelectric capacitors in different ferroelectric memory cells can form a unique ladder-shaped arrangement in the direction from the upper left to the lower right, so that the plate line can be arranged in a ladder-shaped extension. Alternatively, based on the ladder-shaped arrangement of the ferroelectric capacitors, the plate line can also be arranged in a straight line extending in an inclined direction. In addition, based on the ladder-shaped arrangement of the ferroelectric capacitors, the plate line can also avoid blocking the contact hole where the first conductive part is arranged, and the plate line can also avoid being short-circuited with the bit line.

[0022] In some embodiments, in any cell group, the ferroelectric capacitors in the first ferroelectric memory cell and the second ferroelectric memory cell are connected to different plate lines. In this way, the first ferroelectric memory cell and the second ferroelectric memory cell in the same cell group can transmit signals by different plate lines.

[0023] In some embodiments, the ferroelectric capacitors in the first ferroelectric memory cell and the second ferroelectric memory cell connected to the same word line are connected to different plate lines. In this way, the first ferroelectric memory cell and the second ferroelectric memory cell corresponding to the same word line can be respectively transmitted signals by different plate lines.

[0024] In some embodiments, in order to reduce the number of plate lines, when the plurality of word lines include adjacent first and second word lines, the plurality of cell groups connected to the first word line include a first cell group, the plurality of cell groups connected to the second word line include a second cell group, and the bit line connected to the first ferroelectric memory cell in the second cell group is between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first cell group, so that the ferroelectric capacitors in the first ferroelectric memory cell in the first cell group and the first ferroelectric memory cell in the second cell group can be connected to the same plate line, thereby reducing the number of plate lines.

[0025] In some embodiments, due to the staggered arrangement of the transistor channels, sufficient space for plate line wiring can be reserved when connecting a plurality of ferroelectric capacitors. For example, based on the staggered arrangement of the channels, the ferroelectric capacitors in different ferroelectric memory cells can form a unique straight line extending in a direction intersecting both the first direction and the second direction from the upper left to the lower right.

[0026] In some embodiments, the plurality of plate lines are divided into a plurality of plate line groups, wherein each plate line group includes two adjacent plate lines. And the two plate lines in each plate line group are electrically connected to each other, and the plate lines in different plate line groups are insulated from each other.

[0027] Further, the two plate lines in any plate line group can be connected to each other by a connection line.

[0028] In some embodiments, the ferroelectric capacitors in the ferroelectric memory cells corresponding to the same word line can be connected to the same plate line, and the ferroelectric capacitors in the ferroelectric memory cells corresponding to different word lines are connected to different plate lines.

[0029] In some embodiments, based on the stepped arrangement of the ferroelectric capacitors and the staggered arrangement of the transistor channels, sufficient connection line space can be reserved for plate line wiring, so that the plate lines form a zigzag line extending in the first direction.

[0030] In a second aspect, the embodiments of the present application also provide an electronic device, which includes a circuit board and a ferroelectric memory, and the ferroelectric memory is arranged on the circuit board. Wherein, the ferroelectric memory is the ferroelectric memory in the first aspect or the embodiments of the first aspect. And the technical effects of the corresponding solutions in the second aspect can refer to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repeated parts will not be described in detail.

[0031] In a third aspect, the embodiments of the present application further provide a reading method of a ferroelectric memory. The ferroelectric memory comprises a plurality of word lines, a plurality of bit lines, and a plurality of ferroelectric memory cells. Each of the plurality of ferroelectric memory cells is connected to one of the plurality of word lines and one of the plurality of bit lines. The ferroelectric memory cells connected to any word line comprise first ferroelectric memory cells and second ferroelectric memory cells arranged alternately. One first ferroelectric memory cell and one second ferroelectric memory cell connected to the same word line form a cell group. In any cell group, there is at least one bit line between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. In the adjacent two cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group. The method comprises: selecting any word line of the plurality of word lines, controlling the bit lines connected to at least part of the ferroelectric memory cells connected to the selected word line to be floating, and controlling the bit lines not connected to the ferroelectric memory cells to input a fixed potential. Thus, for any cell group, when reading the first ferroelectric memory cell and the second ferroelectric memory cell, the bit line between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell can be used as a shielding line, thereby reducing the mutual coupling problem of the bit line readout signal and improving the accuracy of signal reading.

[0032] The ferroelectric memory of the embodiments of the present application can be used as a ferroelectric memory of a 1T1C array or a 2T2C array.

[0033] In addition, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be written in whole or in part, thereby improving the degree of freedom of the write operation.

[0034] In addition, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be read in whole or in part, thereby improving the degree of freedom of the read operation. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a structural schematic diagram of an electronic device in the embodiments of the present application;

[0036] Figure 2a FIG. 6 is a schematic diagram of the movement of electric charges in a ferroelectric capacitor;

[0037] Figure 2b FIG. 7 is another schematic diagram of the movement of electric charges in a ferroelectric capacitor;

[0038] Figure 3 FIG. 8 is a graph of the relationship between the coercive field voltage and the residual polarization charge amount;

[0039] Figure 4 FIG. 9 is a circuit diagram of a 1T1C ferroelectric memory cell in the related art;

[0040] Figure 5 is a timing diagram of a ferroelectric memory cell in the related art; Figure 4

[0041] Figure 6 is a circuit diagram of a 2T2C ferroelectric memory cell in the related art;

[0042] Figure 7 is a schematic diagram of a bit line in an embodiment of the present application;

[0043] Figure 8 is a circuit diagram of a ferroelectric memory in an embodiment of the present application;

[0044] Figure 9 is a schematic diagram of a cell group composed of ferroelectric memory voltages shown in Figure 8

[0045] is a layout structure diagram corresponding to the circuit diagram shown in Figure 10 Figure 8 is a layout structure diagram corresponding to the circuit diagram shown in

[0046] Figure 11 Figure 10 is a schematic diagram of a cross-sectional structure in the layout structure diagram shown in

[0047] Figure 12 is a circuit diagram of another ferroelectric memory in an embodiment of the present application;

[0048] Figure 13 is a layout structure diagram corresponding to the circuit diagram shown in Figure 12

[0049] is a schematic diagram of a cross-sectional structure in the layout structure diagram shown in Figure 14 Figure 13 is a circuit diagram of another ferroelectric memory in an embodiment of the present application;

[0050] Figure 15 is a layout structure diagram corresponding to the circuit diagram shown in

[0051] Figure 16 Figure 15 is a circuit diagram of another ferroelectric memory in an embodiment of the present application;

[0052] Figure 17 is a circuit diagram of another ferroelectric memory in an embodiment of the present application;

[0053] Figure 18 is a layout structure diagram corresponding to the circuit diagram shown in Figure 17 DETAILED DESCRIPTION

[0054] ​​​​​​In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "a plurality of" can be understood as "at least two". In addition, it should be understood that in the description of the present application, "first", "second", etc. are used only for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0055] It should be noted that the same reference signs in the drawings of the present application represent the same or similar structures, and thus repeated description thereof will be omitted. The expressions of position and direction described in the present application are described with reference to the drawings, but changes can also be made as needed, and the changes made are all included in the protection scope of the present application. The drawings of the present application are only used to show the relative position relationship and do not represent the true proportion.

[0056] The storage scheme provided by the embodiments of the present application can be widely applied in devices with storage function, for example, it can be applied to storage devices with only storage function, such as ferroelectric memory, and can also be applied to electronic devices with storage function and other functions (such as read-write function). The electronic device can be a terminal device, for example, a portable electronic device containing functions such as personal digital assistant and / or music player, such as a mobile phone, a tablet computer, a wearable device with wireless communication function (such as a smart watch), or a vehicle-mounted device, etc. Exemplary embodiments of the terminal device include, but are not limited to, portable electronic devices running Android operating system or other operating systems. The terminal device can also be a laptop (Laptop) with a touch-sensitive surface (such as a touch panel), and it should be understood that in some other embodiments of the present application, the above-mentioned electronic device can also be a desktop computer with a touch-sensitive surface (such as a touch panel). The terminal device can also be a laptop (Laptop) with a touch-sensitive surface (such as a touch panel), and it should be understood that in some other embodiments of the present application, the above-mentioned electronic device can also be a desktop computer with a touch-sensitive surface (such as a touch panel).

[0057] Figure 1 An exemplary structure schematic diagram of an electronic device is shown. Referring to Figure 1The electronic device includes a housing 100 and a circuit board 200 disposed in the housing 100, and the circuit board 200 is provided with a processor 400 and a memory 300. The memory 300 can be used to store computer executable program codes, which can include instructions. The processor 400 executes the instructions stored in the memory 300 to perform various functional applications and data processing of the electronic device. In some embodiments, the memory 300 can also save instructions or data that the processor 400 has just used or recycled. If the processor 400 needs to use the instructions or data again, it can be directly called from the memory 300, avoiding repeated access and reducing the waiting time of the processor, thereby improving the working efficiency of the mobile phone.

[0058] The ferroelectric memory has the advantages of high-speed reading and writing, high-density storage, low power consumption, and radiation resistance, and the memory 300 can be a ferroelectric memory. The ferroelectric memory generally includes a ferroelectric storage cell, and the ferroelectric storage cell has a ferroelectric capacitor. Referring to Figure 2a And Figure 2b , Figure 2a An example shows a schematic diagram of the movement of charges in a ferroelectric capacitor, Figure 2b An example shows another schematic diagram of the movement of charges in a ferroelectric capacitor. The ferroelectric capacitor can include a first electrode 11, a second electrode 12, and a ferroelectric functional layer 13 disposed between the first electrode 11 and the second electrode 12. The ferroelectric functional layer 13 can generate polarization according to the direction and size of the applied electric field. After the electric field is removed, part of the polarization can still be maintained, which is called residual polarization. Because of the existence of the residual polarization charge Pr, the residual polarization has a potential difference. In order to balance the potential difference, the first electrode 11 and the second electrode 12 can induce opposite induced charges. Because the residual polarization does not disappear after the electric field is removed, the induced charges can also be maintained on the first electrode 11 and the second electrode 12. The ferroelectric memory can read the induced charges to achieve non-volatile information storage.

[0059] Figure 3 An example shows a graph of the relationship between the coercive field voltage and the residual polarization charge amount. Referring to Figure 3 When a reverse electric field is applied and the electric field strength exceeds the coercive field, the polarization flips. The information stored in the capacitor C can be read by identifying the amount of charge released during the flipping of the ferroelectric capacitor C. The central voltage of the ferroelectric polarization flipping process is called the coercive voltage Vc. In order to ensure the reliability of the information stored in the ferroelectric capacitor C, the ferroelectric functional layer 13 should be fully flipped, and the potential difference input to the first electrode and the second electrode in the writing stage and the reading stage should be 2-4 times the coercive voltage Vc.

[0060] Figure 4An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 4 The ferroelectric memory can include a word line WL, a bit line BL, a plate line PL, and a plurality of ferroelectric memory cells each including at least one ferroelectric capacitor C and at least one transistor T. The gate of the transistor T is electrically connected to the word line WL, the first electrode of the ferroelectric capacitor C is electrically connected to the first electrode of the transistor T, and the second electrode of the transistor T is electrically connected to the bit line BL.

[0061] Figure 5 An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 4 An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 4 An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 5 Taking writing "1" and reading "1" as an example,

[0062] In the writing phase, the potential on the word line WL is high (e.g., 1.5 V), and the transistor T is turned on. The potential on the plate line PL is high (e.g., 1 V), and the potential on the bit line BL is low (e.g., 0 V), so that "0" can be written into the ferroelectric capacitor in the ferroelectric memory cell. Then, the potential on the plate line PL is low, and the potential on the bit line BL is high, so that "1" can be written into the ferroelectric capacitor in the ferroelectric memory cell.

[0063] In the reading phase, the potential on the word line WL is high, and the transistor T is turned on. The potential on the plate line PL is high, and the bit line BL is floating, so that the charge in the ferroelectric functional layer 13 is flipped and released as a reading signal. The flipped charge passes through the bit line capacitor C BL The reading signal is input in the form of voltage to a multiplexer and then to a sense amplifier (SA) through the multiplexer. The sense amplifier SA can compare the reading signal with a reference voltage Vref to identify that the reading signal is "1", and can also amplify the reading signal.

[0064] An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 4 An exemplary circuit diagram of a 1T1C ferroelectric memory cell is shown in FIG. 1, and an exemplary timing diagram of the ferroelectric memory cell is shown in FIG. 2. Figure 5 Taking writing "0" and reading "0" as an example,

[0065] In the writing phase, the potential on the word line WL is high (e.g., 1.5 V), and the transistor T is turned on. The potential on the plate line PL is high (e.g., 1 V), and the potential on the bit line BL is low (e.g., 0 V), so that "0" can be written into the ferroelectric capacitor in the ferroelectric memory cell.

[0066] In the reading stage: the potential on the word line WL is high, the transistor T is turned on. The potential on the plate line PL is high, the bit line BL is floating. Since the direction of the electric field applied on the first electrode 11 and the second electrode 12 in the writing stage and the reading stage does not change, the charge in the ferroelectric functional layer 13 does not flip, and no charge is released. The bit line BL transmits the reading signal of the unreleased charge to the multiplexer, and the reading signal is input to the comparator SA through the multiplexer. The comparator SA can compare the reading signal with the reference voltage Vref to identify that the reading signal is "0".

[0067] Exemplarily, in the case that the ferroelectric memory cell can work normally, the comparator SA can determine that the reading signal is "1" through the comparison result that "the reading signal is greater than the reference voltage Vref"; otherwise, the comparator SA can determine that the reading signal is "0" through the comparison result that "the reading signal is less than the reference voltage Vref".

[0068] Figure 6 Exemplarily, the circuit diagram of the 2T2C ferroelectric memory cell is shown, referring to Figure 6 Two 1T1C ferroelectric memory cells are combined into one memory cell. In the writing stage: the potential on the word line WL is high, both transistors T are turned on. The potential on the plate line PL is high, the potential on the bit line BL is low, and "0" can be written into the two ferroelectric memory cells first. Then, the potential on the plate line PL is low, the potential on the bit line BL1 is high, the ferroelectric memory cell connected by the bit line BL1 writes "1", and the ferroelectric memory cell connected by the bit line BL2 still keeps "0". In the reading stage: the potential on the word line WL is high, the transistor T is turned on. The potential on the plate line PL is high, the bit line BL is floating. The charge in the ferroelectric functional layer 13 of the ferroelectric memory cell connected by the bit line BL1 flips and releases the flipped charge as the first reading signal. The charge in the ferroelectric functional layer 13 of the ferroelectric memory cell connected by the bit line BL2 does not flip and does not release the charge. The bit line BL1 transmits the first reading signal to the multiplexer, the bit line BL2 transmits the second reading signal of the unreleased charge to the multiplexer, and the first reading signal and the second reading signal can be compared with each other as the reference to determine that the first reading signal is "1" and the second reading signal is "0".

[0069] Compared with the 1T1C ferroelectric memory, the 2T2C ferroelectric memory can determine that the first read signal is "1" and the second read signal is "0" without the reference voltage Vref. Moreover, the difference between the first read signal and the second read signal is twice the difference between the first read signal and the reference voltage Vref and the difference between the second read signal and the reference voltage Vref, which can more accurately determine that the first read signal is "1" and the second read signal is "0". However, compared with the 2T2C ferroelectric memory, the layout area of each memory cell in the 1T1C ferroelectric memory is smaller, which is half of the 2T2C ferroelectric memory.

[0070] Because the bit line needs to be floating during the reading process, the bit line signal is disturbed by the voltage fluctuation of the surrounding environment due to coupling, thereby causing the sense margin to decrease. One of the stronger disturbances is the coupling between adjacent bit lines. For example, for a certain bit line, the potential of the surrounding bit lines during reading depends on the type of stored information. Referring to Figure 7 , Figure 7 An exemplary schematic diagram of 4 bit lines is shown. For the bit line BL1, when the surrounding bit lines BL2-BL4 are all high potentials, the surrounding bit lines BL2-BL4 increase the potential of the bit line BL1 (enhance "1" and weaken "0"). When the surrounding bit lines BL2-BL4 are all low potentials, the surrounding bit lines BL2-BL4 decrease the potential of the bit line BL1 (enhance "0" and weaken "1"). Moreover, as the device miniaturization process advances, the distance between the bit lines becomes closer, and the coupling problem between the bit lines becomes more serious.

[0071] Therefore, an embodiment of the present application provides a ferroelectric memory. The ferroelectric memory can include a plurality of word lines, a plurality of bit lines, and a plurality of ferroelectric memory cells. Each of the plurality of ferroelectric memory cells is connected to one of the plurality of word lines and one of the plurality of bit lines. Moreover, each of the plurality of word lines is connected to a plurality of ferroelectric memory cells. Any word line connected ferroelectric memory cells include a plurality of cell groups. Each of the cell groups includes two ferroelectric memory cells. The two ferroelectric memory cells include a first ferroelectric memory cell and a second ferroelectric memory cell arranged in sequence. In any cell group, at least one bit line is arranged between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. Thus, for any cell group, when reading the first ferroelectric memory cell and the second ferroelectric memory cell, the bit line between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell can be used as a shielding line, thereby reducing the mutual coupling problem of the bit line readout signal and improving the accuracy of signal reading.

[0072] Figure 8An exemplary circuit diagram of a ferroelectric memory according to an embodiment of this application is shown, with reference to... Figure 8 The ferroelectric memory provided in this application embodiment may include: a substrate and multiple word lines WL1 to WL6, multiple bit lines BL1 to BL8, and multiple ferroelectric memory cells A disposed on the substrate. 11 ~A 67 Among them, ferroelectric memory cell A 11 ~A 18 Connected to word line WL1, ferroelectric memory cell A 22 ~A 28 Connected to word line WL2, ferroelectric memory cell A 31 ~A 37 Connected to word line WL3, ferroelectric memory cell A 41 ~A 48 Connected to word line WL4, ferroelectric memory cell A 52 ~A 58 Connected to word line WL5, ferroelectric memory cell A 61 ~A 67 Connected to word line WL6. Furthermore, ferroelectric memory cell A 11 ~A 61 Connected to bit line BL1, ferroelectric memory cell A 12 ~A 52 Connected to bit line BL2, ferroelectric memory cell A 23 ~A 63 Connected to bit line BL3, ferroelectric memory cell A 14 ~A 64 Connected to bit line BL4, ferroelectric memory cell A 15 ~A 55 Connected to bit line BL5, ferroelectric memory cell A 26 ~A 66 Connected to bit line BL6, ferroelectric memory cell A 17 ~A 67 Connected to bit line BL7, ferroelectric memory cell A 18 ~A 58 Connect to bit line BL8.

[0073] Figure 9 An example is shown Figure 8 The diagram shown is a schematic representation of a unit group composed of ferroelectric storage voltages, with reference to... Figure 8 and Figure 9 For the ferroelectric memory cell A connected by word line WL1 11 ~A 18 Ferroelectric memory cell A 11 A 14 A 17 This is the second ferroelectric memory cell, ferroelectric memory cell A. 12 A15 , A 18 is a first ferroelectric memory cell, and the ferroelectric memory cell A 12 is connected to the ferroelectric memory cell A 14 to form a cell group Zl, the ferroelectric memory cell A 12 is connected to the ferroelectric memory cell A 14 is spaced apart from the bit line BL4 connected to the ferroelectric memory cell A 12 and A 14 , the bit lines BL2 and BL4 are called to transmit signals, and the bit line BL3 is not called, so that a fixed potential can be input to the bit line BL3 through a peripheral driving circuit, and the bit line BL3 is used as a shield line of the bit lines BL2 and BL4 to reduce coupling interference between the bit lines BL2 and BL4. Also, the ferroelectric memory cell A 15 and the ferroelectric memory cell A 17 to form a cell group Z2, the ferroelectric memory cell A 15 is connected to the ferroelectric memory cell A 17 is spaced apart from the bit line BL7 connected to the ferroelectric memory cell A 15 and A 17 , the bit lines BL5 and BL7 are called to transmit signals, and the bit line BL6 is not called, so that a fixed potential can be input to the bit line BL6 through a peripheral driving circuit, and the bit line BL6 is used as a shield line of the bit lines BL5 and BL7 to reduce coupling interference between the bit lines BL5 and BL7. In addition, the cell group Zl is disposed adjacent to the cell group Z2, and the bit line BL4 connected to the ferroelectric memory cell A 14 and the bit line BL5 connected to the ferroelectric memory cell A 15 are disposed adjacent to each other to increase the density of the ferroelectric memory cells.

[0074] For the ferroelectric memory cells A 22 ~ A 28 connected to the word line WL2, the ferroelectric memory cell A 22 , A 25 , A 28 is a second ferroelectric memory cell, and the ferroelectric memory cell A 23 , A 26 is a first ferroelectric memory cell, and the ferroelectric memory cell A 23 and the ferroelectric memory cell A 25 to form a cell group Z3, the ferroelectric memory cell A 26 and the ferroelectric memory cell A 28 to form a cell group Z4.

[0075] For the ferroelectric memory cells A 31 ~ A37 , ferroelectric memory cell A 31 , A 34 , A 37 is a first ferroelectric memory cell, and ferroelectric memory cell A 33 , A 36 is a second ferroelectric memory cell, and ferroelectric memory cell A 31 , A 33 comprise a cell group Z5, and ferroelectric memory cell A 34 , A 36 comprise a cell group Z6.

[0076] For ferroelectric memory cells A 41 ~ A 48 , ferroelectric memory cell A 41 , A 44 , A 47 is a second ferroelectric memory cell, and ferroelectric memory cell A 42 , A 45 , A 48 is a first ferroelectric memory cell, and ferroelectric memory cell A 42 , A 44 comprise a cell group Z7, and ferroelectric memory cell A 45 , A 47 comprise a cell group Z8.

[0077] For ferroelectric memory cells A 52 ~ A 58 , ferroelectric memory cell A 52 , A 55 , A 58 is a first ferroelectric memory cell, and ferroelectric memory cell A 53 , A 56 is a second ferroelectric memory cell, and ferroelectric memory cell A 53 , A 55 comprise a cell group Z9, and ferroelectric memory cell A 56 , A 58 comprise a cell group Z 10 .

[0078] For ferroelectric memory cells A 61 ~ A 67 , ferroelectric memory cell A 61 , A 64 , A 67 is a first ferroelectric memory cell, and ferroelectric memory cell A 63 , A 66 is a second ferroelectric memory cell, and ferroelectric memory cell A 61with ferroelectric memory cell A 63 constituent cell group Z 10 , with ferroelectric memory cell A 64 with ferroelectric memory cell A 66 constituent cell group Z 12 .

[0079] For the embodiment of the bit line connected with the ferroelectric memory cell in the cell group Z3~Z 12 , the embodiment of the bit line connected with the ferroelectric memory cell in the cell group Z1~Z2 can be analogously deduced, which is not described in detail herein. In addition, Figure 8 Only part of the ferroelectric memory cell region in the ferroelectric memory is shown, therefore, Figure 8 part of the cell group of the ferroelectric memory cell is not shown, however, the embodiment thereof can be analogously deduced based on the embodiment of the bit line connected with the ferroelectric memory cell in the cell group Z1~Z2, which is not described in detail herein.

[0080] It is worth mentioning that in any cell group, the bit line connected with the first ferroelectric memory cell and the bit line connected with the second ferroelectric memory cell can be further separated by two, three or more bit lines. Among them, in order to improve the density of the ferroelectric memory cell and reduce the number of bit lines, the bit line connected with the first ferroelectric memory cell and the bit line connected with the second ferroelectric memory cell in any cell group can be separated by one bit line.

[0081] In order to further reduce the number of bit lines used, a plurality of word lines can include adjacent first and second word lines, the first ferroelectric memory cell connected with the first word line and the second ferroelectric memory cell connected with the second word line correspond one by one, and the corresponding first and second ferroelectric memory cells are connected to the same bit line, so that the corresponding first and second ferroelectric memory cells share the same bit line. For example, referring to Figure 8 , the word line WL1 can be used as the first word line, the word line WL2 can be used as the second word line, the ferroelectric memory cell A 12 (i.e. the first ferroelectric memory cell) and the ferroelectric memory cell A 22 (i.e. the second ferroelectric memory cell) correspond to each other and are connected to the same bit line BL2, the ferroelectric memory cell A 15 (i.e. the first ferroelectric memory cell) and the ferroelectric memory cell A 25 (i.e. the second ferroelectric memory cell) correspond to each other and are connected to the same bit line BL5, the ferroelectric memory cell A 18 (i.e. the first ferroelectric memory cell) and the ferroelectric memory cell A 28 (i.e. the second ferroelectric memory cell) correspond to each other and are connected to the same bit line BL8.

[0082] Also, the word line WL2 can serve as the first word line, and the word line WL3 can serve as the second word line, and the ferroelectric memory cell A 23 correspond to each other and are connected to the same bit line BL3, and the ferroelectric memory cell A 33 correspond to each other and are connected to the same bit line BL6. 26 correspond to each other and are connected to the same bit line BL3, and the ferroelectric memory cell A 36 correspond to each other and are connected to the same bit line BL6.

[0083] The word line WL3 can serve as the first word line, and the word line WL4 can serve as the second word line, and the ferroelectric memory cell A 31 correspond to each other and are connected to the same bit line BL1, and the ferroelectric memory cell A 41 correspond to each other and are connected to the same bit line BL4, and the ferroelectric memory cell A 34 correspond to each other and are connected to the same bit line BL1, and the ferroelectric memory cell A 44 correspond to each other and are connected to the same bit line BL4, and the ferroelectric memory cell A 37 correspond to each other and are connected to the same bit line BL7. 47 correspond to each other and are connected to the same bit line BL7.

[0084] The word line WL4 can serve as the first word line, and the word line WL5 can serve as the second word line, and the ferroelectric memory cell A 42 correspond to each other and are connected to the same bit line BL2, and the ferroelectric memory cell A 52 correspond to each other and are connected to the same bit line BL5, and the ferroelectric memory cell A 45 correspond to each other and are connected to the same bit line BL2, and the ferroelectric memory cell A 55 correspond to each other and are connected to the same bit line BL5, and the ferroelectric memory cell A 48 correspond to each other and are connected to the same bit line BL8. 58 correspond to each other and are connected to the same bit line BL8.

[0085] The word line WL5 can serve as the first word line, and the word line WL6 can serve as the second word line, and the ferroelectric memory cell A 53 correspond to each other and are connected to the same bit line BL3, and the ferroelectric memory cell A 63 correspond to each other and are connected to the same bit line BL4, and the ferroelectric memory cell A 56 correspond to each other and are connected to the same bit line BL3, and the ferroelectric memory cell A 66The first ferroelectric memory cell A and the second ferroelectric memory cell B correspond to each other and are connected to the same bit line BL6.

[0086] Referring to Figure 8 Each ferroelectric memory cell A 11 ~A 67 may include a transistor T and a ferroelectric capacitor C. The gate of the transistor T is connected to a corresponding word line, the first electrode of the transistor T is connected to a corresponding bit line, and the second electrode of the transistor T is connected to the first electrode of the ferroelectric capacitor C. Exemplarily, the transistor can be a horizontal transmission transistor (for example, a Fin Field Effect Transistor (FinFET), a Gate all around Field Effect Transistor (GAAFET)), or a vertical transmission field effect transistor (Vertical Transport Field Effect Transistor, VTFET). Hereinafter, the transistor T is taken as an example of a FinFET.

[0087] In order to improve the density of the ferroelectric memory cell, the word line, the channel of the transistor, and the bit line can be arranged correspondingly. Exemplarily, Figure 10 As shown in the layout structure diagram, Figure 8 As shown in the layout structure diagram, Figure 11 As shown in the layout structure diagram, Figure 10 As shown in the layout structure diagram, Figure 10 With reference to Figure 11 and in combination with Figure 8 The plurality of word lines WL1-WL6 can extend along a first direction F1 and be arranged at intervals along a second direction F2, and the plurality of bit lines BL1-BL8 can extend along the second direction F2 and be arranged at intervals along the first direction F1. The first direction F1 and the second direction F2 are perpendicular, and thus arranged, the word lines and the bit lines can be arranged in a perpendicular manner. Based on this, the channel ch of the transistor in each ferroelectric memory cell can be arranged to extend along the second direction F2 respectively, so that the channel of each transistor does not need to be additionally inclined, and the process difficulty can be reduced. In addition, Figure 11 F3 in the above represents a vertical direction perpendicular to the substrate 10.

[0088] The ferroelectric capacitor in the embodiment of the present application can have a first electrode 11, a second electrode 12, and a ferroelectric functional layer 13 arranged between the first electrode 11 and the second electrode 12. In some embodiments, the ferroelectric capacitor can be a ferroelectric capacitor with a bottom electrode structure. Figure 2a and Figure 2bIn the stack structure shown, in other embodiments, the ferroelectric capacitor can also be a pillar electrode, for example, the second electrode is a pillar electrode, the ferroelectric functional layer surrounds the bottom and sidewall of the second electrode, and the first electrode surrounds the ferroelectric functional layer. In addition, the channel generally has a channel region, and a first source-drain region and a second source-drain region located on both sides of the channel region, the first source-drain region is connected to the corresponding bit line, and the second source-drain region is connected to the first electrode of the ferroelectric capacitor. The corresponding word line covers the channel through the gate dielectric layer to form a gate electrode. In this way, the word line can be used to form a gate electrode, so that no additional structure is needed to form a gate electrode, reducing the area occupied by the gate electrode. It can be understood that the first source-drain region and the second source-drain region can be heavily doped regions for signal transmission.

[0089] In specific implementation, the first source-drain region can be connected to the corresponding bit line through the first conductive part. For example, referring to Figure 10 With Figure 11 , sd A12 represents the first source-drain region of the transistor T channel in the ferroelectric storage unit A 12 , sd A22 represents the first source-drain region of the transistor T channel in the ferroelectric storage unit A 22 , the first source-drain region sd A12 (or the first source-drain region sd A22 ) is connected to the bit line BL2 through the first conductive part CK 1a , sd A42 represents the first source-drain region of the transistor T channel in the ferroelectric storage unit A 42 , sd A52 represents the first source-drain region of the transistor T channel in the ferroelectric storage unit A 52 , the first source-drain region sd A42 (or the first source-drain region sd A52 ) is connected to the bit line BL2 through the first conductive part CK 1b . The rest is the same, and the same can be applied by analogy, which is not described here. It is worth mentioning that the material of the first conductive part can be a metal material, for example, it can be one or more of copper, molybdenum, and ruthenium.

[0090] In addition, the second source-drain region can be connected to the first electrode of the corresponding ferroelectric capacitor through the second conductive part. For example, referring to Figure 10 With Figure 11 , sd B12 represents the second source-drain region of the transistor T channel in the ferroelectric storage unit A 12 , the second source-drain region sd B12 is connected to the first electrode 11 of the corresponding ferroelectric capacitor C through the second conductive part CK 2a . sd B22 represents the second source-drain region of the transistor T channel in the ferroelectric storage unit A 22The second source-drain region of the channel of the transistor T B22 Through the second conductive part CK 2b Connected to the first electrode 11 of the corresponding ferroelectric capacitor C B42 Representing the ferroelectric storage unit A 42 The second source-drain region of the channel of the transistor T B42 Through the second conductive part CK 2c Connected to the first electrode 11 of the corresponding ferroelectric capacitor C B52 Representing the ferroelectric storage unit A 52 The second source-drain region of the channel of the transistor T B52 Through the second conductive part CK 2d Connected to the first electrode 11 of the corresponding ferroelectric capacitor C The rest is the same, and the same can be applied to the above, which will not be repeated here. It is worth mentioning that the material of the second conductive part can be a metal material, for example, it can be one or more of copper, molybdenum, and ruthenium.

[0091] In some embodiments of the present application, the channels of all transistors connected to the same bit line can be arranged in the second direction F2 in turn, so that the channels can be arranged closely and the area occupied by the channels can be reduced. For example, referring to Figure 10 With Figure 11 The ferroelectric storage unit A 11 The ferroelectric storage unit A 31 The ferroelectric storage unit A 41 The ferroelectric storage unit A 61 The channels ch of the transistors T in the ferroelectric storage unit A 11 The ferroelectric storage unit A 31 The ferroelectric storage unit A 41 The ferroelectric storage unit A 61 The channels ch of the transistors T in the ferroelectric storage unit A The rest of the channels of the transistors connected to the bit line can be applied in turn, which will not be repeated here.

[0092] In order to further improve the density of the ferroelectric storage unit, when a plurality of word lines include adjacent first and second word lines, the first source-drain region of the transistors in the corresponding first and second ferroelectric storage units can be arranged in the same area, so that the first source-drain region of the transistors in the corresponding first and second ferroelectric storage units is shared, further reducing the area occupied by the channels, and the channels of the transistors connected to the adjacent two bit lines can be arranged in a staggered manner. For example, referring to Figure 8 , Figure 10 andFigure 11 When word line WL1 is used as the first word line and word line WL2 is used as the second word line, the ferroelectric memory cell A 12 transistor T in A12 ditch A12 First source leak region sd A12 With ferroelectric memory cell A 22 transistor T in A22 ditch A22 First source leak region sd A22 For the same region. When word line WL2 is the first word line and word line WL3 is the second word line, the ferroelectric memory cell A... 23 The first source / drain region of the transistor channel and the ferroelectric memory cell 33 The first source and drain regions of the transistor channel are in the same area. When word line WL3 is used as the first word line and word line WL4 is used as the second word line, the ferroelectric memory cell A... 34 The first source / drain region of the transistor channel and the ferroelectric memory cell A 44 The first source and drain regions of the transistor channel are in the same area. When word line WL4 is used as the first word line and word line WL5 is used as the second word line, the ferroelectric memory cell A... 42 transistor T in A42 ditch A42 First source leak region sd A42 With ferroelectric memory cell A 52 transistor T in A52 ditch A52 First source leak region sd A52 This is the same region. The implementation methods for the first source-drain regions of the transistors connected to the other bit lines can be deduced similarly, and will not be elaborated here.

[0093] Based on this, refer to Figure 10 In this embodiment, by extending the channels of each transistor along the second direction F2 without tilting, and arranging the word lines and bit lines in orthogonal directions, each ferroelectric memory cell requires an average of 1.5 word lines along the bit line extension direction (i.e., the second direction F2), resulting in each ferroelectric memory cell requiring at least 3 critical dimensions (CDs). Furthermore, along the word line extension direction (i.e., the first direction F1), each ferroelectric memory cell requires an average of one channel (ch), thus requiring at least 2 CDs per ferroelectric memory cell. Based on this, the layout area of ​​the ferroelectric memory cell in this embodiment can be 6F. 2 This allows for at least partial shielding of adjacent bit lines during the read phase, while also achieving a higher layout density.

[0094] Continue to refer to Figure 8 ,Figure 10 and Figure 11 For the transistors in ferroelectric memory cell A 11 , ferroelectric memory cell A 31 , ferroelectric memory cell A 41 and ferroelectric memory cell A 61 , the ferroelectric capacitors connected to the transistors are also arranged in the second direction F2 in sequence, and the ferroelectric capacitors connected to the transistors have overlapping areas with the bit line BL1 in the orthographic projection of the substrate 10, and the ferroelectric capacitors connected to the transistors have overlapping areas with the second source-drain regions connected to the transistors in the orthographic projection of the substrate 10. For the transistors in ferroelectric memory cell A 12 , ferroelectric memory cell A 22 , ferroelectric memory cell A 42 and ferroelectric memory cell A 52 , the ferroelectric capacitors connected to the transistors are also arranged in the second direction F2 in sequence, and the ferroelectric capacitors connected to the transistors have overlapping areas with the bit line BL2 in the orthographic projection of the substrate 10, and the ferroelectric capacitors connected to the transistors have overlapping areas with the second source-drain regions connected to the transistors in the orthographic projection of the substrate 10. For the transistors in ferroelectric memory cell A 23 , ferroelectric memory cell A 33 , ferroelectric memory cell A 53 and ferroelectric memory cell A 63 , the ferroelectric capacitors connected to the transistors are also arranged in the second direction F2 in sequence, and the ferroelectric capacitors connected to the transistors have overlapping areas with the bit line BL3 in the orthographic projection of the substrate 10, and the ferroelectric capacitors connected to the transistors have overlapping areas with the second source-drain regions connected to the transistors in the orthographic projection of the substrate 10. The embodiments of the remaining ferroelectric capacitors can be sequentially deduced and are not described herein. In this way, the ferroelectric capacitors connected to the transistors in the same bit line can be arranged in the second direction F2 in sequence, and the ferroelectric capacitors in each ferroelectric memory cell can be arranged in correspondence with the second source-drain regions connected to the transistors, so that the ferroelectric capacitors are uniformly arranged. Further, in order to avoid short circuit of the ferroelectric capacitors to the first conductive part, any ferroelectric capacitor can not have overlapping areas with any first conductive part in the orthographic projection of the substrate.

[0095] Continuing to refer to Figure 8 , Figure 10 and Figure 11The ferroelectric memory also includes multiple board lines PL1 to PL5. The layer containing board lines PL1 to PL5 is located between the layer containing word lines WL1 to WL6 and the layer containing bit lines BL1 to BL8. Furthermore, the second electrode 13 of the ferroelectric capacitor C in each ferroelectric memory cell is connected to one of the multiple board lines PL1 to PL5. With this configuration, the board line can be used as the second electrode 13 of the ferroelectric capacitor C to transmit signals.

[0096] In some embodiments, the ferroelectric capacitors of the first and second ferroelectric memory cells in any group of cells can be connected to the same board line, so that some memory cells share the same board line, reducing the number of board lines. For example, refer to... Figure 8 , Figure 10 as well as Figure 11 With unit groups Z1, Z2, Z5 and Z 11 For example, for cell group Z1, ferroelectric memory cell A 12 The second electrode 13 of the ferroelectric capacitor C and the ferroelectric storage cell A 14 The second electrode 13 of the ferroelectric capacitor C is connected to the plate line PL3. For cell group Z2, ferroelectric storage cell A 15 The second electrode 13 of the ferroelectric capacitor C and the ferroelectric storage cell A 17 The second electrode 13 of the ferroelectric capacitor C is connected to the plate line PL4. For cell group Z5, ferroelectric storage cell A 31 The second electrode of the ferroelectric capacitor and the ferroelectric storage cell A 33 The second electrode of the ferroelectric capacitor in the circuit is connected to plate line PL2. For unit group Z 11 Ferroelectric memory cell A 61 The second electrode of the ferroelectric capacitor and the ferroelectric storage cell A 63 The second electrode of the ferroelectric capacitor in the circuit is connected to the board line PL1. The connection method of the ferroelectric capacitors in the other unit groups to the board lines can be deduced in the same way, and will not be described in detail here.

[0097] Furthermore, the ferroelectric capacitors C in different cell groups connected to the same word line can be connected to different board lines. This configuration allows different board lines to transmit signals to adjacent cell groups, enabling the reading of all or part of the ferroelectric memory cells when any word line is selected, thus increasing the flexibility of the read operation. For example, refer to... Figure 8 , Figure 10 as well as Figure 11 Taking unit groups Z1 and Z2 as examples, the second electrode of the ferroelectric capacitor in unit group Z1 is connected to the plate line PL3, and the second electrode of the ferroelectric capacitor in unit group Z2 is connected to the plate line PL4.

[0098] To further reduce the number of plate lines, when the plurality of word lines include adjacent first and second word lines, the plurality of cell groups connected by the first word line can include a first cell group, the plurality of cell groups connected by the second word line can include a second cell group, and the bit line connected by the first ferroelectric storage cell in the second cell group is between the bit line connected by the first ferroelectric storage cell and the bit line connected by the second ferroelectric storage cell in the first cell group, so that the ferroelectric capacitors in the first and second cell groups connected by different word lines can share the same plate line, thereby reducing the number of plate lines. For example, referring to Figure 8 , Figure 9 and Figure 10 , when the word line WL1 is the first word line and the word line WL2 is the second word line, the cell group Z1 can be the first cell group connected by the word line WL1, and the cell group Z3 can be the second cell group connected by the word line WL2. The plate line connected by the cell groups Z1 and Z3 is the same plate line PL3. When the word line WL2 is the first word line and the word line WL3 is the second word line, Z3 can be the first cell group connected by the word line WL2, and Z6 can be the second cell group connected by the word line WL3. The plate line connected by the cell groups Z3 and Z6 is the same plate line PL3. When the word line WL3 is the first word line and the word line WL4 is the second word line, Z6 can be the first cell group connected by the word line WL3, and Z8 can be the second cell group connected by the word line WL4. The plate line connected by the cell groups Z6 and Z8 is the same plate line PL3. When the word line WL4 is the first word line and the word line WL5 is the second word line, Z8 can be the first cell group connected by the word line WL4, and Z 10 may be the second cell group connected by the word line WL5. The plate line connected by the cell groups Z8 and Z 10 is the same plate line PL3. The rest is the same, and the same can be applied in sequence, which will not be repeated here. Based on this, in the ferroelectric memory provided in the embodiments of the present application, there can be a plurality of plate lines (such as PL1-PL5) arranged at intervals.

[0099] In addition, when the plate line is connected to a plurality of ferroelectric capacitors, due to the staggered arrangement of the transistor channels, sufficient space can be reserved for the plate line to be arranged as an inclined fold line. For example, referring to Figure 11 , based on the staggered arrangement of the channels, the ferroelectric capacitors in different ferroelectric storage cells can form a unique stepped arrangement in the direction from the upper left to the lower right, so that the plate line (such as PL2, PL3) can be arranged as a stepped fold line. Alternatively, based on the stepped arrangement of the ferroelectric capacitors, the plate line can also be arranged as a straight line extending in an inclined direction. In addition, based on the stepped arrangement of the ferroelectric capacitors, the plate line can also avoid blocking the contact hole where the first conductive part is located, and avoid shorting the plate line and the bit line.

[0100] The ferroelectric memory of the embodiment of the present application can be used as a ferroelectric memory of a 1T1C array. And, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be written, improving the freedom of the write operation. The write process of the ferroelectric memory of the embodiment of the present application as a ferroelectric memory of 1T1C is described below in conjunction with the embodiment. Taking word line WL1 as an example, in the write stage, the potential on the word line WL1 is high, and the transistors T in the ferroelectric memory cells A 11 ~A 18 are all turned on. And, first, the potential on each plate line PL1~PL5 is set to high, and the potential on the bit lines BL1~BL8 (or the bit lines BL1, BL2, BL4, BL5, BL7, BL8) is set to low, so that the ferroelectric capacitors in the ferroelectric memory cells A 11 ~A 18 are all written with "0". Then, the potential on each plate line PL1~PL5 is set to low, and the potential on the bit lines BL2, BL5 is high, so that the ferroelectric capacitors in the ferroelectric memory cells A 12 , A 15 are written with "1" respectively, and the ferroelectric capacitors in the ferroelectric memory cells A 11 , A 14 , A 17 , A 18 are kept with "0" respectively. The rest is the same, and the specific process is not described here.

[0101] In the embodiment of the present application, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, all or part of the ferroelectric memory cells can be read, improving the freedom of the read operation. The read process of the ferroelectric memory of the embodiment of the present application as a ferroelectric memory of 1T1C is described below in conjunction with the embodiment.

[0102] Embodiment one

[0103] In the read stage, when a certain word line is selected, each plate line is called, and only the bit line connected by the transistor connected to the word line is called, and the rest of the bit lines input a fixed potential as a shield line, reducing the coupling interference between the bit lines. And, based on the process, all the ferroelectric memory cells connected to the same word line can be read, realizing the operation process of reading all the bits corresponding to the same word line.

[0104] Exemplarily, referring to Figure 8 , taking the selected word line WL1 as an example, and the ferroelectric capacitors in the ferroelectric memory cells A 12 , A 15 are written with "1" respectively, and the ferroelectric capacitors in the ferroelectric memory cells A 11 , A 14 , A 17 , A18 The ferroelectric capacitor in the ferroelectric memory cell A 11 ~A 18 The transistors T in the ferroelectric memory cell A 11 The ferroelectric capacitor in the ferroelectric memory cell A 12 The ferroelectric capacitor in the ferroelectric memory cell A 14 The ferroelectric capacitor in the ferroelectric memory cell A 15 The ferroelectric capacitor in the ferroelectric memory cell A 17 The ferroelectric capacitor in the ferroelectric memory cell A 18 The ferroelectric capacitor in the ferroelectric memory cell A

[0105] Embodiment Two

[0106] In the read phase, a specific word line can be selected from a plurality of word lines, and a plurality of plate lines (for example, a plurality of plate lines) are called, and only the bit lines connected by the transistors connected to the selected word line and the called plate lines are called, and the rest of the bit lines are inputted with a fixed potential as a shielding line to reduce the coupling interference between the bit lines. Moreover, based on the process, the ferroelectric memory cells in the plurality of cell groups connected to the same word line can be read, and the operation process of reading a plurality of bits corresponding to the same word line can be realized. The following will be described in detail in combination with a specific embodiment.

[0107] First embodiment: in the read phase, when a certain word line is selected, the first odd plate line or the first even plate line is called, and only the bit lines connected by the transistors connected to the selected word line and the called plate lines are called, and the rest of the bit lines are inputted with a fixed potential as a shielding line, so that one or more shielding lines can be respectively arranged between each called bit line, and a 100% shielding effect can be realized. Moreover, based on the process, the ferroelectric memory cells in the first odd or first even cell groups connected to the same word line can be read, and the operation process of reading a plurality of bits corresponding to the same word line can be realized.

[0108] Exemplarily, refer toFigure 8 For example, the even-numbered plate lines are called when the word line WL1 is selected, and the ferroelectric storage unit A 12 , A 15 , A 11 , A 14 , A 17 , A 18 , A 11 ~A 18 is written with "0". In the read stage, the word line WL1 is selected, and the potential on the word line WL1 is high. The transistors T in the ferroelectric storage units A 11 ~A 15 are all turned on. The even-numbered plate lines PL2 and PL4 are called, and the potentials on the plate lines PL2 and PL4 are set to high. The odd-numbered plate lines PL1, PL3, and PL5 are not called, and the plate lines PL1, PL3, and PL5 are floating. In addition, the bit lines BL1, BL5, and BL7 are floating, and the bit lines BL2, BL3, BL4, BL6, and BL8 are input with fixed potentials as shielding lines. The bit lines BL2, BL3, and BL4 can be shielding lines between the bit line BL1 and the bit line BL5, the bit line BL6 can be a shielding line between the bit line BL5 and the bit line BL7, and the functions of the remaining bit lines and shielding lines can be inferred in the same manner, which will not be described herein. Based on this, the comparator can read "0" stored in the ferroelectric storage unit A 17 through the bit line BL1, read "1" stored in the ferroelectric storage unit A 11 through the bit line BL5, and read "0" stored in the ferroelectric storage unit A 15 through the bit line BL7. The remaining bit lines can be read in the same manner, which will not be described herein.

[0109] It can be understood that in actual application, the even-numbered plate lines (for example, PL2 and PL4) can be called when the word line WL1 is selected, to read "0" stored in the ferroelectric storage unit A 17 , "1" stored in the ferroelectric storage unit A 12 , and "0" stored in the ferroelectric storage unit A 14 . Then, the odd-numbered plate lines (for example, PL1, PL3, and PL5) are called, to read "1" stored in the ferroelectric storage unit A 18"0" stored in the ferroelectric storage unit A With this arrangement, when any one of the word lines is selected, the even-numbered plate lines are called first and then the odd-numbered plate lines are called. Further, when each of the word lines is selected, the even-numbered plate lines are called first and then the odd-numbered plate lines are called. Alternatively, when a specific one of the word lines is selected from among the plurality of word lines, the even-numbered plate lines are called first and then the odd-numbered plate lines are called.

[0110] Alternatively, when the word line WL1 is selected, the odd-numbered plate lines (e.g., PL1, PL3, PL5) can be called first to read out "1" stored in the ferroelectric storage unit A 12 "0" stored in the ferroelectric storage unit A 14 "0" stored in the ferroelectric storage unit A 18 "0" stored in the ferroelectric storage unit A 11 "0" stored in the ferroelectric storage unit A 15 "1" stored in the ferroelectric storage unit A 17 "0" stored in the ferroelectric storage unit AWith this arrangement, when any one of the word lines is selected, the even-numbered plate lines are called first and then the odd-numbered plate lines are called. Further, when each of the word lines is selected, the even-numbered plate lines are called first and then the odd-numbered plate lines are called. Alternatively, when a specific one of the word lines is selected from among the plurality of word lines, the even-numbered plate lines are called first and then the odd-numbered plate lines are called.

[0111] Alternatively, when any one of the word lines is selected, only the even-numbered plate lines can be called. Further, when each of the word lines is selected, only the even-numbered plate lines are called. Alternatively, when a specific one of the word lines is selected from among the plurality of word lines, only the even-numbered plate lines are called.

[0112] Alternatively, when any one of the word lines is selected, only the odd-numbered plate lines can be called. Further, when each of the word lines is selected, only the odd-numbered plate lines are called. Alternatively, when a specific one of the word lines is selected from among the plurality of word lines, only the odd-numbered plate lines are called.

[0113] Alternatively, when each of the word lines is selected, the odd-numbered plate lines are called first and then the even-numbered plate lines are called. Alternatively, when a specific one of the word lines is selected from among the plurality of word lines, the odd-numbered plate lines are called first and then the even-numbered plate lines are called.

[0114] The second embodiment: in the reading stage, when a certain word line is selected, a specific part of the plurality of plate lines (for example, a plurality of plate lines) is called, which can be 2, 3, 4 or more plate lines. Exemplarily, the part of the plate lines are adjacent, or the part of the plate lines can include part of the adjacent plate lines and part of the non-adjacent plate lines. Based on the process, the ferroelectric storage cells in the plurality of cell groups connected to the same word line can be read, and the operation process of reading a plurality of bits corresponding to the same word line is realized.

[0115] Exemplarily, referring to Figure 8 , taking the example of selecting the word line WL1 and calling the plate lines PL2, PL3 and PL4, and the ferroelectric capacitors in the ferroelectric storage cells A 12 , A 15 are written with “1”, and the ferroelectric capacitors in the ferroelectric storage cells A 11 , A 14 , A 17 , A 18 are written with “0”. In the reading stage, the word line WL1 is selected, the potential on the word line WL1 is high, and the transistors T in the ferroelectric storage cells A 11 ~A 18 are all turned on. The plate lines PL2, PL3 and PL4 are called, and the potentials on the plate lines PL2, PL3 and PL4 are all set to high level, the plate lines PL1 and PL5 are not called, and the plate lines PL1 and PL5 are floating. And the bit lines BL1, BL2, BL4, BL5 and BL7 are floating, and the bit lines BL3, BL6 and BL8 input a fixed potential as a shield line. Based on this, combined with the comparator, the “0” stored in the ferroelectric storage cell A 11 can be read through the bit line BL1, the “1” stored in the ferroelectric storage cell A 12 can be read through the bit line BL2, the “0” stored in the ferroelectric storage cell A 14 can be read through the bit line BL4, the “1” stored in the ferroelectric storage cell A 15 can be read through the bit line BL5, and the “0” stored in the ferroelectric storage cell A 17 can be read through the bit line BL7. The rest is the same, which can be extended by analogy, and will not be repeated here.

[0116] Embodiment three

[0117] In the reading stage, a specific word line can be selected from a plurality of word lines and a plate line can be called to read two ferroelectric storage cells in a cell group, and the operation process of reading at least 2 bits corresponding to the same word line is realized. Exemplarily, referring to Figure 8 , taking the example of selecting the word line WL1 and calling the plate line PL4, and the ferroelectric capacitors in the ferroelectric storage cells A12 15 11 14 17 18 11 18 12 14

[0118] Embodiment Four

[0119] In the read stage, a specific part of the plurality of word lines (for example, a plurality of word lines) can be selected, and a specific part of the plurality of plate lines (for example, a plurality of plate lines) can be called. The specific part of the plurality of word lines can be 2, 3, 4, or more word lines, and the specific part of the plurality of plate lines can be 2, 3, 4, or more plate lines. Based on the process, the ferroelectric storage units in the plurality of unit groups connected by the plurality of word lines can be read, and the operation process of reading a plurality of bits corresponding to the plurality of word lines can be realized. It is worth mentioning that a single bit line can only be called by one ferroelectric storage unit at a time, so different ferroelectric storage units connected to the same bit line cannot occupy the bit line at the same time in a single read operation.

[0120] ​​​​​​​​​​In addition to 1T1C, the ferroelectric memory of the embodiments of the present application can also be used as a 2T2C array of ferroelectric memory. As before, the 2T2C array accesses two 1T1C cells combined into one storage cell, and the information stored in the two cells is opposite. Since in the embodiments of the present application, at least 2 ferroelectric memory cells of 1T1C can be read at a time, each cell group can just form a 2T2C memory cell, and the bit lines around the formed 2T2C memory cell are set as un-called bit lines for use as shielding lines. Exemplarily, in the read stage, when a certain word line is selected, the odd-numbered plate lines or the even-numbered plate lines are called, and the bit lines connected to the transistors connected to the selected word line and the called plate lines are called, and the remaining bit lines input a fixed potential as shielding lines. One or more shielding lines can be provided between each called bit line to achieve 100% shielding effect. Moreover, based on this process, the ferroelectric memory cells in the odd-numbered or even-numbered cell groups connected to the same word line can be read to achieve the operation process of reading multiple bits corresponding to the same word line. For example, referring to Figure 8 , taking the selected word line WL1 and the called even-numbered plate lines as an example, and the ferroelectric capacitors in the ferroelectric memory cells A 12 , A 15 , A 18 are written with “1” respectively, and the ferroelectric capacitors in the ferroelectric memory cells A 11 , A 14 , A 17 are written with “0” respectively. In the read stage, the word line WL1 is selected, the potential on the word line WL1 is high, and the transistors T in the ferroelectric memory cells A 11 ~ A 18 are all turned on. The plate lines PL2, PL4 are called, and the potentials on the plate lines PL2, PL4 are all set to high level, the plate lines PL1, PL3, PL5 are not called, and the plate lines PL1, PL3, PL5 are all floating. Moreover, the bit lines BL1, BL5, BL7 are all called floating, and the bit lines BL2, BL3, BL4, BL6, BL8 input a fixed potential as shielding lines. Among them, the bit lines BL2, BL3, BL4 can be used as shielding lines between the bit line BL1 and the bit line BL5, the bit line BL6 can be used as a shielding line between the bit line BL5 and the bit line BL7, and the remaining bit lines and their shielding lines can be used in the same way, which will not be described here. Based on this, combined with the comparator, the “1” stored in the ferroelectric memory cell A 15 or the “0” stored in the ferroelectric memory cell A 17 can be read out through the bit line BL5 and the bit line BL7. The rest is the same, which can be used in the same way, and will not be described here in detail.

[0121] Therefore, the ferroelectric memory in the embodiment of the present application can also be used as a ferroelectric memory of a 2T2C array, and the minimum reading unit is 1 bit (i.e. 2T2C storage unit). Moreover, not only the bit lines of different 2T2C storage units can have the shield lines, but also the two bit lines in the same 2T2C storage unit are provided with the shield lines, so that the reduction effect of the coupling interference can reach close to 100%. Moreover, the ferroelectric memory in the embodiment of the present application can also be used as a ferroelectric memory of a 2T2C array, and the layout area of the 2T2C storage unit is 2*6F 2 Therefore, the mutual coupling problem in reading the bit line signal can be improved, and the accuracy of signal reading can be improved compared with the scheme of the 2T2C storage unit in the prior art without reducing the storage density.

[0122] It is worth mentioning that, in the ferroelectric memory in the embodiment of the present application, by introducing the function of reading a specific unit group, the use frequency and the service life of the ferroelectric memory can be increased, and the power consumption can be reduced.

[0123] Figure 12 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 13 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 12 An exemplary layout structure diagram corresponding to the circuit diagram is shown, Figure 14 An exemplary layout structure diagram corresponding to the circuit diagram is shown, Figure 13 An exemplary cross-sectional structure diagram in the AA' direction in the layout structure diagram is shown, and the ferroelectric memory in the embodiment is for the above Figure 8 The ferroelectric memory in the embodiment shown is deformed, and the same parts are not repeated here, and the different parts are that the connection mode of the plate line. The specific description is made in combination with the drawings and examples.

[0124] Referring to Figure 9 and Figure 12 Taking the plate line PL1-PL9 as an example, for the unit group Z1, the second electrode of the ferroelectric capacitor C in the ferroelectric storage unit A 12 (i.e. the first ferroelectric storage unit) is connected to the plate line PL5, and the second electrode of the ferroelectric capacitor C in the ferroelectric storage unit A 14 (i.e. the second ferroelectric storage unit) is connected to the plate line PL6. For the unit group Z2, the second electrode of the ferroelectric capacitor C in the ferroelectric storage unit A 15 (i.e. the first ferroelectric storage unit) is connected to the plate line PL7, and the second electrode of the ferroelectric capacitor C in the ferroelectric storage unit A 17The second electrode of the ferroelectric capacitor C in the second ferroelectric memory cell is connected to board line PL8. The rest can be deduced similarly, and will not be elaborated further here. With this configuration, for any given cell group, the ferroelectric capacitors in the first and second ferroelectric memory cells within the same cell group can be connected to different board lines, allowing the first and second ferroelectric memory cells in the same cell group to transmit signals using different board lines.

[0125] Furthermore, the ferroelectric capacitors in the first and second ferroelectric memory cells connected to the same word line are connected to different board lines, so that these ferroelectric memory cells do not share board lines, further improving the freedom of data reading. For example, refer to... Figure 12 to Figure 14 Ferroelectric storage unit A 11 ~A 18 For example, ferroelectric memory cell A 11 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL4. Ferroelectric memory cell A 12 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL5. Ferroelectric memory cell A 14 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL6. Ferroelectric memory cell A 15 The second electrode of the ferroelectric capacitor C in (i.e., the first ferroelectric memory cell) is connected to the board line PL7. Ferroelectric memory cell A 17 The second electrode of the ferroelectric capacitor C in (i.e., the second ferroelectric memory cell) is connected to the board line PL8. Ferroelectric memory cell A 18 The second electrode of the ferroelectric capacitor C in the first ferroelectric storage unit is connected to the board line PL9.

[0126] To reduce the number of board lines, when multiple word lines include adjacent first and second word lines, the multiple cell groups connected by the first word line can be considered as a first cell group, and the multiple cell groups connected by the second word line can be considered as a second cell group. Furthermore, the bit line connected to the first ferroelectric memory cell in the second cell group is located between the bit lines connected to the first and second ferroelectric memory cells in the first cell group. This allows the ferroelectric capacitors in the first ferroelectric memory cells in the first cell group and the first ferroelectric memory cells in the second cell group to be connected to the same board line, thereby reducing the number of board lines. For example, refer to... Figure 9 , Figure 12 and Figure 13 When word line WL1 is the first word line and word line WL2 is the second word line, cell group Z1 can be the first cell group connected by word line WL1, and cell group Z3 can be the second cell group connected by word line WL2. Then, the ferroelectric memory cell A in cell group Z1... 12(i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z3 23 The board line connected to the first ferroelectric memory cell is the same board line PL5. When word line WL2 is the first word line and word line WL3 is the second word line, Z3 can be the first unit group connected by word line WL2, and Z6 can be the second unit group connected by word line WL3. Then, the ferroelectric memory cell A in unit group Z3... 23 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z6 34 The board line connected to the first ferroelectric memory cell is the same board line PL5. When word line WL3 is the first word line and word line WL4 is the second word line, Z6 can be the first unit group connected by word line WL3, and Z8 can be the second unit group connected by word line WL4. Then, the ferroelectric memory cell A in unit group Z6... 34 (i.e., the first ferroelectric memory cell) and ferroelectric memory cell A in cell group Z8 45 The board line connected to the first ferroelectric memory unit (i.e., the first ferroelectric memory unit) is the same board line PL5. When word line WL4 is the first word line and word line WL5 is the second word line, Z8 can be used as the first unit group connected to word line WL4. 10 If it can be used as the second unit group connected by word line WL5, then the ferroelectric storage unit A in unit group Z8 45 (i.e., the first ferroelectric memory cell) and cell group Z 10 Ferroelectric memory cell A in 56 The board line connected to the first ferroelectric memory cell is the same board line PL5. The others are similar and can be deduced sequentially, so they will not be elaborated further here. Based on this, in the ferroelectric memory provided in this embodiment, there can be multiple board lines (e.g., PL1 to PL5) that are spaced apart from each other.

[0127] Furthermore, when connecting multiple ferroelectric capacitors, the staggered arrangement of transistor channels allows for ample space to be reserved for the board wiring, sloping towards the straight lines. For example, refer to... Figure 13 Based on the staggered arrangement of the channels, the ferroelectric capacitors in different ferroelectric memory cells can form a unique straight line extending in an inclined direction (this inclined direction intersects both the first direction F1 and the second direction F2) from the upper left to the lower right. In addition, based on the stepped arrangement of the ferroelectric capacitors, the obstruction of the contact hole where the first conductive part is located by the board line can also be avoided, and the short circuit between the board line and the bit line can be avoided.

[0128] The ferroelectric memory of the embodiment of the present application can be used as a 1T1C array or a 2T2C array ferroelectric memory. And, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be written in whole or in part, improving the degree of freedom of the write operation. For the process of the write stage in the embodiment, the process in the above-mentioned embodiments can be referred to, and details are not repeated here.

[0129] And, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be read in whole or in part, improving the degree of freedom of the read operation. For the process of the read stage in the embodiment, the process in the above-mentioned embodiments can be referred to, and details are not repeated here.

[0130] Figure 15 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 16 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 15 The layout structure diagram corresponding to the circuit diagram shown, the ferroelectric memory in the embodiment is for the above Figure 12 The ferroelectric memory in the embodiment shown is deformed, and the same parts are not repeated here, and the different parts are that the connection relationship of the plate lines. Specifically, the plurality of plate lines are divided into a plurality of plate line groups, wherein each plate line group includes two adjacent plate lines. And, the two plate lines in each plate line group are electrically connected to each other, and the plate lines in different plate line groups are insulated from each other. Exemplarily, the two plate lines in each plate line group can be electrically connected to each other by a connection line. For example, referring to Figure 15 And, Figure 16 The plate lines PL2 and PL3 are divided into a plate line group, and the plate lines PL2 and PL3 are electrically connected to each other by one or more connection lines XL. The plate lines PL4 and PL5 are divided into a plate line group, and the plate lines PL4 and PL5 are electrically connected to each other by one or more connection lines XL. The plate lines PL6 and PL7 are divided into a plate line group, and the plate lines PL6 and PL7 are electrically connected to each other by one or more connection lines XL. The plate lines PL8 and PL9 are divided into a plate line group, and the plate lines PL8 and PL9 are electrically connected to each other by one or more connection lines XL.

[0131] And, referring to Figure 16 Based on the stepped arrangement of the ferroelectric capacitors and the staggered arrangement of the transistor channels, sufficient connection line space can be reserved for connection line wiring. And, based on the stepped arrangement of the ferroelectric capacitors, the connection line can also avoid blocking the contact hole where the first conductive part is located, and the plate line and the bit line are short-circuited.

[0132] The ferroelectric memory of the embodiment of the present application can be used as a ferroelectric memory of a 1T1C array or a 2T2C array. And, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be written in whole or in part, improving the degree of freedom of the write operation. For the process of the write stage in the embodiment, the process in the above-mentioned embodiments can be referred to, and details are not repeated here.

[0133] And, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be read in whole or in part, improving the degree of freedom of the read operation. For the process of the read stage in the embodiment, the process in the above-mentioned embodiments can be referred to, and details are not repeated here.

[0134] Figure 17 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 18 An exemplary circuit diagram of another ferroelectric memory in the embodiment of the present application is shown, Figure 17 The layout structure diagram corresponding to the circuit diagram shown, the ferroelectric memory in the embodiment is for the above Figure 8 The ferroelectric memory in the embodiment shown is deformed, and the same parts are not repeated here, and the different parts are that the connection relationship of the plate lines. Specifically, the ferroelectric capacitors in the ferroelectric memory cells corresponding to the same word line can be connected to the same plate line, and the ferroelectric capacitors in the ferroelectric memory cells corresponding to different word lines are connected to different plate lines. For example, referring to Figure 17 And Figure 18 The second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 11 ~A 18 is connected to the plate line PL1, the second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 22 ~A 28 is connected to the plate line PL2, the second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 31 ~A 37 is connected to the plate line PL3, the second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 41 ~A 48 is connected to the plate line PL4, the second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 52 ~A 58 is connected to the plate line PL5, and the second electrode of the ferroelectric capacitor in the ferroelectric memory cell A 61 ~A 67 is connected to the plate line PL6, and the plate lines PL1~PL6 can be arranged at intervals along the second direction F2.

[0135] And, referring to Figure 17, the stepped arrangement of the ferroelectric capacitors, and the staggered arrangement of the transistor channels can reserve sufficient connection line space for the plate line routing, so that the plate line is a fold line extending along the first direction F1. Moreover, based on the stepped arrangement of the ferroelectric capacitors, the plate line can avoid blocking the contact hole where the first conductive part is located, and avoid shorting the plate line and the bit line.

[0136] The ferroelectric memory of the embodiments of the present application can be used as a 1T1C array or a 2T2C array ferroelectric memory. Moreover, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be written in full. For the process of the write stage in the embodiments, the process in the above embodiments can be referred to, and details are not repeated here.

[0137] Moreover, based on the stepped arrangement of the ferroelectric capacitors, when any word line is selected, the ferroelectric memory cells can be read in full. For the process of the read stage in the embodiments, the process in the above embodiments can be referred to, and details are not repeated here.

[0138] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A ferroelectric memory, characterized in that, include: Multiple word lines, multiple bit lines, and multiple ferroelectric memory cells, each of the multiple ferroelectric memory cells being connected to one word line and one bit line among the multiple word lines; The plurality of ferroelectric memory cells connected by any word line include alternating first ferroelectric memory cells and second ferroelectric memory cells. A first ferroelectric memory cell and a second ferroelectric memory cell connected by the same word line form a cell group. In any cell group, there is at least one bit line between the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. In two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group.

2. The ferroelectric memory as described in claim 1, characterized in that, In any of the unit groups, there is a bit line between the bit line connected to the first ferroelectric memory unit and the bit line connected to the second ferroelectric memory unit.

3. The ferroelectric memory as described in claim 2, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The first ferroelectric memory cells connected by the first word line correspond one-to-one with the second ferroelectric memory cells connected by the second word line. The corresponding first ferroelectric memory cells and second ferroelectric memory cells are connected to the same bit line.

4. The ferroelectric memory as described in any one of claims 1-3, characterized in that, Each of the ferroelectric memory cells includes a transistor and a ferroelectric capacitor, wherein the gate of the transistor is connected to the corresponding word line, the first terminal of the transistor is connected to the corresponding bit line, and the second terminal of the transistor is connected to the ferroelectric capacitor; The plurality of word lines extend along a first direction and are spaced apart along a second direction, the plurality of bit lines extend along the second direction and are spaced apart along the first direction, and the channel of the transistor in each ferroelectric memory cell extends along the second direction.

5. The ferroelectric memory as described in claim 4, characterized in that, The channels of transistors connected to the same bit line are arranged sequentially along the second direction; or, The ferroelectric capacitors connected to the transistors on the same bit line are arranged sequentially along the second direction.

6. The ferroelectric memory as described in claim 5, characterized in that, The channel of the transistor includes a first source-drain region and a second source-drain region, the first source-drain region being connected to a corresponding bit line, and the second source-drain region being connected to the first electrode of the ferroelectric capacitor. The multiple word lines include adjacent first word lines and second word lines. The first ferroelectric memory cell connected by the first word line corresponds to the second ferroelectric memory cell connected by the second word line. The first source-drain regions of the transistors in the corresponding first ferroelectric memory cells and second ferroelectric memory cells are in the same region.

7. The ferroelectric memory as described in any one of claims 4-6, characterized in that, The multiple word lines, the multiple bit lines, and the multiple ferroelectric memory cells are disposed on the substrate, and the orthographic projection of any of the ferroelectric capacitors on the substrate and the second source / drain region connected to any of the ferroelectric capacitors on the orthographic projection of the substrate have an overlapping region.

8. The ferroelectric memory as described in any one of claims 4-7, characterized in that, It also includes multiple plate lines, with the second electrode of the ferroelectric capacitor in each of the ferroelectric memory cells connected to one of the multiple plate lines.

9. The ferroelectric memory as described in claim 8, characterized in that, In any of the unit groups, the ferroelectric capacitors in the first ferroelectric storage unit and the second ferroelectric storage unit are connected to the same board line.

10. The ferroelectric memory as described in claim 9, characterized in that, Ferroelectric capacitors in different unit groups connected to the same word line are connected to different board lines.

11. The ferroelectric memory according to any one of claims 8-10, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The multiple unit groups connected by the first word lines include a first unit group. The multiple unit groups connected by the second word lines include a second unit group. The bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first unit group. The ferroelectric capacitors in the first unit group and the second unit group are connected to the same board line.

12. The ferroelectric memory as described in any one of claims 8-11, characterized in that, Each of the aforementioned plate lines is a stepped, zigzag line.

13. The ferroelectric memory as described in claim 8, characterized in that, In any of the unit groups, the ferroelectric capacitors in the first ferroelectric storage unit and the second ferroelectric storage unit are connected to different board lines.

14. The ferroelectric memory as described in claim 13, characterized in that, The ferroelectric capacitors in the first and second ferroelectric memory cells, which are connected to the same word line, are connected to different board lines.

15. The ferroelectric memory as described in claim 14, characterized in that, The multiple word lines include adjacent first word lines and second word lines. The multiple unit groups connected by the first word lines include a first unit group. The multiple unit groups connected by the second word lines include a second unit group. The bit line connected to the first ferroelectric memory cell in the second unit group is located between the bit lines connected to the first ferroelectric memory cell and the second ferroelectric memory cell in the first unit group. The ferroelectric capacitor in the first ferroelectric memory cell in the first unit group and the first ferroelectric memory cell in the second unit group are connected to the same board line.

16. The ferroelectric memory as described in claim 15, characterized in that, Each of the plate lines is a straight line extending in a direction that intersects both the first and second directions.

17. The ferroelectric memory as described in claim 15 or 16, characterized in that, The plurality of board wires includes a plurality of board wire groups, each board wire group includes two adjacent board wires, and the two board wires in each board wire group are electrically connected to each other.

18. The ferroelectric memory as described in claim 8, characterized in that, Ferroelectric capacitors in ferroelectric memory cells corresponding to the same word line are connected to the same board line, while ferroelectric capacitors in ferroelectric memory cells corresponding to different word lines are connected to different board lines.

19. The ferroelectric memory as described in claim 18, characterized in that, Each of the aforementioned plate lines is a broken line extending along a first direction.

20. An electronic device, characterized in that, include: The circuit board and the ferroelectric memory as described in any one of claims 1-19, wherein the ferroelectric memory is disposed on the circuit board.

21. A method for reading a ferroelectric memory, characterized in that, The ferroelectric memory includes: multiple word lines, multiple bit lines, and multiple ferroelectric memory cells. Each of the multiple ferroelectric memory cells is connected to one word line and one bit line among the multiple word lines. Any word line connecting multiple ferroelectric memory cells includes alternating first and second ferroelectric memory cells. A first ferroelectric memory cell and a second ferroelectric memory cell connected to the same word line form a cell group. In any cell group, at least one bit line separates the bit line connected to the first ferroelectric memory cell and the bit line connected to the second ferroelectric memory cell. In two adjacent cell groups connected to the same word line, the bit line connected to the first ferroelectric memory cell in one cell group is adjacent to the bit line connected to the second ferroelectric memory cell in the other cell group. The method includes: Select any one of the multiple word lines, control at least a portion of the bit lines connected to the ferroelectric memory cells to be in a floating state, and control the unconnected bit lines of the ferroelectric memory cells to input a fixed potential.

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