Logical block address-to-physical block address mapping method for high-capacity solid-state disk

Abstract

The invention discloses a logical block address-to-physical block address mapping method for a high-capacity solid-state disk. The method comprises the steps of defining that a logical mapping unit is composed of a plurality of logic blocks; decomposing a write request of a host into a write request for the logical mapping unit; judging whether the logical mapping unit is in a cache or not, adding the logical mapping unit to the cache, and judging whether the cache is full or not; judging whether the logical mapping unit entering the cache at the earliest is written in the cache or not if the cache is full; mapping the logical mapping unit entering the cache at the earliest to a physical mapping unit capable of realizing parallel write, writing the logical mapping unit into a flash memory if the logical mapping unit is not written into the cache; reading the mapping unit from the flash memory if the mapping unit is written into the flash memory previously, combining the mapping unit with the data in the cache, mapping the combined logical mapping unit to the physical mapping unit capable of realizing parallel write, and writing the logical mapping unit into the flash memory. The size of a mapping table is controlled.

Description

[0001] technical field [0002] The invention relates to the field of data storage, in particular to a large-capacity solid-state hard disk logical address-to-physical address mapping method. Background technique [0003] Currently, NAND flash-based solid-state drives (SSDs) need to map the logical address (LBA) used by the host to the actual physical address of the flash. Usually, in order to improve the throughput of reading and writing, flash memory chips are placed on different channels (Channels), and there are usually several Targets in the flash memory chip, each Target has several LUNs, and each LUN has Several Planes, each Plane will have several blocks (Block), and each Block will have several pages (Page). Blocks and pages located on different channels, different chips, different targets, different LUNs and different planes can be read and written in parallel. So the physical address of flash memory includes channel number, chip number, Target address, LUN addre...

AI Technical Summary

Problems solved by technology

[0004] In the design of large-capacity solid-state drives, a prominent problem is that the mapping table may be too large

Larger mapping table means larger double-rate synchronous dynamic random access memory (DDR), larger memory addressing, larger space to place DDR, and greater power consumption, which makes the design more complex

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