A novel method to synchronize the switching frequency of hysteretic power converters is presented. The method includes the generation of a clock signal and the injection of a periodic disturbance signal operating at the frequency of the generated clock in the main loop of the converter to synchronize the hysteretic power converter to switch at the frequency of the clock.
The presented approach provides significant advantages with respect to the more traditional means of utilizing Frequency Lock Loop, Phase Lock Loop or Delay Lock Loop circuits, mainly for its simplicity, faster locking and much reduced phase error.
The switching frequency can be higher or lower than the free running frequency of the power converter provided that the free running frequency is close enough to the desired switching frequency.
The method is presented for buck and boost hysteretic high frequency switching power converters.