The application discloses a bottom-up
clock tree synthesis method and
system, which comprises inserting a logic unit to be inserted between a driver and a load connected to the driver; judging whether a
clock tree with the inserted logic unit meets a design rule constraint, if yes, the
insertion of the logic unit between the driver and the load connected to the driver is completed, if not, taking the inserted logic unit as a new load and starting from the
insertion of the logic unit to be inserted between the driver and the load connected to the driver. When the logic unit is inserted, the logic unit is inserted layer by layer from bottom to top, and leaf nodes which need to share
clock paths as much as possible due to
clock skew, common control critical path and other reasons can be divided under the same sub-tree as early as possible in the bottom layer, so that the
power consumption and the
chip area occupied are reduced, the problem that the
common path of the leaf nodes of the critical path is too short is avoided, and the
clock tree synthesis situation of a buffer, an
inverter or a mixture of both can be applied.