The invention discloses a bottom-to-top
clock tree synthesis method and
system. The method comprises the following steps: inserting a logic unit to be inserted between a driver and a load connected with the driver; and judging whether the
clock tree in which the logic unit is inserted meets design rule constraints or not, if so, completing
insertion of the logic unit between the driver and the load connected with the driver, and if not, taking the inserted logic unit as a new load, and starting execution from
insertion of the logic unit to be inserted between the driver and the load connected with the driver. When the logic units are inserted, the logic units are inserted layer by layer from bottom to top, leaf nodes which need to share
clock paths as far as possible due to
clock skew, common control of key paths and other reasons can be divided into the same sub-trees as soon as possible at the bottom layer,
power consumption and occupied
chip area are reduced, and the cost is reduced. The problem that a
common path of leaf nodes of a critical path is too short is avoided, and the method can be suitable for the situation of
clock tree synthesis of a buffer, a phase
inverter or a mixture of the buffer and the phase
inverter.