10 results about "Circuit partition" patented technology

This invention provides an automatic method and system for generating analog circuits. The circuit partitioning step divides the radio frequency (RF) circuit into multiple circuit units. The circuit segmentation step converts each circuit unit into multiple circuit segments. Each circuit segment includes at least one main component data and at least one peripheral component data. The main component model establishment step establishes a main component model, which corresponds to the main component data of each circuit segment. The circuit segment model establishment step establishes a circuit segment model, which corresponds to each circuit segment. The model combination step combines the main component model corresponding to each circuit segment with the circuit segment model to generate the analog circuit. This automatically converts the RF circuit into an analog circuit suitable for analog software.

Systems, structures, packages, circuits, and methods provide high-side gate driver circuits configured to control operation of high-side power (switching) transistors without use of external bootstrap capacitors. A high-side driver can include three sections, including a pull-up section, first pull-down section, and a second pull-down or Miller clamp section. The gate drivers can include a charge pump circuit and can avoid use of bootstrap capacitors and related circuitry. Partitioned gate drivers can include an individual pull-up section, an individual first pull-down section, and an individual second pull-down section for each of multiple high-side power transistors.

The invention provides an integrated circuit partitioning method and device, a terminal and a computer readable storage medium, and belongs to the technical field of integrated circuit emulation.The method comprises the steps that a plurality of unit modules in a to-be-partitioned module of an integrated circuit are obtained, and the to-be-partitioned module of the integrated circuit is partitioned according to the number of graphs in the unit modules, a graph number threshold value and first position information; target partition module information of the to-be-partitioned module is determined, so that the difference of the number of graphs of any target partition module determined based on the target partition module information is reduced or even the number of graphs is equal, and the distribution uniformity of the number of graphs of each target partition module is improved; in the process of calculating the integrated circuit by using the EDA back-end verification design tool according to the target partition module information, the phenomenon of overlarge peak memory can be effectively reduced, and the problem that the overall performance of the EDA back-end verification design tool is influenced by the overlarge peak memory is solved.

The invention relates to a manufacturing method of an integrated circuit partition control power supply embedded copper block circuit board, which comprises the following steps of: forming an integrated copper block constructed by bottom copper and a special-shaped copper block through one-time depth control milling in the previous procedure, and manufacturing a windowing core plate and carrying out primary embedding forming on the windowing core plate and the integrated copper block; the problems of deformation and liquid medicine permeation caused by thickness difference are avoided through the thickness balance effect of a first single-face windowing copper-clad plate and a second single-face windowing copper-clad plate and the isolation protection function of a first windowing release film and a second windowing release film in the second multi-layer structure stacking and laminating processing in the middle procedure; and finally, an auxiliary structure is precisely removed through laser depth-controlled milling, the position precision of the irregular special-shaped copper block is guaranteed in the whole process, the problems of deflection, deviation and the like are thoroughly avoided, the functions of the special-shaped copper block in various and multiple integrated circuit partition packaging control application, efficient heat dissipation, large current bearing, high-voltage adaptation and the like can be fully played, and the production efficiency is improved. And high-precision processing and application of the partition control high-heat-dissipation circuit board are realized.

The invention discloses an intelligent composite material heating system for realizing low-temperature uniform curing, which comprises a uniform planar composite material heating actuator and an industrial edge computing controller, and is characterized in that the heating actuator is a flexible whole formed by compounding multiple layers of functional materials through hot pressing and is divided into a plurality of independent circuit partitions; and a film temperature control sensor is embedded in each subarea. The controller runs a self-adaptive control algorithm, and the flow of the algorithm comprises the following steps: system self-learning and model identification; subarea adaptive control and global thermal field collaborative equalization are carried out; and environment disturbance feedforward compensation. According to the heating system, through combination of a planar uniform heat source and partition intelligent balance control, high-uniformity temperature control within + / -1.0 DEG C on a large heating area during low-temperature curing below 85 DEG C is achieved, the steady-state precision is within + / -0.3 DEG C, the anti-interference capacity is high, energy consumption is remarkably reduced, and high-quality low-temperature curing manufacturing of composite materials is powerfully supported.

Systems, structures, packages, circuits, and methods provide high-side gate driver circuits configured to control operation of high-side power (switching) transistors without use of external bootstrap capacitors. A high-side driver can include three sections, including a pull-up section, first pull-down section, and a second pull-down or Miller clamp section. The gate drivers can include a charge pump circuit and can avoid use of bootstrap capacitors and related circuitry. Partitioned gate drivers can include an individual pull-up section, an individual first pull-down section, and an individual second pull-down section for each of multiple high-side power transistors.

A real-time simulation method and system for an energy release device, which method and system relate to the technical field of power simulation. The method comprises: acquiring a charging pile circuit and an energy release multi-unit circuit of an energy release device, and performing circuit partitioning on the energy release multi-unit circuit, so as to obtain a plurality of parallel sub-circuits; loading the parallel sub-circuits and the charging pile circuit onto a preset parallel simulation platform, so as to obtain an initial simulation model; performing performance optimization on the initial simulation model, so as to obtain a target simulation model; and performing simulation processing on the energy release device by means of the target simulation model, so as to obtain a simulation result corresponding to the energy release device. The technical problem of the operational reliability of an energy release device being reduced is solved, wherein the reduction is caused by the difficulty in meeting performance requirements for microsecond-level electromagnetic transient real-time simulation of a large-scale energy release device because existing electromagnetic transient simulation methods for an energy release device are not adapted to large-scale system simulation in terms of computation, memory, communication, etc.

A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.

Embodiments herein relate to a circuit for evaluating the ground voltage of each circuit partition of a number of circuit partitions, one partition at a time. Once the ground voltage is determined, a corresponding code is stored to control a leakage circuit coupled to the ground node. The leakage circuit provides a leakage current based on the code to offset the ground voltage to a target voltage, which may be common for each of the partitions. The circuit can include a voltage source which supplies a stair step increasing voltage to a comparator. The comparator compares the voltage of the voltage source to the ground node voltage and provides an output which changes when the two input voltages are approximately equal, within a tolerance. The circuit may include a finite state machine for managing the process.

The invention provides a partition transmission, a gate driving circuit, a driver, a control method and a display device, the gate driving circuit comprises a shift register and a partition transmission circuit, the partition transmission circuit can transmit a driving signal of the shift register to a partition signal output end so as to maintain an original refresh rate, and the drive signal is transmitted to the display device. In addition, transmission of the driving signal to the partition signal output end can be blocked according to needs, meanwhile, the second level signal is input into the partition signal output end, at the moment, the AA area cannot obtain the enable signal, the next frame is not refreshed any more, and the low refresh rate is maintained. Therefore, by using the partition transfer circuit and the gate drive circuit comprising the partition transfer circuit in the embodiment, partition refreshing of the display device can be realized, and low power consumption and a display effect are both considered.