41 results about "Circuit partition" patented technology

Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a microprocessor includes: look-up memory and a first circuit coupled to the look-up memory. In response to the microprocessor receiving a first instruction, the first circuit partitions the look-up memory into a first plurality of look-up tables. In response to the microprocessor receiving a second instruction, the first circuit partitions the look-up memory into a second plurality of look-up tables; and the second plurality of look-up tables simultaneously look up a plurality of entries.

A switched mode power converter having a feedback mechanism by which a coded train of pulses with well defined integrity is generated on a secondary side of the power converter and transmitted to a dedicated control signal winding on the primary side for decoding and application to regulate the power converter output. The control signal winding enables separation of control signal transmission and power transmission resulting in improved processing of the control signal by a primary side controller. The pulse train is modulated by a secondary side controller, transmitted across a transformer and received by the control signal winding, and supplied to the primary side controller. Coded information is included in the coded pulse train by modulating pulses of the pulse train.

The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

The invention discloses a pixel circuit, a driving method thereof and a display device. The pixel circuit comprises a first switch sub-circuit, a partition driving chip and a plurality of light-emitting elements. The first switch sub-circuit is respectively connected with a scanning line, a data line and a first node and is used for writing a data voltage signal of the data line into the first node under the control of the scanning line; and the partition driving chip is connected with the first node and the plurality of light-emitting elements respectively and is used for judging driving timecorresponding to each light-emitting element according to a data voltage signal input by the first node, and driving the light-emitting elements to emit light by using the data voltage signal withinthe corresponding driving time. Active site selection driving is realized through the first switch sub-circuit and the partition driving chip, so that the number of glass-based wires is effectively reduced, the difficulty of a side edge wire routing process is greatly reduced, the driving power consumption and the driving cost of the whole display module are reduced, and the competitive advantageof a product is greatly improved.

The invention discloses a method and a system for cooperatively evaluating the reliability of a power transmission and transformation system and a power distribution system based on partition simplification. The method comprises the following steps: partitioning a power distribution system into partitioning power supply areas according to a switch device, and partitioning the power supply area by using the switch as a boundary; partitioning into circuit partitions according to a component group of the power transmission and transformation system, and partitioning the power transmission and transformation system; traversing component failures of the power transmission and transformation system; traversing failures of internal components of a transformer substation; traversing component failures of a middle-voltage power transmission system; and acquiring the reliability index of the power transmission and transformation system and the power distribution system according to the component failures of the power transmission and transformation system, the failures of the internal components of the transformer substation and the component failures of the middle-voltage power transmission system. Through the scheme, the whole power supply reliability level of the power transmission and transformation system is balanced, so that scientific and reasonable construction of the power transmission and transformation system and the power distribution system is guided, and the development of reliable operation and maintenance of the power transmission and transformation system and the power distribution system is guided.

Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined partitioning method, where each circuit partition includes one or more circuit components. The method further includes, for each circuit partition, identifying substantial correlations between the circuit partition and one or more other circuit partitions to form a spanning tree, where the spanning tree connects the circuit partition to the one or more other circuit partitions via a graph, and merging the circuit partition and the one or more other circuit partitions in the spanning tree to form a new circuit partition.

Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

A subscriber line interface circuit has a battery-powered, high voltage analog section, that drives tip and ring lines of a subscriber loop, and a mixed signal (low voltage and digital signal processing) section, that monitors and controls the high voltage analog section. An input signal receiving unit of the high voltage analog section conditions input voice and low voltage signaling and ringing signals from the mixed signal section, for application to a dual mode, programmable gain, tip/ring amplifier coupled to the loop. A sense amplifier at the output of the tip/ring amplifier is through an auxiliary amplifier to an analog feedback monitor port for closing a loop to synthesize the circuit's output impedance.

The invention discloses a high-performance self-test external reference time-base circuit and an implementation method thereof. The high-performance self-test external reference time-base circuit comprises an external reference filtering and amplifying circuit, an external reference self-test circuit, an external reference phase discrimination filtering circuit, an one-out-of-two switch and a constant-temperature crystal oscillator, wherein an output end of the external reference self-test circuit is connected with a selection control end of the one-out-of-two switch; an output end of the external reference phase discrimination filtering circuit is connected with one input end of the one-out-of-two switch; when an external reference signal is input, the external reference filtering and amplifying circuit partitions the external reference signal into two paths after filtering and amplifying the external reference signal; one path of the external reference signal is connected with the external reference phase discrimination filtering circuit; the other path of the external reference signal is connected with the external reference self-test circuit; and the one-out-of-two switch is controlled to be switched to an output end of the external reference phase discrimination filtering circuit in order to perform loop phase locking on the external reference signal. The high-performance self-test external reference time-base circuit has the beneficial effects that a complete machine can decide whether to use the external reference signal not under the control of an FPGA (Field Programmable Gate Array) even when the external reference signal is input.

The application provides a power supply circuit of an ADC (Analog to Digital Converter) and a spectrum analyzer. The power supply circuit of the ADC (Analog to Digital Converter) is suitable for a digital-analog hybrid circuit board and at least comprises a first direct current converter, a second direct current converter, a first linear voltage stabilizer, a second linear voltage stabilizer and athird linear voltage stabilizer; the first direct current converter, the second direct current converter and the first linear voltage stabilizer are arranged in a power source partition; the second linear voltage stabilizer is arranged in an analog circuit partition; the third linear voltage stabilizer is disposed in a digital circuit partition; a voltage supplied by a power source is subjected to two-stage voltage reduction of the first direct current converter and the third direct current converter so as to be decreased to a power supply voltage of the digital power source end of the ADC; and the voltage supplied by the power source is subjected to three-stage voltage reduction of the second direct current converter, the first linear voltage stabilizer and the second direct current converter so as to be decreased to a power supply voltage of the analog power source end of the ADC. With the power supply circuit of the ADC (Analog to Digital Converter) and the spectrum analyzer of theinvention adopted, low-frequency noises from the power source or coupled along a line can be reduced.

The present invention provides a signal processing system distributed across a first chip and a second chip, and associated method. The signal processing system includes a first inter-ship connection circuit, a second inter-ship connection circuit, and a quantity of converters. Each converter includes multiple serially coupled units forming multiple frequency interfaces, and each of the units is capable of converting frequencies between two consecutive frequency interfaces. The first inter-ship connection circuit and the second inter-ship connection circuit partition each converter to a first portion and a second portion at a corresponding one of the frequency interfaces of each converter. The first portion and the second portion of each converter are respectively formed in the first chip and the second chip, and the first inter-ship connection circuit and the second first inter-ship connection circuit are arranged to relay signal between the first portion and the second portion of each converter. The signal processing system and associated method has higher flexibility.

The invention discloses a method and a circuit structure for controlling abnormal instruction output. The circuit structure comprises a reset circuit, a partition time sequence power supply circuit, an instruction generation latch circuit and a redundant signal control instruction driving circuit. A redundant latch circuit is adopted as an instruction generation circuit, a plurality of latches respectively generate pulse control signals to form multi-pulse control signals, and instructions can be output only when the corresponding multi-pulse control signals are valid; an independent power supply unit supplies power to an instruction generation circuit and an instruction driving circuit separately, the power supply of the instruction driving circuit is controlled by a reset signal, the instruction driving circuit is powered on after the instruction generation circuit is powered on, and abnormal instruction output in the power-on process is forbidden; the voltage of the subarea power supply is monitored in real time, when the voltage is lower than a normal power supply range, a reset signal is generated to power off the instruction driving circuit, the instruction driving circuit ispowered off in the process that voltage abnormal fluctuation is lower than a normal value or power is off, and abnormal instruction output is avoided. The reliability of instruction output can be effectively improved.

A computer-aided method for parallel calculation of the operating point of electrical circuits has the circuit partitioned into a number of partitions in a first step, in which the charging method is used for the parallel calculation of the individual partitions.

The invention discloses a navigation data making method and system suitable for an intelligent rail express system, which can make and maintain the navigation data according to a proprietary format, visually display the information, such as stations and speed limits of the operation of an intelligent rail train, etc., and meet the requirements of ART trains for the navigation data. According to the technical scheme, the method comprises the steps of 1, creating a line set container; 2, setting circuit partitions; 3, making the interval data in the circuit partitions; and 4, performing data compiling on the interval data.

The invention provides an adjusting device and an adjusting method for circuit signal offset. The circuit signal offset adjusting method comprises the following steps: providing a controller to execute the following steps: based on each of a plurality of clock signals, segmenting the circuit according to a network link table of the circuit to generate a plurality of circuit partitions; respectively performing clustering action on the circuit partitions to obtain a plurality of circuit clusters; recognizing adjacent states of the layout positions of the circuit groups; and adjusting the offset value of each circuit group according to the adjacent state.