41 results about "Circuit partition" patented technology

A subscriber line interface circuit has a battery-powered, high voltage analog section, that drives tip and ring lines of a subscriber loop, and a mixed signal (low voltage and digital signal processing) section, that monitors and controls the high voltage analog section. An input signal receiving unit of the high voltage analog section conditions input voice and low voltage signaling and ringing signals from the mixed signal section, for application to a dual mode, programmable gain, tip / ring amplifier coupled to the loop. A sense amplifier at the output of the tip / ring amplifier is through an auxiliary amplifier to an analog feedback monitor port for closing a loop to synthesize the circuit's output impedance.

Some embodiments of the invention provide a three-dimensional (3D) circuit structure that uses latches to transfer signals between two bonded circuit layers. In some embodiments, this structure includes a first circuit partition on a first bonded layer and a second circuit partition on a second bonded layer. It also includes at least one latch to transfer signals between the first circuit partition on the first bonded layer and the second circuit partition on the second bonded layer. In some embodiments, the latch operates in (1) an open first mode that allows a signal to pass from the first circuit partition to the second circuit partition and (2) a closed second mode that maintains the signal passed through during the prior open first mode. By allowing the signal to pass through the first circuit partition to the second circuit partition during its open mode, the latch allows the signal to borrow time from a first portion of a clock cycle of the second circuit partition for a second portion of the clock cycle of the second circuit partition.

The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step 1) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step 2) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Step 1 by a predetermined coefficient α, and a step (Step 3) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

A pixel circuit, its driving method, and a display device. The pixel circuit includes a first switch subcircuit, a partition driver chip, and a plurality of light-emitting elements, wherein: the first switch subcircuit is connected to a scanning line, a data line, and a first node connection, used to write the data voltage signal of the data line into the first node under the control of the scan line; The corresponding driving time of each light-emitting element is determined according to the data voltage signal, and the light-emitting element is driven to emit light by using the data voltage signal within the corresponding driving time. This application realizes the active site selection drive through the first switch sub-circuit and the partition driver chip, which effectively reduces the number of glass-based wiring, greatly reduces the difficulty of the side wiring process, and reduces the driving power of the overall display module. Consumption and driving costs, greatly improving the competitive advantage of the product.

The invention provides a circuit partitioning method for parallel circuit simulation, and belongs to the technical field of very large scale integration (VLSI) circuit design automation. The method comprises the steps as follows: better initial partition is rapidly acquired with a recursive multistage two-way partition method taking minimum cut as a target; and then minimum communication traffic and load balancing are taken as targets, and the partition is continuously improved with an iteration improvement method. The technical scheme is as follows: 1), a k-route initial partition is acquired with the recursive two-way partition method; 2), the two-way partition is performed with a multistage partition method, wherein at a roughening stage, load balancing is combined, and at an elaboration stage, iterations are limited; and 3), in an iteration improvement process, a peak which can improve the load balancing is selected to be moved preferentially each time. According to the method, an obtained partition result meets the requirements of the load balancing and less communication traffic, and the method is applicable to a circuit partition stage of an VLSI parallel circuit simulation system.

The invention discloses a specific protein analyzer and a testing method thereof. The specific protein analyzer includes a casing and a frame, and the frame includes a front support plate spaced from the front operating panel of the casing and a rear support spaced from the back plate of the casing Two-dimensional arm fixing plate perpendicular to the bottom plate is installed between the front and rear support plates. The X-axis component of the automatic two-dimensional arm is installed on the two-dimensional arm fixing plate. One side of the two-dimensional arm fixing plate is provided with a The circuit partitions are set at intervals on the back of the shell, the control board is installed between the circuit partition, the two-dimensional arm fixing plate and the casing, and the liquid circuit partition perpendicular to the bottom plate is arranged between the circuit partition and the front support plate. A horizontal support plate parallel to the bottom plate is provided between the front support plate and the rear support plate. The horizontal support plate is located below the side of the two-dimensional arm fixing plate where the automatic two-dimensional arm is installed. The reagent storage module and the reaction module are fixed On the horizontal support plate, the reagent storage module includes at least two reagent storage positions, and the reaction module is an even number of more than two.