Circuit partitioning method for parallel circuit simulation

Abstract

The invention provides a circuit partitioning method for parallel circuit simulation, and belongs to the technical field of very large scale integration (VLSI) circuit design automation. The method comprises the steps as follows: better initial partition is rapidly acquired with a recursive multistage two-way partition method taking minimum cut as a target; and then minimum communication traffic and load balancing are taken as targets, and the partition is continuously improved with an iteration improvement method. The technical scheme is as follows: 1), a k-route initial partition is acquired with the recursive two-way partition method; 2), the two-way partition is performed with a multistage partition method, wherein at a roughening stage, load balancing is combined, and at an elaboration stage, iterations are limited; and 3), in an iteration improvement process, a peak which can improve the load balancing is selected to be moved preferentially each time. According to the method, an obtained partition result meets the requirements of the load balancing and less communication traffic, and the method is applicable to a circuit partition stage of an VLSI parallel circuit simulation system.

Description

Technical field [0001] The invention relates to a circuit division method for parallel circuit simulation, which belongs to the field of very large-scale integrated circuit (VLSI) design automation technology, especially VLSI circuit simulation technology. Background technique [0002] In the circuit design stage of VLSI, it is necessary to carry out real-time simulation of the designed circuit through the simulation system, so as to carry out functional verification and corresponding optimization design. The simulation calculation process is to obtain the simulation result by solving the differential / algebraic equations representing the circuit function. As the circuit scale becomes larger and larger, simulation takes a lot of time. Traditional simulation technology can no longer meet industrial requirements and has become a bottleneck in VLSI design. Therefore, carrying out circuit simulation in a parallel environment to accelerate the simulation speed has formed a developmen...

AI Technical Summary

Problems solved by technology

Although the minimum cut is directly related to the minimum number of ports, there are still differences between the two.

In addition, parallel circuit simulation has higher requirements for load balance, while using traditional circuit division methods, there may be large differences in the load of each processor, which affects the efficiency of parallel simulation

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