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Multithreading processor and multithreading processing method

A processor and thread technology, applied in machine execution devices, concurrent instruction execution, etc., can solve problems such as waste of hardware resources, limit processing performance, and inability to develop dual-core application systems, and achieve good load balance, cost reduction, and easy utilization. Effect

Inactive Publication Date: 2009-01-14
苏州简约纳电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such a system has certain overlapping functions. For example, the CPU core and DSP core each have their own memory, register file, general-purpose register (GPR), access unit, instruction fetch unit, instruction emission unit, and bus, etc. waste of hardware resources
Secondly, when running, one processor core is often idle while the other processor core is busy, which directly limits the processing performance.
Third, in a dual-core environment, users cannot develop dual-core application systems like developing single-processor programs, and need to complete the process of programming, debugging, compiling optimization, and on-line testing of CPU cores and DSP cores on different platforms

Method used

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  • Multithreading processor and multithreading processing method
  • Multithreading processor and multithreading processing method
  • Multithreading processor and multithreading processing method

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Embodiment Construction

[0014] The processor of the present invention employs an integrated model based on a single programmable engine for multithreading. It does not use two separate MCU and DSP cores for different application processing. In contrast, the present invention performs related processing in a multi-threaded mode within a single core.

[0015] To simplify the description, the following uses the dual-thread mode as an example to describe various implementations of the present invention.

[0016] figure 2 is a structural block diagram of a dual-thread processor core according to an embodiment of the present invention. The processor core is configured to simultaneously process two threads, Thread 0 and Thread 1, from different applications. The instructions of thread 0 and thread 1 are stored independently in different areas of the instruction cache (referred to as instruction cache). In other words, the instruction caches or their regions for different threads should be physically or...

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Abstract

The invention discloses a processor for parallel processing of a plurality of threads and a method for the processor to process a plurality of threads parallelly. The threads can come from different applications in the processor for parallel processing of a plurality of threads. The processor comprises a structural memory, which provides independent instructions and data storage for a plurality of threads; an instruction issuance unit, which reads the instructions of a plurality of threads and issues the instructions to an execution engine; the execution engine, which, shared by a plurality of threads, executes the instructions from the instruction issuance unit. The processor and the method of the invention avoid the necessity of execution pipeline reproduction in dual core proposals, allow better utilization of hardware resources and achieve better load equilibrium among a plurality of processed threads, thereby greatly lowering the chip cost.

Description

technical field [0001] The present invention relates to a processor, in particular to multi-thread parallel processing in the processor. Background technique [0002] Processors, especially embedded processors, are more and more widely used in fields such as mobile communications, digital consumer electronics, and intelligent control equipment, and their functions have changed from single to multiple. It is often necessary to run applications with different processing capabilities and characteristics in the same processor. For portable digital information products, there are not only a large number of real-time digital audio and video processing, but also running system software to process communication protocols / signaling and user interaction information. figure 1 A prior art dual processor core architecture is illustrated. The architecture includes a microprocessor core (MCU) and a digital signal processor (DSP) core. The microprocessor core runs a real-time operating s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
Inventor 梅思行
Owner 苏州简约纳电子有限公司
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