The invention provides an array substrate wiring structure. The wiring structure comprises a plurality of wiring units, each wiring unit comprises a first data line, a second data line, a third data line, a fourth data line, a fifth data line, a sixth data line, a seventh data line, an eighth data line, a first gate line, a second gate line, a third gate line, a fourth gate line, a fifth gate line and a
thin film transistor matrix; the first data line, the fourth data line, the sixth data line and the seventh data line are taken as first
data lines, the second data line, the third data line, the fifth data line and the eighth data line are taken as second
data lines, the polarity of the first
data lines is opposite to that of the second data lines, the first data lines are connected with source electrodes of thin film transistors in odd-numbered rows and odd-numbered columns and thin film transistors in even-numbered rows and even-numbered columns in a corresponding array, and the second data lines are connected with source electrodes of thin film transistors in odd-numbered rows and even-numbered columns and thin film transistors in even-numbered rows and odd-numbered columns in a corresponding array; the second gate line and the fourth gate line are connected with gate electrodes of two thin film transistors which are located in two adjacent rows of the first data line side, and the first gate line, the third gate line and the fifth gate line are connected with gate electrodes of two thin film transistors which are located in two adjacent rows of the second data line side, so that the polarity of each pixel in the
pixel matrix corresponding to the
thin film transistor matrix is opposite to that of any adjacent pixels.