140 results about "Three-dimensional integrated circuit" patented technology

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

The invention belongs to the field of integrated circuit testing, and particularly relates to a glass through hole defect detection method based on WOA-Light GBM. Aiming at the problems that the existing detection means is low in efficiency and high in cost and the precision depends on human experience, three-dimensional models of a TGV structure under different defect conditions are established through electromagnetic simulation software, the three-dimensional models comprise defect models of uneven through hole contours and multi-stage side wall roughness characteristics, and corresponding S parameters are extracted as judgment bases; and constructing a feature data set. On this basis, a LightGBM classification model is constructed, a whale optimization algorithm is adopted to carry out global search and optimization on key hyper-parameters, an optimal parameter combination is obtained, and automatic classification and identification of the defect TGV are realized. Therefore, according to the glass through hole defect detection method based on the WOA-LightGBM, high-precision detection of various types of defects can be achieved in a lossless mode, the algorithm training efficiency is high, the method is suitable for the large-scale production detection process, and flexibility is provided for manufacturing of high-standard and high-reliability glass through holes.

Integrated circuits (ICs) having a separate signal and power distribution network (PDN) interconnect structures for reduced power signal routing congestion and path lengths, and related three-dimensional (3D) ICs (3DICs) and fabrication methods. The IC includes a separate signal interconnect structure providing input / output (I / O) signal routing, and a PDN interconnect structure for providing power distribution signal routing. The signal interconnect structure is disposed on a first side of a semiconductor layer in the IC, and the PDN interconnect structure is disposed on a second side of the semiconductor layer opposite of the first side. In this manner, performance of semiconductor devices in the semiconductor layer can be improved, because power distribution signals do not have to be routed in a shared interconnect structure that is also used for routing I / O signals, which could otherwise congest and increase power distribution signal routing path lengths in the IC.

An avalanche diode arrangement includes a three-dimensional integrated circuit including a stack with at least a top-tier and a bottom-tier. The avalanche diode arrangement also includes a breakdown voltage monitor circuit. The top-tier includes an array of avalanche diodes. The bottom-tier includes an array of integrated light sources, located below the top-tier. In a calibration mode of operation, the light sources are operable to emit light towards the avalanche diodes. The breakdown voltage monitor circuit is operable to adjust bias voltages of the avalanche diodes depending on trigger events induced by light emitted by the light sources during the calibration mode of operation.

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

In an embodiment, a method for fast prediction of hotspot temperatures in three-dimensional (3D) integrated circuit (IC) chips, can involve inputting a dataset comprising thermal simulation data and associated parameters for 3D IC chips, wherein the dataset includes variables such as power distribution, processor core location distribution, and Through Silicon Via (TSV) distribution, applying a K-fold CrossValidation (K-CV) algorithm to train a machine learning model using the inputted dataset, wherein the K-CV algorithm is employed to optimize the training process and prevent overfitting, utilizing a Support Vector Regression (SVR) algorithm within the trained machine learning model to predict hotspot temperatures of the 3D IC chips, and adjusting a cooling strategy for cooling the 3D IC chips, in response to monitoring the hotspot temperatures via the trained machine learning model. The 3D IC chip can include a multi-layer structure including a group of vertically stacked semiconductor layers.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

A computing power chip and a physical design method thereof, and a three-dimensional integrated circuit chip, the method comprising: determining a structure and a design level of the computing power chip, the computing power chip comprising a plurality of computing groups arranged along a first direction, each computing group comprising a plurality of computing units arranged along a second direction, the design level comprises a calculation unit layer, a calculation group layer and a top layer from bottom to top, and the first direction and the second direction intersect; in the calculation unit layer, first layout wiring design is carried out on the calculation units, and the calculation units with time sequence convergence are obtained; in the calculation group layer, calling a plurality of calculation units, flattening the calculation units, deleting wires in the calculation units, and carrying out second layout wiring design on the calculation groups to obtain the calculation groups with time sequence convergence; and at the top layer, calling the calculation group, and carrying out third layout wiring design on the top layer to obtain a designed computing power chip.

The present disclosure relates to three-dimensional integrated circuits and fabrication thereof. An IC structure includes a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

The invention discloses a finite element-based calculation method for heat distribution of a large-scale three-dimensional integrated circuit (3DIC). The method comprises the following steps of: establishing a large-scale 3DIC model; performing heat distribution calculation on the established large-scale 3DIC model; for an existing heat dissipation method, 3DIC is systematically looked up, and important parameters in the aspects of geometry, heat dissipation, heat sources and the like are collected; parameterizing geometry, heat dissipation, a heat source and the like; establishing a large-scale 3DIC model database; performing heat distribution calculation on the database model; collecting a database model heat distribution calculation result, and inputting the result into a database; and establishing an artificial intelligence / machine learning optimization system. According to the method, the finite element analysis FEA technology with an accurate solving function is combined with an efficient XSim calculation tool, high accuracy and calculation efficiency are achieved, the super-strong performance of comprehensively simulating thermal behaviors of the whole packaging large model and the surrounding thermal environment of the whole packaging large model is achieved, and the heat distribution calculation problem of large three-dimensional integrated circuit 3DIC packaging is solved.

A method of characterizing a device under test (DUT) includes illuminating the DUT with a broadband optical beam within an optical field of view (FOV), illuminating the DUT with an X-ray beam within an X-ray FOV overlapping the optical FOV, and concurrently acquiring X-ray metrology information, e.g., one or more X-ray images utilizing various modalities, such as absorption, phase contrast difference, darkfield, small angle X-ray scattering (SAXS) and / or fluorescence, from the X-ray FOV and a plurality of optical images of the optical FOV, each of the optical images corresponding to respective selected wavelengths of the broadband optical beam from each of ultraviolet, visible, and infrared wavelengths, for example including deep ultraviolet, near infrared, or short-wavelength infrared wavelengths. The DUT may be one or more substrates, e.g., stacked, and include electronic devices such as three-dimensional integrated devices.

This application discloses a method for fabricating conductive lines on a multilayer co-fired ceramic substrate and the multilayer co-fired ceramic substrate itself, relating to the field of electronic ceramic multilayer co-fired manufacturing technology. The method for fabricating conductive lines on the multilayer co-fired ceramic substrate includes: providing a green ceramic film strip for multilayer stacking and co-firing; forming conductive patterns on the surface of the green ceramic film strip using nanoimprinting technology, aligning and stacking it with at least one other green ceramic film strip, and laminating it to form a stack; and performing adhesive removal and co-firing treatment on the stack to form embedded conductive lines within the stack. The fabrication method proposed in this application can fabricate conductive lines with linewidths and spacings less than 50 μm, achieving embedded forming of conductive lines in multilayer structures. It can be used in conjunction with via drilling / filling and stack alignment processes for precision packaging of three-dimensional integrated circuits such as high-density multilayer wiring, high-frequency and high-speed circuits, and power electronic integration.

Three-dimensional (3D) integrated circuit (IC) structures that are less constrained by the 2D footprint of a conventional IC chip. The novel 3D IC structures combine 3D ICs fabricated using various die and / or wafer bonding technologies with embedded die packaging technology. Embodiments include a 3D IC structure including one or more 3D IC chips embedded in a stack of one or more planar lamination layers. The combination of one or more 3D ICs with an embedded die packaging technology results in a high degree of integration and miniaturization by utilizing the placement of electrical connection pads on both the top and bottom surfaces of the 3D ICs.This enables better integration of active components as well as passive components, enables flexible partitioning of circuits and systems for 3D integration, and enables low-profile 3D IC structures that utilize scaling effects.

Systems and methods are presented for packet-based simulation of hybrid bumps for a circuit design of a three-dimensional integrated circuit (3DIC). A method may include identifying hybrid bumps of an input circuit design, each hybrid bump may represent connecting elements between circuits of a three-dimensional integrated circuit (3DIC) structure. The method may also include grouping the hybrid bumps into bump groups based on a pitch value specifying a distance between the hybrid bumps from each other, wherein each bump group includes a plurality of hybrid bumps. For a given one of the salient point groups, the method may include performing a point-to-point simulation from a representative point determined for the given salient point group, and using a result of the point-to-point simulation from the representative point as a simulation result of each of the plurality of mixed salient points included in the given salient point group.

An apparatus of a ferromagnetic transformer in a 3D integrated circuit is described, which comprises a plurality of semiconductor chips stacked within the 3D integrated circuit. An individual semiconductor chip of the plurality of semiconductor chips comprises a substrate, a plurality of dielectric layers, and a plurality of metal layers in the plurality of dielectric layers. In at least one example, the apparatus comprises one or more ferromagnetic through silicon vias vertically positioned through the individual semiconductor chip.

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

A three dimensional (3D) Integrated Circuit (IC) package is provided. The 3D IC package includes a first IC die having a first substrate at a back side of the first IC die and a second IC die stacked at the back side of the first IC die and facing the first substrate. The 3D IC further includes a Through Silicon Via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV. A protection module is fabricated in the first substrate. The protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Mechanisms to improve the thermal conductivity of three-dimensional integrated circuit (3DIC) structures by thinning the metal and dielectric layers in comparison to the dimensions of these layers in conventional 3DIC structures, resulting in a commensurate thinning of the oxide layers between active layers and metal layers, and a reduction in the number of metal and oxide layers utilized compared to conventional 3DIC structures.

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression.

This invention discloses a type 0-3 polymer ferroelectric composite material for use in integrated circuit interposers and its preparation method. The composite material consists of an epoxy resin matrix and KBiFe2O5 ferroelectric powder dispersed therein, with 100 parts by mass of epoxy resin and 5-50 parts by mass of KBiFe2O5. KBiFe2O5 has a layered perovskite structure and a low intrinsic dielectric constant (<3.5), and a coefficient of thermal expansion of only 1.6-10 ppm / K. Surface modification of the ferroelectric powder with a silane coupling agent can significantly improve its interfacial bonding strength with the epoxy resin. This invention utilizes a type 0-3 composite structure to achieve adjustable coefficient of thermal expansion of the composite material within the range of 3-20 ppm / K while maintaining a low dielectric constant (3.0-3.8@1 MHz) and low dielectric loss (<0.005@1 MHz), enabling good matching with silicon chips (CTE approximately 3-5 ppm / K) and effectively reducing thermal cycling stress. The composite material has a simple preparation process, is compatible with existing packaging production lines, and is suitable for use as an interposer material in three-dimensional integrated circuit packaging, showing promising application prospects.

The invention relates to a three-dimensional integrated circuit (3DIC) and a 3DIC design method and system. Three-dimensional integrated circuit (3DIC) design methods and systems include metal stack and bond pitch optimization to improve power, performance, and area (PPA). The resulting 3DIC includes a first chip and a second chip. The last metal level of the second chip may be bonded to the last metal level of the first chip by a bonding element. A bonding pitch of the bonding elements may be at least as large as a pitch of the first chip last metal level and the second chip last metal level. The metal stack configuration of each chip may be the same or different. In the case of different metal stack configurations, the total number of metal levels on each chip, the thickness of metal levels on each chip, and / or the pitch of the last metal levels on each chip may be different.

The present invention relates to a three-dimensional integrated circuit and a manufacturing method thereof. The three-dimensional integrated circuit includes: a memory wafer, a plurality of first power supply lines are provided on a metal layer of the memory wafer, and the plurality of first power supply lines are used to supply power to circuits on the memory wafer; a logic wafer, a plurality of second power supply lines are provided on a metal layer of the logic wafer, and the plurality of second power supply lines are used to supply power to circuits on the memory wafer; wherein each of the plurality of first power supply lines is connected in parallel with a corresponding second power supply line among the plurality of second power supply lines.

This invention discloses a method, prediction method, and apparatus for constructing a thermal stress field prediction model for a TSV array, relating to the field of three-dimensional integrated circuit technology. It addresses the problems of traditional TSV array thermal stress prediction methods relying on finite element simulation, which is computationally complex and time-consuming. The construction method includes: obtaining silicon via array parameter samples; performing thermal stress simulation on the silicon via array based on the silicon via array parameter samples to obtain thermal stress field simulation data; and training an initial model of the TSV array thermal stress field prediction model based on the silicon via array parameter samples and the thermal stress field simulation data to obtain a target TSV array thermal stress field prediction model. This invention provides a method for constructing a TSV array thermal stress field prediction model for high-precision and high-efficiency prediction of the thermal stress field of TSV arrays.

The invention provides an integrated circuit layout design method and device. The method comprises the following steps: formulating a new design rule according to each two-dimensional layout file in the three-dimensional integrated circuit, layer information of the three-dimensional layout file and a layout interconnection relationship between the three-dimensional layout file and each two-dimensional layout file; performing layer mapping and layout merging on each two-dimensional layout file and each three-dimensional layout file to obtain a new layout file; and checking and modifying the new layout file by adopting the new design rule until the new layout file passes the checking. The layout design and verification process can be simplified, and the design period is shortened.

The invention provides a low-temperature and low-voltage copper-copper metal bonding method, and belongs to the technical field of semiconductor packaging. The method comprises the following steps of: firstly, carrying out mechanochemical polishing on the copper column salient point formed by electroplating, reducing the surface roughness of the copper column salient point to a nanoscale to form a high-flatness bonding surface, and then applying a temperature of 290-300 DEG C and a pressure of 100-170 MPa in an air environment, and loading a constant current of 0.5-0.8 A to assist bonding for 30-90 seconds. The surface roughness is remarkably reduced through the CMP technology, the constant-current auxiliary induced electro-plastic effect is combined, rapid and reliable bonding of the copper pillar protruding points is successfully achieved under the low-temperature and low-pressure conditions, and the method is suitable for low-temperature and low-pressure rapid interconnection manufacturing of a three-dimensional integrated circuit (3D IC) and has good application prospects. And particularly, the bonding reliability problem of a heat-sensitive device in high-density packaging is solved.