101 results about "Three-dimensional integrated circuit" patented technology

The invention belongs to the field of integrated circuit testing, and particularly relates to a glass through hole defect detection method based on WOA-Light GBM. Aiming at the problems that the existing detection means is low in efficiency and high in cost and the precision depends on human experience, three-dimensional models of a TGV structure under different defect conditions are established through electromagnetic simulation software, the three-dimensional models comprise defect models of uneven through hole contours and multi-stage side wall roughness characteristics, and corresponding S parameters are extracted as judgment bases; and constructing a feature data set. On this basis, a LightGBM classification model is constructed, a whale optimization algorithm is adopted to carry out global search and optimization on key hyper-parameters, an optimal parameter combination is obtained, and automatic classification and identification of the defect TGV are realized. Therefore, according to the glass through hole defect detection method based on the WOA-LightGBM, high-precision detection of various types of defects can be achieved in a lossless mode, the algorithm training efficiency is high, the method is suitable for the large-scale production detection process, and flexibility is provided for manufacturing of high-standard and high-reliability glass through holes.

An avalanche diode arrangement includes a three-dimensional integrated circuit including a stack with at least a top-tier and a bottom-tier. The avalanche diode arrangement also includes a breakdown voltage monitor circuit. The top-tier includes an array of avalanche diodes. The bottom-tier includes an array of integrated light sources, located below the top-tier. In a calibration mode of operation, the light sources are operable to emit light towards the avalanche diodes. The breakdown voltage monitor circuit is operable to adjust bias voltages of the avalanche diodes depending on trigger events induced by light emitted by the light sources during the calibration mode of operation.

A three-dimensional integrated circuit device can include a group of die, a device layer and a thermal interface material formed above the substrate. A heat spreader can be located above the die, the device layer and the thermal interface material. The heat spreader can include a heat pipe comprising a rectangular-shaped heat pipe or disk-shaped heat pipe. A heat sink can be located above the heat spreader. The heat sink can include the heat pipe comprising the rectangular-shaped heat pipe or the disk-shaped heat pipe.

A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.

In an embodiment, a method for fast prediction of hotspot temperatures in three-dimensional (3D) integrated circuit (IC) chips, can involve inputting a dataset comprising thermal simulation data and associated parameters for 3D IC chips, wherein the dataset includes variables such as power distribution, processor core location distribution, and Through Silicon Via (TSV) distribution, applying a K-fold CrossValidation (K-CV) algorithm to train a machine learning model using the inputted dataset, wherein the K-CV algorithm is employed to optimize the training process and prevent overfitting, utilizing a Support Vector Regression (SVR) algorithm within the trained machine learning model to predict hotspot temperatures of the 3D IC chips, and adjusting a cooling strategy for cooling the 3D IC chips, in response to monitoring the hotspot temperatures via the trained machine learning model. The 3D IC chip can include a multi-layer structure including a group of vertically stacked semiconductor layers.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

A computing power chip and a physical design method thereof, and a three-dimensional integrated circuit chip, the method comprising: determining a structure and a design level of the computing power chip, the computing power chip comprising a plurality of computing groups arranged along a first direction, each computing group comprising a plurality of computing units arranged along a second direction, the design level comprises a calculation unit layer, a calculation group layer and a top layer from bottom to top, and the first direction and the second direction intersect; in the calculation unit layer, first layout wiring design is carried out on the calculation units, and the calculation units with time sequence convergence are obtained; in the calculation group layer, calling a plurality of calculation units, flattening the calculation units, deleting wires in the calculation units, and carrying out second layout wiring design on the calculation groups to obtain the calculation groups with time sequence convergence; and at the top layer, calling the calculation group, and carrying out third layout wiring design on the top layer to obtain a designed computing power chip.

The present disclosure relates to three-dimensional integrated circuits and fabrication thereof. An IC structure includes a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

A method of characterizing a device under test (DUT) includes illuminating the DUT with a broadband optical beam within an optical field of view (FOV), illuminating the DUT with an X-ray beam within an X-ray FOV overlapping the optical FOV, and concurrently acquiring X-ray metrology information, e.g., one or more X-ray images utilizing various modalities, such as absorption, phase contrast difference, darkfield, small angle X-ray scattering (SAXS) and / or fluorescence, from the X-ray FOV and a plurality of optical images of the optical FOV, each of the optical images corresponding to respective selected wavelengths of the broadband optical beam from each of ultraviolet, visible, and infrared wavelengths, for example including deep ultraviolet, near infrared, or short-wavelength infrared wavelengths. The DUT may be one or more substrates, e.g., stacked, and include electronic devices such as three-dimensional integrated devices.

This application discloses a method for fabricating conductive lines on a multilayer co-fired ceramic substrate and the multilayer co-fired ceramic substrate itself, relating to the field of electronic ceramic multilayer co-fired manufacturing technology. The method for fabricating conductive lines on the multilayer co-fired ceramic substrate includes: providing a green ceramic film strip for multilayer stacking and co-firing; forming conductive patterns on the surface of the green ceramic film strip using nanoimprinting technology, aligning and stacking it with at least one other green ceramic film strip, and laminating it to form a stack; and performing adhesive removal and co-firing treatment on the stack to form embedded conductive lines within the stack. The fabrication method proposed in this application can fabricate conductive lines with linewidths and spacings less than 50 μm, achieving embedded forming of conductive lines in multilayer structures. It can be used in conjunction with via drilling / filling and stack alignment processes for precision packaging of three-dimensional integrated circuits such as high-density multilayer wiring, high-frequency and high-speed circuits, and power electronic integration.

Three-dimensional (3D) integrated circuit (IC) structures that are less constrained by the 2D footprint of a conventional IC chip. The novel 3D IC structures combine 3D ICs fabricated using various die and / or wafer bonding technologies with embedded die packaging technology. Embodiments include a 3D IC structure including one or more 3D IC chips embedded in a stack of one or more planar lamination layers. The combination of one or more 3D ICs with an embedded die packaging technology results in a high degree of integration and miniaturization by utilizing the placement of electrical connection pads on both the top and bottom surfaces of the 3D ICs.This enables better integration of active components as well as passive components, enables flexible partitioning of circuits and systems for 3D integration, and enables low-profile 3D IC structures that utilize scaling effects.

Systems and methods are presented for packet-based simulation of hybrid bumps for a circuit design of a three-dimensional integrated circuit (3DIC). A method may include identifying hybrid bumps of an input circuit design, each hybrid bump may represent connecting elements between circuits of a three-dimensional integrated circuit (3DIC) structure. The method may also include grouping the hybrid bumps into bump groups based on a pitch value specifying a distance between the hybrid bumps from each other, wherein each bump group includes a plurality of hybrid bumps. For a given one of the salient point groups, the method may include performing a point-to-point simulation from a representative point determined for the given salient point group, and using a result of the point-to-point simulation from the representative point as a simulation result of each of the plurality of mixed salient points included in the given salient point group.

An apparatus of a ferromagnetic transformer in a 3D integrated circuit is described, which comprises a plurality of semiconductor chips stacked within the 3D integrated circuit. An individual semiconductor chip of the plurality of semiconductor chips comprises a substrate, a plurality of dielectric layers, and a plurality of metal layers in the plurality of dielectric layers. In at least one example, the apparatus comprises one or more ferromagnetic through silicon vias vertically positioned through the individual semiconductor chip.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

Mechanisms to improve the thermal conductivity of three-dimensional integrated circuit (3DIC) structures by thinning the metal and dielectric layers in comparison to the dimensions of these layers in conventional 3DIC structures, resulting in a commensurate thinning of the oxide layers between active layers and metal layers, and a reduction in the number of metal and oxide layers utilized compared to conventional 3DIC structures.

This invention discloses a type 0-3 polymer ferroelectric composite material for use in integrated circuit interposers and its preparation method. The composite material consists of an epoxy resin matrix and KBiFe2O5 ferroelectric powder dispersed therein, with 100 parts by mass of epoxy resin and 5-50 parts by mass of KBiFe2O5. KBiFe2O5 has a layered perovskite structure and a low intrinsic dielectric constant (<3.5), and a coefficient of thermal expansion of only 1.6-10 ppm / K. Surface modification of the ferroelectric powder with a silane coupling agent can significantly improve its interfacial bonding strength with the epoxy resin. This invention utilizes a type 0-3 composite structure to achieve adjustable coefficient of thermal expansion of the composite material within the range of 3-20 ppm / K while maintaining a low dielectric constant (3.0-3.8@1 MHz) and low dielectric loss (<0.005@1 MHz), enabling good matching with silicon chips (CTE approximately 3-5 ppm / K) and effectively reducing thermal cycling stress. The composite material has a simple preparation process, is compatible with existing packaging production lines, and is suitable for use as an interposer material in three-dimensional integrated circuit packaging, showing promising application prospects.

This invention discloses a method, prediction method, and apparatus for constructing a thermal stress field prediction model for a TSV array, relating to the field of three-dimensional integrated circuit technology. It addresses the problems of traditional TSV array thermal stress prediction methods relying on finite element simulation, which is computationally complex and time-consuming. The construction method includes: obtaining silicon via array parameter samples; performing thermal stress simulation on the silicon via array based on the silicon via array parameter samples to obtain thermal stress field simulation data; and training an initial model of the TSV array thermal stress field prediction model based on the silicon via array parameter samples and the thermal stress field simulation data to obtain a target TSV array thermal stress field prediction model. This invention provides a method for constructing a TSV array thermal stress field prediction model for high-precision and high-efficiency prediction of the thermal stress field of TSV arrays.

The invention provides an integrated circuit layout design method and device. The method comprises the following steps: formulating a new design rule according to each two-dimensional layout file in the three-dimensional integrated circuit, layer information of the three-dimensional layout file and a layout interconnection relationship between the three-dimensional layout file and each two-dimensional layout file; performing layer mapping and layout merging on each two-dimensional layout file and each three-dimensional layout file to obtain a new layout file; and checking and modifying the new layout file by adopting the new design rule until the new layout file passes the checking. The layout design and verification process can be simplified, and the design period is shortened.

The invention provides a low-temperature and low-voltage copper-copper metal bonding method, and belongs to the technical field of semiconductor packaging. The method comprises the following steps of: firstly, carrying out mechanochemical polishing on the copper column salient point formed by electroplating, reducing the surface roughness of the copper column salient point to a nanoscale to form a high-flatness bonding surface, and then applying a temperature of 290-300 DEG C and a pressure of 100-170 MPa in an air environment, and loading a constant current of 0.5-0.8 A to assist bonding for 30-90 seconds. The surface roughness is remarkably reduced through the CMP technology, the constant-current auxiliary induced electro-plastic effect is combined, rapid and reliable bonding of the copper pillar protruding points is successfully achieved under the low-temperature and low-pressure conditions, and the method is suitable for low-temperature and low-pressure rapid interconnection manufacturing of a three-dimensional integrated circuit (3D IC) and has good application prospects. And particularly, the bonding reliability problem of a heat-sensitive device in high-density packaging is solved.

The application belongs to the technical field of three-dimensional integrated circuits, and discloses a through-silicon via link total dose effect evaluation method, equipment and medium based on an equivalent circuit model, wherein the method comprises the following steps: establishing a total dose equivalent circuit topology structure according to a through-silicon via structure; determining a parasitic electric parameter calculation equation in the total dose effect equivalent circuit; calculating the value of the electric parameter under normal conditions, and comparing the S parameter obtained through simulation calculation with the actually measured S parameter to verify the total dose effect equivalent circuit model; optimizing the design, extracting the electric parameter in the equivalent circuit under different radiation dose conditions; extracting the electric parameter change curve with the radiation dose; fitting the equation of the material attribute change with the radiation dose; and predicting the S parameter of the through-silicon via link at any radiation dose point. The equipment and medium are used for realizing the through-silicon via link total dose effect evaluation method based on the equivalent circuit model. The evaluation factors are comprehensive, the actual irradiation conditions can be better matched, and the performance of the through-silicon via link under the actual radiation conditions can be more accurately simulated.

Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.

The present application relates to the technical field of three-dimensional integrated circuit protection in aerospace radiation environment, and particularly relates to a method and system for simulating and modeling a microsystem interconnection module based on a through silicon via under proton irradiation. The method comprises: constructing a three-dimensional finite element model containing a through silicon via, a redistribution layer and a micro-bump, adjusting material parameters to extract scattering parameters, and establishing a correlation model between material characteristics and scattering parameters; constructing an equivalent RLC circuit in an ADS environment and establishing a corresponding relationship between the equivalent RLC circuit and the scattering parameters; combining a proton irradiation experiment to obtain scattering parameters under different radiation fluences, and further establishing a correlation model between the radiation fluence and the RLC circuit parameters. The present application combines simulation and experimental methods to achieve precise modeling between the radiation dose, the circuit parameters and the scattering characteristics, and provides support for the electrical performance prediction and protection design of three-dimensional microsystems in complex radiation environments.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

The invention discloses a multi-physics field coupling simulation learning method and system for a three-dimensional integrated circuit. The method comprises the following steps: firstly, obtaining a space geometric structure of the three-dimensional integrated circuit and structure attribute parameters and physical attribute parameters of each structure unit forming the space geometric structure; then constructing a three-dimensional coordinate system for the space geometric structure; obtaining stress calculation original data according to the mathematical structure model of each structure unit and the corresponding physical attribute parameters; and finally, inputting the stress calculation original data into the LBO simulation mathematical model to obtain the physical field distribution of the corresponding structural unit output by the LBO simulation mathematical model. Multi-physics field coupling simulation of the three-dimensional integrated circuit is carried out by introducing a physically constrained LBO simulation mathematical model, and rapid estimation of temperature and stress distribution of each device in the three-dimensional integrated circuit can be realized.

Implementing a circuit design for an integrated circuit device having a plurality of dies where each die has a plurality of fabric sub-regions (FSRs) includes detecting an inter-FSR net of the circuit design. A source of the inter-FSR net and an anchor for the inter-FSR net are projected to a selected die of the plurality of dies resulting in a projected source and a projected anchor in the selected die. The inter-FSR net is replaced with a modified inter-FSR net coupling the projected source with the projected anchor in the selected die and a new intra-FSR net coupling the anchor with a load of the inter-FSR net. The circuit design including the modified inter-FSR net and the new intra-FSR net is routed.

Systems, apparatus, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. In a three-dimensional integrated circuit, a first semiconductor die has a second die vertically stacked on top of it. The first die includes through-silicon via (TSV) interconnects that do not penetrate the first die. The first die includes one or more metal layers above the TSVs, said one or more metal layers being connected to a bonding pad interface via bonding pad vias. If signals transmitted through the TSVs of the first die are shared by the second die, the second die includes TSVs aligned with the bonding pad interfaces of the first die. If the second die does not share these signals, the second die includes an insulating portion on the wafer backside aligned with the bonding pad interfaces.

The application relates to the technical field of semiconductor structures, in particular to a three-dimensional electromagnetic bandgap structure based on a through silicon via and an array system, which comprises a dielectric substrate, upper and lower surface metal layers and a via array; the metal layers are provided with central interdigital electrodes for generating planar distributed capacitances and edge comb electrodes for realizing electromagnetic coupling, and the vias connect the upper and lower interdigital electrodes to form a three-dimensional resonant loop; the array system realizes non-contact staggered engagement of the edge comb electrodes of adjacent units, forms distributed field interaction in the staggered area and excites a coupled resonant mode; through superposition of an intrinsic mode and a coupled mode in a frequency domain, a continuous wideband noise suppression stopband is formed, and the electromagnetic compatibility of a three-dimensional integrated circuit is significantly improved.

The invention belongs to the technical field of three-dimensional integrated circuit thermal management. The invention provides a TSV thermal modeling method based on a physical information neural network. According to the embodiment of the invention, the PINN model is constructed, and the multi-stage training strategy and the systematized sensitivity analysis experiment are combined, so that high-precision and high-efficiency prediction of the TSV temperature field is realized. According to the method, the precision better than that of a traditional machine learning method can be achieved only through a small amount of training data, the extrapolation capability is excellent, the prediction result strictly follows the physical law, a novel technical means is provided for thermal reliability design of a three-dimensional integrated circuit, and the design efficiency and the model credibility are remarkably improved.

The application discloses a multi-physical field coupling simulation learning method and system for a three-dimensional integrated circuit, which comprises the following steps: firstly, acquiring a spatial geometric structure of the three-dimensional integrated circuit and structure attribute parameters and physical attribute parameters of each structural unit constituting the spatial geometric structure; then, constructing a three-dimensional coordinate system for the spatial geometric structure; then, acquiring stress calculation original data according to a mathematical structure model of each structural unit and corresponding physical attribute parameters; finally, inputting the stress calculation original data into an LBO simulation mathematical model to acquire physical field distribution of the corresponding structural unit output by the LBO simulation mathematical model. The multi-physical field coupling simulation of the three-dimensional integrated circuit is performed by introducing the LBO simulation mathematical model with physical constraints, so that the temperature and stress distribution of each device in the three-dimensional integrated circuit can be quickly estimated.