23 results about "Three-dimensional integrated circuit" patented technology

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The present disclosure relates to three-dimensional integrated circuits and fabrication thereof. An IC structure includes a first transistor formed on a substrate, a first interconnect structure over the first transistor, a dielectric layer over the first interconnect structure, a plurality of 2D semiconductor islands on the dielectric layer, and a plurality of second transistors formed on the plurality of 2D semiconductor islands.

A method of characterizing a device under test (DUT) includes illuminating the DUT with a broadband optical beam within an optical field of view (FOV), illuminating the DUT with an X-ray beam within an X-ray FOV overlapping the optical FOV, and concurrently acquiring X-ray metrology information, e.g., one or more X-ray images utilizing various modalities, such as absorption, phase contrast difference, darkfield, small angle X-ray scattering (SAXS) and / or fluorescence, from the X-ray FOV and a plurality of optical images of the optical FOV, each of the optical images corresponding to respective selected wavelengths of the broadband optical beam from each of ultraviolet, visible, and infrared wavelengths, for example including deep ultraviolet, near infrared, or short-wavelength infrared wavelengths. The DUT may be one or more substrates, e.g., stacked, and include electronic devices such as three-dimensional integrated devices.

This application discloses a method for fabricating conductive lines on a multilayer co-fired ceramic substrate and the multilayer co-fired ceramic substrate itself, relating to the field of electronic ceramic multilayer co-fired manufacturing technology. The method for fabricating conductive lines on the multilayer co-fired ceramic substrate includes: providing a green ceramic film strip for multilayer stacking and co-firing; forming conductive patterns on the surface of the green ceramic film strip using nanoimprinting technology, aligning and stacking it with at least one other green ceramic film strip, and laminating it to form a stack; and performing adhesive removal and co-firing treatment on the stack to form embedded conductive lines within the stack. The fabrication method proposed in this application can fabricate conductive lines with linewidths and spacings less than 50 μm, achieving embedded forming of conductive lines in multilayer structures. It can be used in conjunction with via drilling / filling and stack alignment processes for precision packaging of three-dimensional integrated circuits such as high-density multilayer wiring, high-frequency and high-speed circuits, and power electronic integration.

The present application relates to the field of advanced semiconductor packaging technology, and particularly relates to a borosilicate system TGV glass interposer composite interconnection structure for three-dimensional integrated circuit packaging and a preparation method and application thereof. The structure comprises a borosilicate glass interposer, a TGV through array penetrating the interposer, a low-loss insulation / adhesion layer arranged on the upper and lower surfaces of the interposer, a fine re-routed layer, a ground shielding via array and a thermal diffusion metal layer. By adopting borosilicate glass as the core material of the interposer, realizing vertical interconnection through TGV, constructing a ground shielding and power integrity enhancement structure around the high-speed signal channel, and introducing a thermal diffusion layer and a stress buffer insulation layer, the requirements of high-density interconnection, low insertion loss, low crosstalk, low warpage and high reliability can be met. The structure is suitable for three-dimensional packaging scenes such as AI accelerator, high-performance computing, radio frequency front end, co-packaged optical and high-reliability sensor.

Mechanisms to improve the thermal conductivity of three-dimensional integrated circuit (3DIC) structures by thinning the metal and dielectric layers in comparison to the dimensions of these layers in conventional 3DIC structures, resulting in a commensurate thinning of the oxide layers between active layers and metal layers, and a reduction in the number of metal and oxide layers utilized compared to conventional 3DIC structures.

This invention discloses a type 0-3 polymer ferroelectric composite material for use in integrated circuit interposers and its preparation method. The composite material consists of an epoxy resin matrix and KBiFe2O5 ferroelectric powder dispersed therein, with 100 parts by mass of epoxy resin and 5-50 parts by mass of KBiFe2O5. KBiFe2O5 has a layered perovskite structure and a low intrinsic dielectric constant (<3.5), and a coefficient of thermal expansion of only 1.6-10 ppm / K. Surface modification of the ferroelectric powder with a silane coupling agent can significantly improve its interfacial bonding strength with the epoxy resin. This invention utilizes a type 0-3 composite structure to achieve adjustable coefficient of thermal expansion of the composite material within the range of 3-20 ppm / K while maintaining a low dielectric constant (3.0-3.8@1 MHz) and low dielectric loss (<0.005@1 MHz), enabling good matching with silicon chips (CTE approximately 3-5 ppm / K) and effectively reducing thermal cycling stress. The composite material has a simple preparation process, is compatible with existing packaging production lines, and is suitable for use as an interposer material in three-dimensional integrated circuit packaging, showing promising application prospects.

Clock calibration adjustments are provided. Some embodiments disclosed herein are related to a device. A device can include a first conductive element configured to receive a first signal at a first functional block. The device can include a second conductive element configured to convey the first signal to a second functional block of the device. The device can include a third conductive element to receive a second signal from the second functional block, the second signal varying from the first signal according to a phase-shift. The device can include a first circuit configured to determine the phase-shift between the first signal and the second signal. The device can include a second circuit configured to generate a third signal based on the phase-shift, the first signal, the second signal.

The present application relates to the technical field of three-dimensional integrated circuit protection in aerospace radiation environment, and particularly relates to a method and system for simulating and modeling a microsystem interconnection module based on a through silicon via under proton irradiation. The method comprises: constructing a three-dimensional finite element model containing a through silicon via, a redistribution layer and a micro-bump, adjusting material parameters to extract scattering parameters, and establishing a correlation model between material characteristics and scattering parameters; constructing an equivalent RLC circuit in an ADS environment and establishing a corresponding relationship between the equivalent RLC circuit and the scattering parameters; combining a proton irradiation experiment to obtain scattering parameters under different radiation fluences, and further establishing a correlation model between the radiation fluence and the RLC circuit parameters. The present application combines simulation and experimental methods to achieve precise modeling between the radiation dose, the circuit parameters and the scattering characteristics, and provides support for the electrical performance prediction and protection design of three-dimensional microsystems in complex radiation environments.

Systems, apparatus, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. In a three-dimensional integrated circuit, a first semiconductor die has a second die vertically stacked on top of it. The first die includes through-silicon via (TSV) interconnects that do not penetrate the first die. The first die includes one or more metal layers above the TSVs, said one or more metal layers being connected to a bonding pad interface via bonding pad vias. If signals transmitted through the TSVs of the first die are shared by the second die, the second die includes TSVs aligned with the bonding pad interfaces of the first die. If the second die does not share these signals, the second die includes an insulating portion on the wafer backside aligned with the bonding pad interfaces.

The application discloses a multi-physical field coupling simulation learning method and system for a three-dimensional integrated circuit, which comprises the following steps: firstly, acquiring a spatial geometric structure of the three-dimensional integrated circuit and structure attribute parameters and physical attribute parameters of each structural unit constituting the spatial geometric structure; then, constructing a three-dimensional coordinate system for the spatial geometric structure; then, acquiring stress calculation original data according to a mathematical structure model of each structural unit and corresponding physical attribute parameters; finally, inputting the stress calculation original data into an LBO simulation mathematical model to acquire physical field distribution of the corresponding structural unit output by the LBO simulation mathematical model. The multi-physical field coupling simulation of the three-dimensional integrated circuit is performed by introducing the LBO simulation mathematical model with physical constraints, so that the temperature and stress distribution of each device in the three-dimensional integrated circuit can be quickly estimated.

Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.

The application discloses a TGV interlayer-copper paste interconnection-high thermal conductivity and low loss insulation material collaborative packaging structure for three-dimensional integrated circuit packaging and a preparation method thereof, and belongs to the technical field of advanced electronic packaging materials. The structure comprises a TGV glass interlayer with low dielectric and adjustable thermal expansion coefficient, a high-uniformity metal interconnection structure formed by filling and sintering of functional copper paste, and a high-thermal-conductivity and low-loss insulation packaging layer. Through collaborative design of the interlayer material, the copper paste interconnection material and the insulation packaging material, excellent high-frequency electrical performance, thermal management performance and structural reliability can be realized. The application has simplified process and controllable cost, and is suitable for three-dimensional packaging application scenarios such as AI accelerators, high-performance computing, radio frequency front ends and heterogeneous integration.

The present application belongs to the field of three-dimensional integrated circuit, high-power semiconductor heat dissipation and cooling technology, and is a double-layer cooling heat sink for gas-liquid separation. The double-layer cooling heat sink is composed of a gas-liquid separation cavity (1), a framework (2) and a heat transfer enhancement cavity (3). The present application has the advantages of using a double-layer design, so that the cooling medium is subjected to twice heat exchange inside the heat sink, and the cooling medium works more fully. The flower-shaped rib columns in the gas-liquid separation cavity (1) can improve the nucleation point density and be beneficial to the generation of bubbles. In the heat transfer enhancement cavity (3), the fan blades of the rotating rib columns can help to cause rotational flow, add fluid disturbance and improve the cooling efficiency to realize secondary heat exchange. The designed framework (2) structure connects the liquid separation cavity (1) and the heat transfer enhancement cavity (3), and can simultaneously exchange heat for two chips.

The memory layer and the digital device layer are configured as a three-dimensional integrated circuit (IC) die stack. The digital device layer (304) has a first surface (side) positioned closest to the cooling solution (308), and the memory layer is positioned on a second surface (side) of the digital device layer opposite the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer (304) and the memory layer (302). Through-silicon vias (TSVs) (314) through the memory layer and reaching the digital device layer are used to interconnect signals, controls, and power supply voltages to circuitry in these layers. Some of the TSVs are used to couple to external connections of the memory stack device. The digital device layer can be a complex electronic device layer such as a microprocessor or microcontroller for improved high speed signal transfer.

An intelligent imager comprising a three-dimensional integrated circuit having a stack of at least two integrated circuit layers: a sensor layer with a pixel array, and one or more processing layers. The three-dimensional integrated circuit includes: a conversion block (30) comprising a plurality of analog-to-digital converters (31) at the base of each pixel column; a parallel processing processor (40) comprising several processing units (41), each comprising several elementary processors (42) and a shared memory (43); a data bus (50); and a control block (60) configured to route the digital data output from the conversion block (30) directly to the shared memories (43) of the processing units (41), with the digital data representing the same pixel row being routed simultaneously to different processing units (41). Figure for the abstract: Fig. 1

Devices and methods for testing interconnect lanes of multichip packages with memory test algorithms are provided. The multichip packages that can be tested can comprise a plurality of semiconductor dies mounted on an active interposer.

This application discloses a design method and layout structure for three-dimensional integrated circuits, applicable to the field of integrated circuit design. The method first determines the first process technology used in the first device layer and the second process technology used in the second device layer. Then, based on the process design kit corresponding to the first process technology and the general simulation program model of the integrated circuit corresponding to the second process technology, circuit simulation is performed to determine the dimensions of the second type of device using the second process technology. Finally, based on the process design kit corresponding to the first process technology, the dimensions of the second type of device, and the vertical interconnect channels used to realize the electrical connection between the first type of device using the first process technology and the second type of device, a three-dimensional integrated circuit layout is designed. Thus, by vertically stacking, the projected area of ​​the logic cells approaches the area of ​​a single transistor, significantly reducing the integrated circuit layout area.

This invention provides a method for fabricating a TSV structure in a three-dimensional integrated circuit package. By employing an insulating film layer that can be patterned using photolithography and blocks the diffusion of copper particles during the formation of the TSV holes, this insulating film layer serves both as a mask layer for etching the TSV holes and as an insulating dielectric layer for the TSV structure. This dual-function insulating film layer allows for the etching of TSV holes using only this single insulating film layer, effectively reducing process steps and manufacturing costs. Furthermore, the insulating film layer's ability to block copper particle diffusion significantly reduces the risk of Cu particles generated during CMP polishing of the Cu-filled layer / blocking adhesion layer composite interface diffusing into the insulating film layer, thereby improving the electrical properties and reliability of the package.

Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).

Embodiments relate to a three-dimensional integrated circuit (3D IC) fabrication process involving wafer-to-wafer bonding of a first wafer to a second wafer. The process includes partially cutting trenches in the second wafer's streets, aligning interconnects between the two wafers, and coupling them to form a wafer stack. The second wafer is then thinned to expose the partially cut trenches, and materials between the second wafer's dies are removed to expose die pads on the first wafer for external connection, enabling the creation of a 3D IC with improved connectivity and functionality.