Three-dimensional integrated circuit structure and method of making same

Abstract

Vertically oriented semiconductor devices may be added to a separately fabricated substrate that includes electrical devices and / or interconnect. The plurality of vertically oriented semiconductor devices are physically separated from each other, and are not disposed within the same semiconductor body, or semiconductor substrate. The plurality of vertically oriented semiconductor devices may be added to the separately fabricated substrate as a thin layer including several doped semiconductor regions which, subsequent to attachment, are etched to produce individual doped stack structures. Alternatively, the plurality of vertically oriented semiconductor devices may be fabricated prior to attachment to the separately fabricated substrate. The doped stack structures may form the basis for diodes, capacitors, n-MOSFETs, p-MOSFETs, bipolar transistors, and floating gate transistors. Ferroelectric memory devices, Ferromagnetic memory devices, chalcogenide phase change devices, may be formed in a stackable add-on layer for use in conjunction with a separately fabricated substrate. Stackable add-on layers may include interconnect lines.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to three dimensional integrated circuit (IC) structures and manufacturing methods therefore, and more particularly relates to combining a semiconductor substrate with a thin add-on semiconductor layer in which various active and / or passive devices have been fabricated. [0002] As shown in FIG. 1, a prior art 3-D IC might be termed a ‘Hybrid IC’. A conventional Hybrid IC implementation method typically includes; providing a first IC which consists of a base semiconductor substrate 201 and a dielectric layer 202; providing a second IC that also consists of a base semiconductor substrate 203 and a dielectric layer 204; stacking and bonding these ICs, or individual chips; and implementing a deep via 255 such as shown in U.S. Pat. No. 6,600,173 which penetrates the semiconductor substrate, or providing micro bumps as shown in U.S. Pat. No. 6,355,501. [0003] Still referring to FIG. 1, it is noted that devices in the stac...

AI Technical Summary

Problems solved by technology

However, both the laser recrystallization and the epitaxial processes described above are have drawbacks, such as requiring high temperature operations, which are incompatible with the low temperature processing required for many semiconductor devices; and further, single crystalline semiconductor layers formed in this way may have many defects, and therefore these methods are not widely used.

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