Voltage control circuit and display device

Abstract

The present invention proposes a voltage control circuit and a display device, wherein the voltage control circuit includes a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit. The power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when the power is turned on or off. The comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly. The switch control circuit controls the on and off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit. Through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected. When a voltage rebound occurs during the power-off process, the first switch circuit can be effectively kept off to prevent the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from abnormally powering on and causing screen abnormalities or flickering problems, thereby improving the display quality and user experience of the display device.

Description

Technical Field

[0001] The present invention belongs to the technical field of display devices, and in particular relates to a voltage control circuit and a display device. Background Art

[0002] In a display device, a mainboard is usually used to provide a power supply voltage to a power management integrated circuit, and the power management integrated circuit provides an operating power supply to a display panel and a corresponding driving circuit.

[0003] During the shutdown process, the power supply voltage gradually decreases, and the power management integrated circuit and the back-end load will stop working. The sudden power failure of the load will cause the power supply voltage to rebound. When the rebound voltage is too high, the power management integrated circuit will restart abnormally and instantly, which will cause the display panel to power on abnormally, resulting in abnormal screen or flickering on the display panel. Summary of the Invention

[0004] The present invention aims to provide a voltage control circuit to solve the problem in which voltage rebound occurs during power failure in conventional display devices, causing abnormal restart of the power management integrated circuit and abnormal or flickering images on the display panel.

[0005] A first aspect of an embodiment of the present invention provides a voltage control circuit, including:

[0006] a first switch circuit, wherein an input end of the first switch circuit is used to input a power supply voltage, an output end of the first switch circuit is connected to a power input end of a power management integrated circuit of the display device, and the first switch circuit is triggered to turn on by a first level signal and to turn off by a second level signal;

[0007] a power-on reset circuit, wherein an input terminal of the power-on reset circuit is used to input a supply voltage, the power-on reset circuit is configured to charge the supply voltage when it is powered on, and output a third level signal when it is charged to a first reference voltage, and output a fourth level signal when it is not charged to the first reference voltage or when the supply voltage is powered down to the first reference voltage, wherein the supply voltage rises to reach a second reference voltage when the power-on reset circuit is charged to the first reference voltage;

[0008] a comparison circuit, configured to compare the supply voltage with the second reference voltage, and output a fifth level signal when the supply voltage is greater than or equal to the second reference voltage, and output a sixth level signal when the supply voltage is less than the second reference voltage;

[0009] a switch control circuit, connected to the first switch circuit, the power-on reset circuit, and the comparison circuit, respectively. The switch control circuit is configured to output the first-level signal upon receiving the fourth-level signal or simultaneously receiving the third-level signal and the fifth-level signal during power-on, and to trigger output of the second-level signal upon simultaneously receiving the third-level signal and the sixth-level signal during power-off, until the fourth-level signal is received and the first-level signal is switched to be output.

[0010] Optionally, the power-on reset circuit includes a first resistor, a first capacitor and a first comparator;

[0011] The first end of the first resistor is used to input the supply voltage, the second end of the first resistor, the first end of the first capacitor and the non-inverting input end of the first comparator are connected, the second end of the first capacitor is grounded, the inverting input end of the first comparator is used to input the first reference voltage, and the output end of the first comparator constitutes the output end of the power-on reset circuit.

[0012] Optionally, the comparison circuit includes a second resistor, a third resistor, a fourth resistor, a voltage regulator diode and a second comparator;

[0013] The first end of the second resistor and the non-inverting input end of the second comparator are used to input the supply voltage, the second end of the second resistor, the first end of the third resistor, the cathode of the voltage regulator tube and the inverting input end of the second comparator are connected, the second end of the third resistor, the first end of the fourth resistor and the reference voltage end of the voltage regulator tube are connected, the second end of the fourth resistor and the anode of the voltage regulator tube are grounded, and the output end of the second comparator constitutes the output end of the comparison circuit.

[0014] Optionally, the switch control circuit includes a first NAND gate and a second NAND gate;

[0015] The first input end of the first NAND gate is connected to the output end of the power-on reset circuit, the first input end of the second NAND gate is connected to the output end of the comparison circuit, the output end of the first NAND gate is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the second input end of the first NAND gate to form the output end of the switch control circuit.

[0016] Optionally, a load capacitor is further connected between the power input terminal of the power management integrated circuit and the ground;

[0017] The voltage control circuit further includes:

[0018] a second switch circuit, wherein an input end of the second switch circuit is used to input a power supply voltage, an output end of the second switch circuit is connected to a power input end of the power management integrated circuit, and the second switch circuit is triggered to be turned on by the seventh level signal and triggered to be turned off by the eighth level signal;

[0019] A time detection circuit, wherein the input end of the time detection circuit is used to input the supply voltage, the output end of the time detection circuit is connected to the control end of the second switching circuit, and the time detection circuit is used to compare the supply voltage with a third reference voltage and a fourth reference voltage respectively, and output the seventh level signal when the supply voltage is between the third reference voltage and the fourth reference voltage and lasts for a preset time length, otherwise output the eighth level signal, wherein the third reference voltage is greater than the second reference voltage and less than the steady-state voltage of the supply voltage, and the fourth reference voltage is greater than the steady-state voltage of the supply voltage.

[0020] Optionally, the time detection circuit includes:

[0021] a window comparator circuit, wherein an input terminal of the window comparator circuit is used to input the supply voltage, the window comparator circuit is used to compare the supply voltage with a third reference voltage and a fourth reference voltage, respectively, and output a ninth level signal when the supply voltage is between the third reference voltage and the fourth reference voltage, and output a tenth level signal when the supply voltage is not between the third reference voltage and the fourth reference voltage;

[0022] a delay trigger circuit connected between the second switch circuit and the window comparator circuit, the delay trigger circuit being configured to charge upon receiving the ninth level signal and output the seventh level signal when the charging time reaches a preset time length, and to trigger the eighth level signal upon receiving the ninth level signal and charging when the charging time does not reach the preset time length or when receiving the tenth level signal.

[0023] Optionally, the window comparison circuit includes a third comparator, a fourth comparator, a first diode, a second diode and an inverter;

[0024] The inverting input terminal of the third comparator is used to input the fourth reference voltage, the non-inverting input terminal of the fourth comparator is used to input the third reference voltage, the non-inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are used to input the supply voltage, the output terminal of the third comparator is connected to the anode of the second diode, the output terminal of the fourth comparator is connected to the anode of the first diode, the cathode of the first diode, the cathode of the second diode and the input terminal of the inverter are connected, and the output terminal of the inverter constitutes the output terminal of the window comparator circuit.

[0025] Optionally, the delay trigger circuit includes a fifth resistor, a sixth resistor, a third diode, a second capacitor and a D trigger;

[0026] The first end of the fifth resistor is grounded, the second end of the fifth resistor, the cathode of the third diode, the first end of the sixth resistor and the reset end of the D trigger constitute the input end of the delay trigger circuit, the anode of the third diode, the second end of the sixth resistor, the first end of the second capacitor and the clock end of the D trigger are connected, the second end of the second capacitor is grounded, the data end and the power supply end of the D trigger are used to input the power supply voltage, and the output end of the D trigger constitutes the output end of the delay trigger circuit.

[0027] Optionally, the first switching circuit includes a first electronic switching tube, and a first end, a second end and a control end of the first electronic switching tube constitute the input end, the output end and the control end of the first switching circuit respectively;

[0028] The second switch circuit includes a second electronic switch tube, and the first end, the second end and the control end of the second electronic switch tube respectively constitute the input end, the output end and the control end of the second switch circuit.

[0029] A second aspect of an embodiment of the present invention provides a display device, comprising a power management integrated circuit and the voltage control circuit as described above, wherein the voltage control circuit is connected to a power input terminal of the power management integrated circuit.

[0030] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the voltage control circuit includes a first switching circuit, a power-on reset circuit, a comparison circuit and a switch control circuit; the power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when powered on or powered off; the comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly; the switch control circuit controls the on and off of the first switching circuit based on the level signals output by the power-on reset circuit and the comparison circuit; through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected; when a voltage rebound occurs during the power-off process, the first switching circuit can be effectively kept off, preventing the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from having abnormal screen or screen flickering problems caused by abnormal power-on, thereby improving the display quality and user experience of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic structural diagram of a voltage control circuit provided in Embodiment 1 of the present invention;

[0032] Figure 2 A schematic diagram of voltage changes of the voltage control circuit provided in the first embodiment of the present invention;

[0033] Figure 3 A circuit diagram of a voltage control circuit provided in Embodiment 2 of the present invention;

[0034] Figure 4 A schematic diagram of a first structure of a voltage control circuit provided in the third embodiment of the present invention;

[0035] Figure 5 A schematic diagram of voltage changes of a voltage control circuit provided in the third embodiment of the present invention;

[0036] Figure 6 A second structural diagram of the voltage control circuit provided in the third embodiment of the present invention;

[0037] Figure 7 A circuit diagram of a second switch circuit and a time detection circuit provided in a fourth embodiment of the present invention;

[0038] Figure 8 This is a structural diagram of a display device provided in Example 5 of the present invention.

[0039] Among them, the reference numerals in the figures are:

[0040] 100, voltage control circuit; 200, power management integrated circuit; 10, first switch circuit; 20, power-on reset circuit; 30, comparison circuit; 40, switch control circuit; 50, second switch circuit; 60, time detection circuit; 61, window comparison circuit; 62, delay trigger circuit;

[0041] R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; C1, first capacitor; C2, second capacitor; Cr, load capacitor; U1, first comparator; U2, second comparator; U3, first NAND gate; U4, second NAND gate; U5, third comparator; U6, fourth comparator; U7, inverter; U8, D flip-flop; D1, first diode; D2, second diode; D3, third diode; ZD, voltage regulator; M1, first electronic switch; M2, second electronic switch;

[0042] VCC, supply voltage; Vref1, first reference voltage; Vref2, second reference voltage; Vref3, third reference voltage; Vref4, fourth reference voltage; Vin, power input terminal; V0, steady-state voltage; Vth, threshold voltage. DETAILED DESCRIPTION

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0045] Example 1

[0046] A first aspect of an embodiment of the present invention proposes a voltage control circuit 100, which is connected to a power management integrated circuit 200 of a display device, wherein the power management integrated circuit 200 includes a power input terminal Vin and at least one power output terminal. The power input terminal Vin is used to connect to a mainboard and obtain a power supply voltage VCC. When the power supply voltage VCC is greater than a threshold voltage Vth, the power management integrated circuit 200 starts and outputs an operating voltage to each module at the back end, such as outputting multiple operating voltages to a timing controller, a source driver circuit, a gate driver circuit, and a display panel in the display device. The source driver circuit is used to output a data signal under the control of the timing controller, and the gate driver circuit is used to output a scan signal under the control of the timing controller and scan the display panel line by line. The display panel displays corresponding image information under the drive of the data signal and the scan signal.

[0047] When voltage rebound occurs, the power management integrated circuit 200 restarts abnormally, causing the source driving circuit and the gate driving circuit to abnormally output data signals and scan signals, and causing the display panel to display abnormal images or flickering screens.

[0048] In order to solve this problem, in this embodiment, a voltage control circuit is proposed for detecting the power-off voltage. When a voltage rebound occurs during the power-off process, the power supply of the power management integrated circuit 200 can be effectively kept in the off state, thereby preventing the power management integrated circuit 200 from restarting abnormally, effectively preventing the display panel from having abnormal screen abnormalities or screen flickering problems caused by abnormal power-on, and improving the display quality and user experience of the display device.

[0049] like Figure 1 As shown, in this embodiment, the voltage control circuit 100 includes:

[0050] A first switch circuit 10, wherein the input end of the first switch circuit 10 is used to input a power supply voltage VCC, and the output end of the first switch circuit 10 is connected to the power input end Vin of the power management integrated circuit 200 of the display device. The first switch circuit 10 is triggered to turn on by a first level signal and to turn off by a second level signal;

[0051] a power-on reset circuit 20, wherein the input terminal of the power-on reset circuit 20 is used to input the supply voltage VCC. The power-on reset circuit 20 is configured to charge the supply voltage VCC when it is powered on and output a third level signal when it is charged to the first reference voltage Vref1, and output a fourth level signal when it is not charged to the first reference voltage Vref1 or when the supply voltage VCC is powered down to the first reference voltage Vref1. When the power-on reset circuit 20 is charged to the first reference voltage Vref1, the supply voltage VCC rises to reach the second reference voltage Vref2;

[0052] a comparison circuit 30 for comparing the power supply voltage VCC with the second reference voltage Vref2, and outputting a fifth level signal when the power supply voltage VCC is greater than or equal to the second reference voltage Vref2, and outputting a sixth level signal when the power supply voltage VCC is less than the second reference voltage Vref2;

[0053] The switch control circuit 40 is connected to the first switch circuit 10, the power-on reset circuit 20 and the comparison circuit 30 respectively. The switch control circuit 40 is configured to output the first level signal when receiving the fourth level signal or the third level signal and the fifth level signal at the time of power-on, and to trigger the output of the second level signal when receiving the third level signal and the sixth level signal at the time of power-off until the fourth level signal is received and the first level signal is switched to be output.

[0054] In this embodiment, reference Figure 2 As shown, when the power supply voltage VCC is powered on, the power-on reset circuit 20 begins charging. When the power-on reset circuit 20 has not yet charged to the first reference voltage Vref1, the power-on reset circuit 20 outputs a fourth-level signal. After receiving the fourth-level signal, the switch control circuit 40 outputs a first-level signal. Triggered by the first-level signal, the first switch circuit 10 turns on, and the power supply voltage VCC is input to the power input terminal Vin of the power management integrated circuit 200 through the first switch circuit 10. During the reset period, regardless of whether the comparison circuit 30 outputs the fifth-level signal or the sixth-level signal, the switch control circuit 40 maintains outputting the first-level signal, without affecting the switching state of the first switch circuit 10, thereby forcibly resetting the first switch circuit 10. The reset time t1 is determined by the capacitance and resistance in the power-on reset circuit 20.

[0055] When the power-on reset circuit 20 is charged to the first reference voltage Vref1, the power-on reset circuit 20 outputs a third-level signal. At this time, the supply voltage VCC has risen to the second reference voltage Vref2, and the comparison circuit 30 outputs a fifth-level signal. The switch control circuit 40 receives the third-level signal and the fifth-level signal at the same time and continues to output the first-level signal. The first switch circuit 10 remains in the on state.

[0056] When the power supply voltage VCC is powered off, the power supply voltage VCC begins to drop. When the power supply voltage VCC drops below the second reference voltage Vref2, the comparison circuit 30 outputs a sixth level signal. The switch control circuit 40 receives the third level signal and the sixth level signal at the same time, triggering the output of the second level signal. The first switch circuit 10 is turned off under the triggering of the second level signal, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. During the power-off process, even if the power supply voltage VCC rebounds and exceeds the second reference voltage Vref2, the switch control circuit 40 continues to output the second level signal, the first switch circuit 10 remains in the off state, the power management integrated circuit 200 will not start working, the power management integrated circuit 200 remains in the off state, no working voltage is output, the corresponding source drive circuit and the gate drive circuit have no signal output, and the display panel is normally off to avoid display abnormalities or screen flickering.

[0057] When the supply voltage VCC continues to drop below the first reference voltage Vref1, the power-on reset circuit 20 outputs a fourth-level signal. After receiving the fourth-level signal, the switch control circuit 40 switches to outputting the first-level signal. Triggered by the first-level signal, the first switch circuit 10 turns on, and the supply voltage VCC is again input to the power input terminal Vin of the power management integrated circuit 200 through the first switch circuit 10. At this point, because the supply voltage VCC is already less than the threshold voltage Vth of the power management integrated circuit 200, the power management integrated circuit 200 is powered off and does not start operating. The power management integrated circuit 200 remains in the off state, with no operating voltage output.

[0058] Among them, the first switching circuit 10 can adopt the corresponding switching tube, the power-on reset circuit 20 can adopt the corresponding capacitor, comparator and other structures, the comparison circuit 30 can adopt the corresponding comparator, inverter U7, etc., and the switch control circuit 40 can adopt the corresponding trigger, memory and other structures.

[0059] Through the cooperation of the power-on reset circuit 20, the comparison circuit 30 and the switch control circuit 40, the power-off voltage can be detected. When the voltage rebounds during the power-off process, the first switch circuit 10 can be effectively kept off to prevent the power management integrated circuit 200 from restarting abnormally, thereby effectively preventing the display panel from having abnormal screen or screen flickering problems caused by abnormal power-on, thereby improving the display quality and user experience of the display device.

[0060] Example 2

[0061] like Figure 3 As shown, in an optional embodiment, the power-on reset circuit 20 includes a first resistor R1, a first capacitor C1 and a first comparator U1;

[0062] A first end of the first resistor R1 is used to input a power supply voltage VCC, a second end of the first resistor R1, a first end of the first capacitor C1, and a non-inverting input end of the first comparator U1 are connected, a second end of the first capacitor C1 is grounded, an inverting input end of the first comparator U1 is used to input a first reference voltage Vref1, and an output end of the first comparator U1 constitutes an output end of the power-on reset circuit 20.

[0063] The comparison circuit 30 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a voltage regulator diode ZD and a second comparator U2;

[0064] The first end of the second resistor R2 and the non-inverting input end of the second comparator U2 are used to input the power supply voltage VCC. The second end of the second resistor R2, the first end of the third resistor R3, and the cathode of the voltage-stabilizing diode ZD are connected to the inverting input end of the second comparator U2. The second end of the third resistor R3, the first end of the fourth resistor R4, and the reference voltage end of the voltage-stabilizing diode ZD are connected. The second end of the fourth resistor R4 and the anode of the voltage-stabilizing diode ZD are grounded. The output end of the second comparator U2 constitutes the output end of the comparison circuit 30.

[0065] The switch control circuit 40 includes a first NAND gate U3 and a second NAND gate U4;

[0066] A first input terminal of the first NAND gate U3 is connected to the output terminal of the power-on reset circuit 20, a first input terminal of the second NAND gate U4 is connected to the output terminal of the comparison circuit 30, the output terminal of the first NAND gate U3 is connected to the second input terminal of the second NAND gate U4, and the output terminal of the second NAND gate U4 is connected to the second input terminal of the first NAND gate U3 to form the output terminal of the switch control circuit 40.

[0067] The first switch circuit 10 includes a first electronic switch tube M1 , wherein a first terminal, a second terminal and a control terminal of the first electronic switch tube M1 respectively constitute an input terminal, an output terminal and a control terminal of the first switch circuit 10 .

[0068] In this embodiment, the first electronic switch tube M1 can be selected as an NMOS tube or a PMOS tube. In an optional embodiment, the first electronic switch tube M1 is a PMOS tube. Correspondingly, the first level signal is a low level signal, the second level signal is a high level signal, the first NAND gate U3 and the second NAND gate U4 form an SR trigger, the output end of the power-on reset circuit 20 is connected to the reset end R of the SR trigger, and the output end of the comparison circuit 30 is connected to the set end S of the SR trigger.

[0069] The second reference voltage Vref2 is provided by the voltage regulator diode ZD, Vref2=VR(1+R3 / R4), where VR is the reference voltage provided by the voltage regulator diode ZD, for example, 1.25V.

[0070] The first reference voltage Vref1 can be set according to requirements, for example, 1V.

[0071] When the supply voltage VCC is applied, in the power-on reset circuit 20, the supply voltage VCC charges the first capacitor C1 through the first resistor R1. If the voltage at the terminal of the first capacitor C1 has not yet reached the first reference voltage Vref1, the first comparator U1 outputs a low-level fourth-level signal. The reset terminal R of the SR flip-flop receives a low level, and the SR flip-flop outputs a low-level first-level signal. Triggered by the first-level signal, the first electronic switch M1 turns on. The supply voltage VCC is input to the power input terminal Vin of the power management integrated circuit 200 through the first electronic switch M1. During the reset period, regardless of whether the second comparator U2 outputs a high or low level, the SR flip-flop maintains a low output, which does not affect the switching state of the first electronic switch M1, thereby forcing a reset of the first electronic switch M1. The reset time t1 is determined by the first resistor R1 and the first capacitor C1 in the power-on reset circuit 20: t1 = -R1*C1*ln(1-Vref1).

[0072] When the reset is completed, the first capacitor C1 is charged and rises to the first reference voltage Vref1, and the first comparator U1 outputs a high third-level signal. At this time, the supply voltage VCC has risen to the second reference voltage Vref2, and the second comparator U2 outputs a high fifth-level signal. The SR trigger continues to output a low first-level signal, and the first electronic switch tube M1 remains in the on state.

[0073] When the power supply voltage VCC is powered off, the power supply voltage VCC begins to drop. When the power supply voltage VCC drops below the second reference voltage Vref2, the second comparator U2 outputs a low-level sixth-level signal. At this time, the set terminal S of the SR trigger is 0, and the reset terminal R is 1. The SR trigger is set and switches to output a high-level second-level signal. The first electronic switch tube M1 is triggered to turn off, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. During the power-off process, even if the power supply voltage VCC rebounds and exceeds the second reference voltage Vref2, the SR trigger continues to output the high-level second-level signal, the first electronic switch tube M1 remains in the off state, the power management integrated circuit 200 will not start working, and the power management integrated circuit 200 remains in the off state, with no working voltage output. The corresponding source drive circuit and gate drive circuit have no signal output, and the display panel is normally off to avoid display abnormalities or screen flickering.

[0074] When the supply voltage VCC continues to drop below the first reference voltage Vref1, the first capacitor C1 begins to discharge, and the first comparator U1 outputs a low-level fourth-level signal. After receiving the low-level fourth-level signal, the reset terminal R of the SR flip-flop switches to outputting the first-level signal. Triggered by the first-level signal, the first electronic switch M1 turns on, and the supply voltage VCC is again input to the power input terminal Vin of the power management integrated circuit 200 through the first electronic switch M1. At this point, because the supply voltage VCC is already less than the threshold voltage Vth of the power management integrated circuit 200, the power management integrated circuit 200 is powered off and will not start operating. The power management integrated circuit 200 remains in the off state, with no operating voltage output.

[0075] Example 3

[0076] like Figure 4 As shown, a load capacitor Cr is further connected between the power input terminal Vin of the power management integrated circuit 200 and ground. When the power management integrated circuit 200 is quickly turned on and off, due to the presence of the load capacitor Cr, the charge in the load capacitor Cr cannot be completely discharged every time. As the number of times accumulates, the supply voltage VCC may not be completely powered off and restarted. In this case, when the first switch circuit 10, the power-on reset circuit 20, the comparison circuit 30, and the switch control circuit 40 are used to determine whether the power failure is a normal restart or a voltage rebound, it may be impossible to determine whether it is a normal restart or a voltage rebound. In order to accurately identify the two states, in an optional embodiment, the voltage control circuit 100 further includes:

[0077] A second switch circuit 50, wherein the input terminal of the second switch circuit 50 is used to input the power supply voltage VCC, the output terminal of the second switch circuit 50 is connected to the power input terminal Vin of the power management integrated circuit 200, and the second switch circuit 50 is triggered to be turned on by the seventh level signal and triggered to be turned off by the eighth level signal;

[0078] The time detection circuit 60 has an input terminal for inputting the power supply voltage VCC, and an output terminal of the time detection circuit 60 is connected to the control terminal of the second switch circuit 50. The time detection circuit 60 is used to compare the power supply voltage VCC with the third reference voltage Vref3 and the fourth reference voltage Vref4, respectively, and output a seventh-level signal when the power supply voltage VCC is between the third reference voltage Vref3 and the fourth reference voltage Vref4 and lasts for a preset time period, otherwise output an eighth-level signal, wherein the third reference voltage Vref3 is greater than the second reference voltage Vref2 and less than the steady-state voltage V0 of the power supply voltage VCC, and the fourth reference voltage Vref4 is greater than the steady-state voltage V0 of the power supply voltage VCC.

[0079] In this embodiment, the third reference voltage Vref3 and the fourth reference voltage Vref4 are set accordingly based on the steady-state voltage V0. For example, if the steady-state voltage V0 is 5V, the third reference voltage Vref3 can be set to 4.5V, and the fourth reference voltage Vref4 can be set to 5.5V. Correspondingly, the second reference voltage Vref2 can be set to 4V.

[0080] The time detection circuit 60 monitors the change of the power supply voltage VCC, referring to Figure 5 As shown, when the power supply voltage VCC rebounds after power failure, when the power supply voltage VCC is less than the second reference voltage Vref2, the first switch circuit 10, the power-on reset circuit 20, the comparison circuit 30 and the switch control circuit 40 perform detection and judgment. At this time, the first switch circuit 10 remains in the off state.

[0081] When the power supply voltage VCC loses power and is between the second reference voltage Vref2 and the third reference voltage Vref3, the time detection circuit 60 starts to work. At this time, the time detection circuit 60 detects that the power supply voltage VCC is not between the third reference voltage Vref3 and the fourth reference voltage Vref4. The time detection circuit 60 outputs an eighth level signal, and the second switch circuit 50 is turned off, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. The power management integrated circuit 200 switches to the shutdown state, no working voltage is output, and the corresponding source drive circuit and gate drive circuit have no signal output. The display panel is normally off to avoid display abnormalities or screen flickering.

[0082] When the power supply voltage VCC rebounds to between the third reference voltage Vref3 and the fourth reference voltage Vref4 during power failure and the time does not reach the preset time length, it indicates that the current power supply voltage VCC is in a power failure rebound state. At this time, the time detection circuit 60 outputs an eighth level signal, the second switch circuit 50 is turned off, and the connection between the power supply voltage VCC and the power input terminal Vin of the power management integrated circuit 200 is disconnected. The power management integrated circuit 200 maintains the shutdown state, no working voltage is output, and the corresponding source drive circuit and gate drive circuit have no signal output.

[0083] When the power supply voltage VCC rebounds after power failure or restarts and rises to between the third reference voltage Vref3 and the fourth reference voltage Vref4 and the time reaches the preset duration, it indicates that the current power supply voltage VCC is in a normal restart state, the time detection circuit 60 outputs a seventh level signal, the second switch circuit 50 is triggered to turn on, and the power management integrated circuit 200 starts normally, thereby realizing the normal restart operation of the power management integrated circuit 200.

[0084] The second switch circuit 50 may adopt a corresponding switch tube, and the time detection circuit 60 may adopt a corresponding comparator, trigger, etc. In an optional embodiment, as shown in FIG. Figure 6 As shown, the time detection circuit 60 includes:

[0085] a window comparator circuit 61, wherein an input terminal of the window comparator circuit 61 is used to input a power supply voltage VCC. The window comparator circuit 61 is configured to compare the power supply voltage VCC with a third reference voltage Vref3 and a fourth reference voltage Vref4, respectively, and output a ninth level signal when the power supply voltage VCC is between the third reference voltage Vref3 and the fourth reference voltage Vref4, and output a tenth level signal when the power supply voltage VCC is not between the third reference voltage Vref3 and the fourth reference voltage Vref4;

[0086] The delay trigger circuit 62 is connected between the second switch circuit 50 and the window comparator circuit 61. The delay trigger circuit 62 is configured to charge upon receiving the ninth level signal and output the seventh level signal when the charging time reaches a preset time length, and to trigger the eighth level signal upon receiving the ninth level signal and charging when the charging time does not reach the preset time length or when receiving the tenth level signal.

[0087] In this embodiment, the window comparison circuit 61 performs a window comparison on the power supply voltage VCC. When the power supply voltage VCC is between the second reference voltage Vref2 and the third reference voltage Vref3 during power failure, the window comparison circuit 61 outputs a tenth level signal. At this time, the delay trigger circuit 62 triggers and outputs an eighth level signal. The second switch circuit 50 is turned off, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. The power management integrated circuit 200 switches to a shutdown state with no operating voltage output. The corresponding source drive circuit and gate drive circuit have no signal output, and the display panel is normally off to avoid display abnormalities or screen flickering.

[0088] When the power supply voltage VCC rebounds to between the third reference voltage Vref3 and the fourth reference voltage Vref4 after power failure, the window comparator circuit 61 outputs a ninth level signal. After receiving the ninth level signal, the delay trigger circuit 62 charges and performs a time judgment on the ninth level signal. When the duration of the ninth level signal does not reach the preset duration, it indicates that the current power supply voltage VCC is in a power failure rebound state. At this time, the delay trigger circuit 62 outputs an eighth level signal, and the second switch circuit 50 is turned off, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. The power management integrated circuit 200 maintains the shutdown state, no working voltage is output, and the corresponding source drive circuit and gate drive circuit have no signal output.

[0089] When the power supply voltage VCC rebounds after power failure or restarts and rises to between the third reference voltage Vref3 and the fourth reference voltage Vref4 and the time reaches the preset duration, it indicates that the current power supply voltage VCC is in a normal restart state, the delay trigger circuit 62 outputs the seventh level signal, the second switch circuit 50 is triggered to turn on, and the power management integrated circuit 200 starts normally, thereby realizing the normal restart operation of the power management integrated circuit 200.

[0090] The window comparison circuit 61 may adopt a corresponding comparator, and the delay trigger circuit 62 may adopt a corresponding capacitor, trigger, etc.

[0091] Example 4

[0092] like Figure 7 As shown, in an optional embodiment, the window comparison circuit 61 includes a third comparator U5, a fourth comparator U6, a first diode D1, a second diode D2 and an inverter U7;

[0093] The inverting input terminal of the third comparator U5 is used to input the fourth reference voltage Vref4, the non-inverting input terminal of the fourth comparator U6 is used to input the third reference voltage Vref3, the non-inverting input terminal of the third comparator U5 and the inverting input terminal of the fourth comparator U6 are used to input the power supply voltage VCC, the output terminal of the third comparator U5 is connected to the anode of the second diode D2, the output terminal of the fourth comparator U6 is connected to the anode of the first diode D1, the cathode of the first diode D1, the cathode of the second diode D2 and the input terminal of the inverter U7 are connected, and the output terminal of the inverter U7 constitutes the output terminal of the window comparator circuit 61.

[0094] The delay trigger circuit 62 includes a fifth resistor R5, a sixth resistor R6, a third diode D3, a second capacitor C2 and a D trigger U8;

[0095] A first end of the fifth resistor R5 is grounded, a second end of the fifth resistor R5, a cathode of the third diode D3, a first end of the sixth resistor R6, and a reset end of the D flip-flop U8 constitute an input end of the delay trigger circuit 62, an anode of the third diode D3, a second end of the sixth resistor R6, a first end of the second capacitor C2, and a clock end of the D flip-flop U8 are connected, a second end of the second capacitor C2 is grounded, a data end and a power end of the D flip-flop U8 are used to input a power supply voltage VCC, and an output end of the D flip-flop U8 constitutes an output end of the delay trigger circuit 62.

[0096] The second switch circuit 50 includes a second electronic switch tube M2 , and a first terminal, a second terminal and a control terminal of the second electronic switch tube M2 constitute an input terminal, an output terminal and a control terminal of the second switch circuit 50 respectively.

[0097] In this embodiment, the third comparator U5 and the fourth comparator U6 perform a window comparison on the power supply voltage VCC. When the power supply voltage VCC is between the second reference voltage Vref2 and the third reference voltage Vref3 during power failure, the fourth comparator U6 outputs a high level, the first diode D1 is turned on, the second diode D2 is turned off, the first diode D1 outputs a high level, and the inverter U7 inverts and outputs a low-level tenth-level signal. At this time, the second capacitor C2 of the delay trigger circuit 62 is discharged through the third diode D3, the second capacitor C2 outputs a low-level eighth-level signal, the D flip-flop U8 is reset, the D flip-flop U8 outputs a low level, the second electronic switch tube M2 is turned off, and the connection between the power supply voltage VCC and the power input terminal Vin of the power management integrated circuit 200 is disconnected. The power management integrated circuit 200 switches to the shutdown state, no working voltage is output, and the corresponding source drive circuit and gate drive circuit have no signal output. The display panel is normally off, avoiding display abnormalities or screen flickering.

[0098] When the power supply voltage VCC rebounds to between the third reference voltage Vref3 and the fourth reference voltage Vref4 after a power failure, the third comparator U5 and the fourth comparator U6 both output a low level, the first diode D1 and the second diode D2 are both turned off, and the inverter U7 outputs a high-level ninth-level signal. The high level charges the second capacitor C2 through the sixth resistor R6, and the voltage of the second capacitor C2 begins to rise. When the duration of the high level does not reach the preset duration and the voltage of the second capacitor C2 does not exceed the threshold voltage Vth of the D-type flip-flop U8, the clock end of the D-type flip-flop U8 does not detect a rising edge, and the D-type flip-flop U8 maintains an output low level. At this time, the second electronic switch tube M2 is turned off, disconnecting the power supply voltage VCC from the power input terminal Vin of the power management integrated circuit 200. The power management integrated circuit 200 remains in the shutdown state, with no operating voltage output, and the corresponding source drive circuit and gate drive circuit have no signal output.

[0099] When the power supply voltage VCC rebounds after power failure or restarts and rises to between the third reference voltage Vref3 and the fourth reference voltage Vref4 and the time reaches the preset duration, it indicates that the current power supply voltage VCC is in a normal restart state, the duration of the high level reaches the preset duration, and when the voltage of the second capacitor C2 exceeds the threshold voltage Vth of the D trigger U8, the clock end of the D trigger U8 detects a rising edge, the D trigger U8 switches to output a high level, the second electronic switch tube M2 is triggered to turn on, and the power management integrated circuit 200 starts normally, thereby realizing the normal restart operation of the power management integrated circuit 200.

[0100] Corresponding to the signal on-off mode of the second electronic switch tube M2, in an optional embodiment, the second electronic switch tube M2 is an NMOS tube.

[0101] Example 5

[0102] The present invention also provides a display device, such as Figure 8 As shown, the display device includes a power management integrated circuit 200 and a voltage control circuit 100. The specific structure of the voltage control circuit 100 is similar to the above-mentioned embodiments. Since the present display device adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, and will not be described in detail here. The voltage control circuit 100 is connected to the power input terminal Vin of the power management integrated circuit 200.

[0103] In this embodiment, the voltage control circuit 100 can detect the power-off voltage. When a voltage rebound occurs during the power-off process, the power of the power management integrated circuit 200 can be effectively kept off to prevent the power management integrated circuit 200 from restarting abnormally, thereby effectively preventing the display panel from having abnormal screen abnormalities or screen flickering problems caused by abnormal power-on, thereby improving the display quality and user experience of the display device.

[0104] The display device may also include a timing controller, a source driver circuit, a gate driver circuit, and a display panel. The power management integrated circuit 200 starts and outputs an operating voltage to the back-end timing controller, source driver circuit, gate driver circuit, and display panel. The source driver circuit is used to output a data signal under the control of the timing controller. The gate driver circuit is used to output a scan signal and scan the display panel line by line under the control of the timing controller. The display panel displays corresponding image information under the drive of the data signal and the scan signal.

[0105] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A voltage control circuit, characterized in that: include: a first switch circuit, wherein an input end of the first switch circuit is used to input a power supply voltage, an output end of the first switch circuit is connected to a power input end of a power management integrated circuit of the display device, and the first switch circuit is triggered to turn on by a first level signal and to turn off by a second level signal; a power-on reset circuit, wherein an input terminal of the power-on reset circuit is used to input a supply voltage, the power-on reset circuit is configured to charge the supply voltage when it is powered on, and output a third level signal when it is charged to a first reference voltage, and output a fourth level signal when it is not charged to the first reference voltage or when the supply voltage is powered down to the first reference voltage, wherein the supply voltage rises to reach a second reference voltage when the power-on reset circuit is charged to the first reference voltage; a comparison circuit, configured to compare the supply voltage with the second reference voltage, and output a fifth level signal when the supply voltage is greater than or equal to the second reference voltage, and output a sixth level signal when the supply voltage is less than the second reference voltage; a switch control circuit, connected to the first switch circuit, the power-on reset circuit, and the comparison circuit, respectively. The switch control circuit is configured to output the first-level signal upon receiving the fourth-level signal or simultaneously receiving the third-level signal and the fifth-level signal during power-on, and to trigger output of the second-level signal upon simultaneously receiving the third-level signal and the sixth-level signal during power-off, until the fourth-level signal is received and the first-level signal is switched to be output.

2. The voltage control circuit according to claim 1, wherein: The power-on reset circuit includes a first resistor, a first capacitor and a first comparator; The first end of the first resistor is used to input the supply voltage, the second end of the first resistor, the first end of the first capacitor and the non-inverting input end of the first comparator are connected, the second end of the first capacitor is grounded, the inverting input end of the first comparator is used to input the first reference voltage, and the output end of the first comparator constitutes the output end of the power-on reset circuit.

3. The voltage control circuit according to claim 1, wherein: The comparison circuit includes a second resistor, a third resistor, a fourth resistor, a voltage regulator tube and a second comparator; The first end of the second resistor and the non-inverting input end of the second comparator are used to input the supply voltage, the second end of the second resistor, the first end of the third resistor, the cathode of the voltage regulator tube and the inverting input end of the second comparator are connected, the second end of the third resistor, the first end of the fourth resistor and the reference voltage end of the voltage regulator tube are connected, the second end of the fourth resistor and the anode of the voltage regulator tube are grounded, and the output end of the second comparator constitutes the output end of the comparison circuit.

4. The voltage control circuit according to claim 1, wherein: The switch control circuit includes a first NAND gate and a second NAND gate; The first input end of the first NAND gate is connected to the output end of the power-on reset circuit, the first input end of the second NAND gate is connected to the output end of the comparison circuit, the output end of the first NAND gate is connected to the second input end of the second NAND gate, and the output end of the second NAND gate is connected to the second input end of the first NAND gate to form the output end of the switch control circuit.

5. The voltage control circuit according to any one of claims 1 to 4, wherein: A load capacitor is further connected between the power input terminal of the power management integrated circuit and the ground; The voltage control circuit further includes: a second switch circuit, wherein an input end of the second switch circuit is used to input a power supply voltage, an output end of the second switch circuit is connected to a power input end of the power management integrated circuit, and the second switch circuit is triggered to be turned on by the seventh level signal and triggered to be turned off by the eighth level signal; A time detection circuit, wherein the input end of the time detection circuit is used to input the supply voltage, the output end of the time detection circuit is connected to the control end of the second switching circuit, and the time detection circuit is used to compare the supply voltage with a third reference voltage and a fourth reference voltage respectively, and output the seventh level signal when the supply voltage is between the third reference voltage and the fourth reference voltage and lasts for a preset time length, otherwise output the eighth level signal, wherein the third reference voltage is greater than the second reference voltage and less than the steady-state voltage of the supply voltage, and the fourth reference voltage is greater than the steady-state voltage of the supply voltage.

6. The voltage control circuit according to claim 5, wherein: The time detection circuit comprises: a window comparator circuit, wherein an input terminal of the window comparator circuit is used to input the supply voltage, the window comparator circuit is used to compare the supply voltage with a third reference voltage and a fourth reference voltage, respectively, and output a ninth level signal when the supply voltage is between the third reference voltage and the fourth reference voltage, and output a tenth level signal when the supply voltage is not between the third reference voltage and the fourth reference voltage; a delay trigger circuit connected between the second switch circuit and the window comparator circuit, the delay trigger circuit being configured to charge upon receiving the ninth level signal and output the seventh level signal when the charging time reaches a preset time length, and to trigger the eighth level signal upon receiving the ninth level signal and charging when the charging time does not reach the preset time length or when receiving the tenth level signal.

7. The voltage control circuit according to claim 6, wherein: The window comparison circuit includes a third comparator, a fourth comparator, a first diode, a second diode and an inverter; The inverting input terminal of the third comparator is used to input the fourth reference voltage, the non-inverting input terminal of the fourth comparator is used to input the third reference voltage, the non-inverting input terminal of the third comparator and the inverting input terminal of the fourth comparator are used to input the supply voltage, the output terminal of the third comparator is connected to the anode of the second diode, the output terminal of the fourth comparator is connected to the anode of the first diode, the cathode of the first diode, the cathode of the second diode and the input terminal of the inverter are connected, and the output terminal of the inverter constitutes the output terminal of the window comparator circuit.

8. The voltage control circuit according to claim 6, wherein: The delay trigger circuit includes a fifth resistor, a sixth resistor, a third diode, a second capacitor and a D trigger; The first end of the fifth resistor is grounded, the second end of the fifth resistor, the cathode of the third diode, the first end of the sixth resistor and the reset end of the D trigger constitute the input end of the delay trigger circuit, the anode of the third diode, the second end of the sixth resistor, the first end of the second capacitor and the clock end of the D trigger are connected, the second end of the second capacitor is grounded, the data end and the power supply end of the D trigger are used to input the power supply voltage, and the output end of the D trigger constitutes the output end of the delay trigger circuit.

9. The voltage control circuit according to claim 5, wherein: The first switch circuit includes a first electronic switch tube, wherein the first end, the second end and the control end of the first electronic switch tube respectively constitute the input end, the output end and the control end of the first switch circuit; The second switch circuit includes a second electronic switch tube, and the first end, the second end and the control end of the second electronic switch tube respectively constitute the input end, the output end and the control end of the second switch circuit.

10. A display device, characterized in that: The device comprises a power management integrated circuit and a voltage control circuit as claimed in any one of claims 1 to 9, wherein the voltage control circuit is connected to a power input terminal of the power management integrated circuit.

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