Power-on reset system, battery management chip and vehicle

Abstract

The embodiment of the invention provides a power-on reset system, a battery management chip and a vehicle, and the system comprises a sampling circuit, the first end of which is connected with a power supply; the first end of the band-gap reference core is connected with the second end of the sampling circuit, and the second end of the band-gap reference core is connected with the power supply; the first end of the comparator module is connected with the third end of the band-gap reference core, the second end of the comparator module is connected with the fourth end of the band-gap reference core, and the third end of the comparator module is connected with a power supply; and the first end of the phase inverter module is connected with the fourth end of the comparator module, the second end of the phase inverter module is connected with the target equipment, and the third end of the phase inverter module is connected with the power supply. According to the method and the device, the technical problem of relatively poor stability of power-on reset of the target equipment in the prior art is solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of device control, and in particular, to a power-on reset system, a battery management chip and a vehicle. BACKGROUND

[0002] In remote device management and automated production lines, remote power-on reset of a target device is a key link to maintain system stability and improve work efficiency. However, the current power-on reset technology for the target device mostly relies on network signals to send instructions to the target device, and in the industrial environment of instruction transmission, there are usually unstable factors such as electromagnetic interference and signal attenuation, which may cause the interruption or delay of instruction transmission when sending instructions through network signals, so that the reset command cannot reach the device in time or accurately, thereby causing reset failure and poor stability in power-on reset of the target device.

[0003] At present, there is no good solution to the above problems. SUMMARY

[0004] Embodiments of the present application provide a power-on reset system, a battery management chip and a vehicle to at least solve the technical problem of poor stability in power-on reset of a target device in the related art.

[0005] According to an aspect of embodiments of the present application, a power-on reset system is provided, comprising: a sampling circuit, a first end of the sampling circuit being connected with a power supply, the sampling circuit being configured to sample a power supply voltage output by the power supply to obtain a sampling voltage; a bandgap reference core, a first end of the bandgap reference core being connected with a second end of the sampling circuit, a second end of the bandgap reference core being connected with the power supply, the bandgap reference core being configured to transmit the sampling voltage and obtain a reference voltage by temperature compensation of the sampling voltage, wherein the reference voltage is a voltage output by the power supply at a zero temperature coefficient; a comparator module, a first end of the comparator module being connected with a third end of the bandgap reference core, a second end of the comparator module being connected with a fourth end of the bandgap reference core, a third end of the comparator module being connected with the power supply, the comparator module being configured to compare the sampling voltage and the reference voltage to obtain a voltage comparison signal; and an inverter module, a first end of the inverter module being connected with a fourth end of the comparator module, a second end of the inverter module being connected with a target device, a third end of the inverter module being connected with the power supply, the inverter module being configured to generate a reset control signal based on the voltage comparison signal, wherein the reset control signal is a signal for indicating whether the target device needs to be reset.

[0006] Furthermore, the bandgap reference core includes: a temperature compensation circuit, the first terminal of which is connected to the second terminal of the sampling circuit, and the second terminal of which is connected to the first terminal of the comparator module. The temperature compensation circuit is used to compensate the sampling voltage for temperature changes when the ambient temperature of the system changes during power-on reset, so as to output a reference voltage; a current mirror circuit, the first terminal of which is connected to the second terminal of the temperature compensation circuit, the second terminal of which is connected to the third terminal of the temperature compensation circuit, the third terminal of which is connected to the power supply, and the fourth terminal of which is connected to the second terminal of the comparator module, for current mirroring of the current flowing into the temperature compensation circuit, so as to output a sampling voltage; and a voltage regulation circuit, the first terminal of which is connected to the fourth terminal of the temperature compensation circuit, the second terminal of which is connected to the fifth terminal of the temperature compensation circuit, and the third terminal of which is grounded, for maintaining the reference voltage with a zero temperature coefficient.

[0007] Furthermore, the temperature compensation circuit includes: a first bipolar transistor, the base of which is connected to a first terminal of the temperature compensation circuit, the collector of which is connected to a third terminal of the temperature compensation circuit, and the emitter of which is connected to a fourth terminal of the temperature compensation circuit; and a second bipolar transistor, the base of which is connected to the base of the first bipolar transistor, the collector of which is connected to a second terminal of the temperature compensation circuit, and the emitter of which is connected to a fifth terminal of the temperature compensation circuit.

[0008] Further, the current mirror circuit includes: a first field-effect transistor, the source of which is connected to the third terminal of the current mirror circuit, the gate of which is connected to the drain of which is connected to the fourth terminal of the current mirror circuit, and the drain of which is connected to the second terminal of the current mirror circuit; a second field-effect transistor, the source of which is connected to the third terminal of the current mirror circuit, the gate of which is connected to the gate of which is connected to the gate of which is connected to the gate of which is connected to the first terminal of the current mirror circuit, and the drain of which is connected to the first terminal of the current mirror circuit; and a third field-effect transistor, the source of which is connected to a power supply, the gate of which is used to receive a first control signal, the drain of which is connected to the gate ...

[0009] Furthermore, the voltage regulation circuit includes: a first resistor, the first end of which is connected to the first end of the voltage regulation circuit, and the second end of which is connected to the second end of the voltage regulation circuit; and a second resistor, the first end of which is connected to the first end of the first resistor, and the second end of which is grounded.

[0010] Further, the comparator module includes: a voltage input circuit, the first terminal of which is connected to the first terminal of the comparator module, the second terminal of which is connected to the second terminal of the comparator module, and the third terminal of which is connected to the third terminal of the comparator module; the voltage input circuit is used to receive the sampled voltage and the reference voltage; and a voltage enhancement circuit, the first terminal of which is connected to the fourth terminal of the voltage input circuit, the second terminal of which is connected to the fifth terminal of the voltage input circuit and the fourth terminal of the comparator module, and the third terminal of which is grounded; the voltage enhancement circuit is used to enhance the sampled voltage and compare the enhanced sampled voltage with the reference voltage to obtain a voltage comparison signal.

[0011] Furthermore, the voltage input circuit includes: a fourth field-effect transistor, the source of which is connected to the third terminal of the voltage input circuit, the gate of which is connected to the second terminal of the voltage input circuit, and the drain of which is connected to the fourth terminal of the voltage input circuit; and a fifth field-effect transistor, the source of which is connected to the third terminal of the voltage input circuit, the gate of which is connected to the first terminal of the voltage input circuit, and the drain of which is connected to the fifth terminal of the voltage input circuit.

[0012] Furthermore, the voltage enhancement circuit includes: a sixth field-effect transistor, the drain of which is connected to a first terminal of the voltage enhancement circuit, and the source of which is grounded; a seventh field-effect transistor, the drain of which is connected to a second terminal of the voltage enhancement circuit, the source of which is grounded, and the gate of which is connected to the gate of the sixth field-effect transistor; and an eighth field-effect transistor, the source of which is grounded, the drain of which is connected to the gate of the seventh field-effect transistor, the gate of which is used to receive a second control signal, and the eighth field-effect transistor is used to control the voltage enhancement circuit to turn on based on the second control signal.

[0013] Further, the sampling circuit includes: a third resistor, the first end of which is connected to the first end of the sampling circuit, and the second end of which is connected to the second end of the sampling circuit; a fourth resistor, the first end of which is connected to the second end of the third resistor; a fifth resistor, the first end of which is connected to the second end of the fourth resistor, and the second end of which is grounded; and a ninth field-effect transistor, the source of which is grounded, the gate of which is used to receive a third control signal, the drain of which is connected to the second end of the fourth resistor, and the ninth field-effect transistor is used to control the connection of the fourth resistor and the fifth resistor or ground.

[0014] Furthermore, the inverter module includes: a signal enhancement inverter, the first terminal of which is connected to the first terminal of the inverter module, and the second terminal of which is connected to the second terminal of the inverter module; the signal enhancement inverter is used to enhance the load-carrying capacity of the voltage comparison signal; a logic flip inverter, the first terminal of which is connected to the third terminal of the signal enhancement inverter, the second terminal of which is connected to the third terminal of the signal enhancement inverter, the third terminal of which is connected to the third terminal of the inverter module, and the fourth terminal of which is grounded; the logic flip inverter is used to logically flip the voltage comparison signal to obtain a logic flip signal; and a Schmitt trigger, connected in series between the second terminal of the logic flip inverter and the third terminal of the signal enhancement inverter, used to separate the reset signal flip point when the power supply voltage rises and falls based on the logic flip signal.

[0015] According to another aspect of the embodiments of this application, a battery management chip is also provided. The battery management chip includes a stored executable program, wherein, when the executable program is running, it sends a control signal to the power-on reset system of any of the above-mentioned embodiments to control the operation of the power-on reset system.

[0016] According to another aspect of the embodiments of this application, a vehicle is also provided, including: a battery management chip storing an executable program; and a processor for running the program, wherein the program sends a control signal to the power-on reset system of any one of the above-mentioned embodiments during runtime to control the operation of the power-on reset system.

[0017] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein, when the executable program is running, it controls the device where the computer-readable storage medium is located to execute the system of various embodiments of this application.

[0018] According to another aspect of the embodiments of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the systems of various embodiments of this application.

[0019] According to another aspect of the embodiments of this application, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the systems of various embodiments of this application.

[0020] According to another aspect of the embodiments of this application, a computer program is also provided, which, when executed by a processor, implements the systems of the various embodiments of this application.

[0021] In this embodiment, a power-on reset system including a sampling circuit, a bandgap reference core, a comparator module, and an inverter module is adopted. By using the bandgap reference core to transmit and compensate the sampled voltage acquired by the sampling circuit, a reference voltage of the power supply under the critical temperature coefficient is obtained. A reset control signal is generated based on the comparison result between the sampled voltage and the reference voltage. This can effectively determine whether the power supply voltage has reached the stable voltage required for the start-up or normal operation of the target device, thereby ensuring the accuracy and stability of the output reset control signal, and thus solving the technical problem of poor stability of power-on reset of the target device in related technologies. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 This is a structural block diagram of a power-on reset system according to an embodiment of this application;

[0024] Figure 2 This is a circuit diagram of a power-on reset system according to an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, systems, products, or devices.

[0027] According to an embodiment of this application, a system embodiment of a power-on reset system is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0028] This embodiment provides a power-on reset system. Figure 1 This is a structural block diagram of a power-on reset system according to an embodiment of this application, such as... Figure 1 As shown, the power-on reset system 100 may include:

[0029] The sampling circuit 102 has its first terminal connected to the power supply 104. The sampling circuit 102 is used to sample the power supply voltage output by the power supply 104 to obtain the sampled voltage.

[0030] The bandgap reference core 106 has its first end connected to the second end of the sampling circuit 102 and its second end connected to the power supply 104. It is used to transmit the sampling voltage and to obtain the reference voltage by performing temperature compensation on the sampling voltage. The reference voltage is the voltage output by the power supply 104 at zero temperature coefficient.

[0031] The comparator module 108 has its first terminal connected to the third terminal of the bandgap reference core 106, its second terminal connected to the fourth terminal of the bandgap reference core 106, and its third terminal connected to the power supply 104. The comparator module 108 is used to compare the sampled voltage and the reference voltage to obtain a voltage comparison signal.

[0032] Inverter module 110 has its first terminal connected to the fourth terminal of comparator module 108, its second terminal connected to target device 112, and its third terminal connected to power supply 104. Inverter module 110 is used to generate a reset control signal based on a voltage comparison signal. The reset control signal is used to indicate whether the target device 112 needs to be reset.

[0033] In one optional embodiment, considering that when the power-on reset system is used to reset the connected target device under normal circumstances, the power supply voltage usually needs to reach a preset voltage threshold and be maintained for a period of time. However, in actual applications, the power supply may experience voltage drift due to instantaneous fluctuations in power supply voltage, noise interference, or temperature changes. This results in the output power supply voltage not only being unstable, for example, fluctuating around the preset voltage threshold, but even being lower than the preset voltage threshold for a long time. This leads to uncertainties such as false triggering or delayed triggering of the reset signal, affecting the stability of resetting the target device, and even causing functional abnormalities or safety risks to the target device.

[0034] Therefore, to improve the stability of power-on reset of the target device and ensure the accuracy and reliability of the power-on reset signal sent by the power-on reset system, a temperature-compensated reference voltage source can be configured in the power-on reset system. Correspondingly, the power-on reset system can use the reference voltage source to compensate for the impact of temperature changes on the transmitted voltage, outputting a reference voltage with zero temperature coefficient. This ensures that the reference voltage remains constant regardless of changes in the ambient temperature of the power-on reset system, thereby improving the robustness of the power-on reset system to temperature changes. Furthermore, considering that the power supply voltage often does not immediately reach a stable state during transmission but undergoes a gradual increase until it stabilizes, the power supply voltage may fluctuate due to factors such as current demand, circuit characteristics, and inherent instability of the power supply itself. However, the reference voltage output by the reference voltage source is not affected by these factors, and since the reference voltage is obtained by compensating for the sampled voltage, it can be considered as the voltage threshold that needs to be reached when power-on resetting the target device under normal circumstances. Therefore, the power-on reset system can use the reference voltage output by the reference voltage source as the voltage threshold for determining whether the target device needs to be reset, to measure and judge whether the power supply voltage state meets the requirements for system reset.

[0035] Furthermore, in order to ensure that the target device is powered on and reset under safe and stable power supply voltage conditions, and to avoid false resets or reset failures caused by instantaneous voltage fluctuations or power supply noise, a corresponding voltage comparator can be configured in the power-on reset system. The voltage comparator compares the sampled voltage of the power supply in the power-on reset system with the reference voltage to determine whether a reset operation is required for the target device. This effectively filters out abnormal situations such as instantaneous fluctuations and noise interference in the power supply voltage, ensuring that the power-on reset system only triggers the power-on reset signal when the power supply voltage is truly stable and exceeds the reference voltage, thereby avoiding false operations.

[0036] To further ensure the logical correctness of the reset signal and prevent premature release of the reset signal before the power supply voltage is fully stable, thus avoiding incomplete initialization of the target device, an inverter module can be added to the power-on reset system. Correspondingly, the power-on reset system can use the inverter to logically invert the voltage comparison result output by the voltage comparator. This ensures that when the power supply voltage is lower than the reference voltage, the power-on reset system can output a high-level reset signal. When the power supply voltage is higher than the reference voltage and remains stable for a period of time, the inverter module will output a low level, releasing the reset signal and allowing the target device to start and operate normally. This delayed logic control mechanism effectively avoids the impact of power supply voltage fluctuations on the reset process, ensuring that the target device resets or maintains normal operation at the appropriate time, thereby improving the stability and safety of the entire system.

[0037] Based on this, the power-on reset system can include at least the aforementioned sampling circuit 102, bandgap reference core 106, comparator module 108, and inverter module 110. The sampling circuit samples the power supply to obtain a sampled voltage, and the bandgap reference core is used as a reference voltage source to output a reference voltage with zero temperature coefficient based on the sampled voltage. Then, the comparator module is used as a voltage comparator to compare the sampled voltage with the reference voltage to obtain a voltage comparison result. Finally, the inverter module is used as an inverter to perform logical inversion and conversion on the voltage comparison result, thereby generating a reset control signal to determine whether the target device needs to be reset.

[0038] Correspondingly, the first terminal of the sampling circuit 102 can be connected to the power supply 104 to sample the power supply voltage output by the power supply and obtain the sampled voltage.

[0039] The first terminal of the bandgap reference core 106 is then connected to the second terminal of the sampling circuit 102, and the second terminal of the bandgap reference core 106 is connected to the power supply 104. This allows the bandgap reference core to transmit the sampling voltage and to obtain a reference voltage by temperature compensation of the sampling voltage. For example, a temperature sensor can be built into the bandgap reference core to monitor the internal temperature of the power-on reset system and changes in the ambient temperature in real time, generating a corresponding temperature change signal. This temperature change signal is then used to construct compensation parameters to counteract the effect of temperature changes on the sampling voltage. Alternatively, the bandgap reference core can also acquire information about power supply voltage fluctuations to construct compensation parameters based on parameters of internal components, such as resistance values, voltage gain, or feedback ratios, ensuring that the compensation effect on the sampling circuit is maximized.

[0040] Then, the first terminal of comparator module 108 is connected to the third terminal of bandgap reference core 106, the second terminal of comparator module 108 is connected to the fourth terminal of bandgap reference core 106, and the third terminal of comparator module 108 is connected to power supply 104 to compare the sampled voltage transmitted by the bandgap reference core with the output reference voltage to obtain the voltage comparison result, and simultaneously output the voltage comparison signal corresponding to the voltage comparison result. For example, when the sampled voltage is lower than the reference voltage, it indicates that the power supply voltage has not yet reached the stable voltage required for the target device to start or maintain normal operation, and the voltage comparator can output a high-level signal at this time; when the sampled voltage is greater than or equal to the reference voltage, it indicates that the power supply voltage has stabilized and reached the stable voltage required for the target device to start or maintain normal operation, and the voltage comparator can output a low-level signal at this time.

[0041] Finally, the first terminal of inverter module 110 is connected to the fourth terminal of comparator module 108, the second terminal of inverter module 110 is connected to target device 112, and the third terminal of inverter module 110 is connected to power supply 104. This allows the inverter module to logically invert the voltage comparison signal and generate a reset control signal. For example, if the comparator module outputs a high-level signal, the inverter module can convert the high-level signal to a low-level signal to obtain the aforementioned reset control signal, thus preventing erroneous operation. If the comparator module outputs a low-level signal, the inverter module can convert the low-level signal to a high-level signal to obtain the aforementioned reset control signal, thereby controlling the target device to reset.

[0042] In this embodiment, a power-on reset system including a sampling circuit, a bandgap reference core, a comparator module, and an inverter module is adopted. By using the bandgap reference core to transmit and compensate the sampled voltage acquired by the sampling circuit, a reference voltage of the power supply under the critical temperature coefficient is obtained. A reset control signal is generated based on the comparison result between the sampled voltage and the reference voltage. This can effectively determine whether the power supply voltage has reached the stable voltage required for the start-up or normal operation of the target device, thereby ensuring the accuracy and stability of the output reset control signal, and thus solving the technical problem of poor stability of power-on reset of the target device in related technologies.

[0043] Furthermore, the bandgap reference core 106 includes: a temperature compensation circuit, the first terminal of which is connected to the second terminal of the sampling circuit, and the second terminal of which is connected to the first terminal of the comparator module 108. The temperature compensation circuit is used to perform temperature compensation on the sampling voltage when the ambient temperature of the environment where the power-on reset system is located changes, so as to output a reference voltage; a current mirror circuit, the first terminal of which is connected to the second terminal of the temperature compensation circuit, the second terminal of which is connected to the third terminal of the temperature compensation circuit, the third terminal of which is connected to the power supply 104, and the fourth terminal of which is connected to the second terminal of the comparator module 108, for current mirroring of the current flowing into the temperature compensation circuit, so as to output a sampling voltage; and a voltage regulation circuit, the first terminal of which is connected to the fourth terminal of the temperature compensation circuit, the second terminal of which is connected to the fifth terminal of the temperature compensation circuit, and the third terminal of which is grounded. The voltage regulation circuit is used to maintain the reference voltage with zero temperature coefficient.

[0044] In one alternative embodiment, in order to stably transmit the sampling voltage and compensate the sampling voltage to obtain the reference voltage, the bandgap reference core may include at least the temperature compensation circuit, the current mirror circuit, and the voltage regulation circuit described above.

[0045] Specifically, the first terminal of the temperature compensation circuit can be connected to the second terminal of the sampling circuit, and the second terminal of the temperature compensation circuit can be connected to the first terminal of the comparator module 108. This allows the temperature compensation circuit to transmit the sampling voltage and compensate for changes in the ambient temperature of the system after power-on reset, outputting a reference voltage.

[0046] Connect the first terminal of the current mirror circuit to the second terminal of the temperature compensation circuit, connect the second terminal of the current mirror circuit to the third terminal of the temperature compensation circuit, connect the third terminal of the current mirror circuit to the power supply, and connect the fourth terminal of the current mirror circuit to the second terminal of the comparator module. This allows the current mirror circuit to mirror the current flowing into the temperature compensation circuit, thereby stably outputting the sampling voltage.

[0047] Connect the first terminal of the voltage regulation circuit to the fourth terminal of the temperature compensation circuit, connect the second terminal of the voltage regulation circuit to the fifth terminal of the temperature compensation circuit, and ground the third terminal of the voltage regulation circuit. This is to maintain the reference voltage with zero temperature coefficient using the voltage regulation circuit.

[0048] Furthermore, the temperature compensation circuit includes: a first bipolar transistor, the base of which is connected to a first terminal of the temperature compensation circuit, the collector of which is connected to a third terminal of the temperature compensation circuit, and the emitter of which is connected to a fourth terminal of the temperature compensation circuit; and a second bipolar transistor, the base of which is connected to the base of the first bipolar transistor, the collector of which is connected to a second terminal of the temperature compensation circuit, and the emitter of which is connected to a fifth terminal of the temperature compensation circuit.

[0049] In one alternative embodiment, in order to improve the effect of compensating the sampling voltage, the temperature compensation circuit may include at least a first bipolar transistor and a second bipolar transistor.

[0050] Specifically, the base of the first bipolar transistor (BPT) can be connected to the first terminal of the temperature compensation circuit, the collector of the first BPT can be connected to the third terminal of the temperature compensation circuit, and the emitter of the first BPT can be connected to the fourth terminal of the temperature compensation circuit. The power-on reset system can utilize the first BPT to stabilize the current transmitted in the bandgap reference core, thereby ensuring the accuracy of voltage compensation under different power supply conditions. The sampled voltage received at the base of the first BPT is output through the collector, ensuring the accuracy of the sampled voltage received by the subsequent comparator module.

[0051] The base of the second bipolar transistor is connected to the base of the first bipolar transistor. The collector of the second bipolar transistor is connected to the second terminal of the temperature compensation circuit, and the emitter of the second bipolar transistor is connected to the fifth terminal of the temperature compensation circuit. The power-on reset system utilizes the voltage difference Vbe between the second and first bipolar transistors, amplified by a voltage regulation circuit, to convert it into a compensation voltage. This compensation voltage is then used to compensate for the sampled voltage, offsetting voltage deviations caused by temperature changes and ensuring the stability of the output reference voltage.

[0052] Further, the current mirror circuit includes: a first field-effect transistor, the source of which is connected to the third terminal of the current mirror circuit, the gate of which is connected to the drain of which is connected to the fourth terminal of the current mirror circuit, and the drain of which is connected to the second terminal of the current mirror circuit; a second field-effect transistor, the source of which is connected to the third terminal of the current mirror circuit, the gate of which is connected to the gate of which is connected to the gate of which is connected to the first terminal of the current mirror circuit, and the drain of which is connected to the first terminal of the current mirror circuit; and a third field-effect transistor, the source of which is connected to the power supply 104, the gate of which is used to receive a first control signal, the drain of which is connected to the gate ...

[0053] In one alternative embodiment, in order to stably output the sampling voltage, the current mirror circuit may include a first field-effect transistor, a second field-effect transistor, and a third field-effect transistor.

[0054] Specifically, the source of the first field-effect transistor (FET) can be connected to the power supply, the gate of the first FET can be connected to the drain of the first FET, and the drain of the first FET can be connected to the collector of the first bipolar transistor (BPT). The power-on reset system can utilize the first FET as a preliminary current source and regulator to ensure a stable current supply to subsequent circuits, thereby stably outputting the sampling point voltage.

[0055] The source of the second field-effect transistor (FET) can be connected to the power supply, the gate of the second FET can be connected to the gate of the first FET, and the drain of the second FET can be connected to the collector of the second bipolar transistor (BPT). The power-on reset system utilizes the current mirror effect formed by the second and first FETs to replicate the stable current from the first FET and transfer it to the first BPT, which requires a constant current source, thereby achieving precise temperature compensation and voltage amplification. The source of the third FET can be connected to the power supply, the gate of the third FET can receive a first control signal, and the drain of the third FET can be connected to the gate of the first FET. The power-on reset system uses the third FET to control the current mirror circuit to conduct according to the first control signal, thereby achieving current replication.

[0056] Furthermore, the voltage regulation circuit includes: a first resistor, the first end of which is connected to the first end of the voltage regulation circuit, and the second end of which is connected to the second end of the voltage regulation circuit; and a second resistor, the first end of which is connected to the first end of the first resistor, and the second end of which is grounded.

[0057] In one alternative embodiment, in order to effectively compensate the sampled voltage, the voltage regulation circuit may include a first resistor and a second resistor.

[0058] The system can connect the first terminal of the first resistor to the first terminal of the voltage regulation circuit, the second terminal of the first resistor to the second terminal of the voltage regulation circuit, the first terminal of the second resistor to the first terminal of the first resistor, and ground the second terminal of the second resistor. The power-on reset system can utilize the first and second resistors to compensate for potential changes at the emitters of the first and second bipolar transistors. For example, when the temperature rises, the Vbe voltage difference between the two transistors increases, leading to an increase in the current flowing through the first resistor and a corresponding increase in the voltage drop across it. To maintain a constant emitter potential, the second resistor can absorb more current, thus maintaining the stability of the entire voltage divider network and ensuring that the compensation voltage is synchronized with temperature changes, offsetting the effect of temperature on the sampling voltage. When the temperature decreases, the Vbe voltage difference between the two transistors decreases, reducing the current flowing through the first resistor and a corresponding decrease in the voltage drop across it. To maintain a constant emitter potential, the second resistor can absorb less current, again ensuring that the compensation voltage effectively offsets the voltage deviation caused by temperature changes.

[0059] Further, the comparator module 108 includes: a voltage input circuit, the first terminal of which is connected to the first terminal of the comparator module 108, the second terminal of which is connected to the second terminal of the comparator module 108, and the third terminal of which is connected to the third terminal of the comparator module 108; the voltage input circuit is used to receive a sampled voltage and a reference voltage; and a voltage enhancement circuit, the first terminal of which is connected to the fourth terminal of the voltage input circuit, the second terminal of which is connected to the fifth terminal of the voltage input circuit and the fourth terminal of the comparator module 108, and the third terminal of which is grounded; the voltage enhancement circuit is used to enhance the sampled voltage and compare the enhanced sampled voltage with the reference voltage to obtain a voltage comparison signal.

[0060] In one optional embodiment, in order to accurately output the voltage comparison signal, the comparator module may include at least a voltage input circuit and a voltage enhancement circuit.

[0061] Specifically, the first terminal of the voltage input circuit can be connected to the first terminal of the comparator module 108, the second terminal of the voltage input circuit can be connected to the second terminal of the comparator module 108, and the third terminal of the voltage input circuit can be connected to the third terminal of the comparator module 108, so as to receive the sampled voltage and the reference voltage using the voltage input circuit. The first terminal of the voltage enhancement circuit is connected to the fourth terminal of the voltage input circuit, the second terminal of the voltage enhancement circuit is connected to the fifth terminal of the voltage input circuit and the fourth terminal of the comparator module 108, and the third terminal of the voltage enhancement circuit is grounded, so as to enhance the sampled voltage. The enhanced sampled voltage is then compared with the reference voltage to obtain a voltage comparison signal.

[0062] Furthermore, the voltage input circuit includes: a fourth field-effect transistor, the source of which is connected to the third terminal of the voltage input circuit, the gate of which is connected to the second terminal of the voltage input circuit, and the drain of which is connected to the fourth terminal of the voltage input circuit; and a fifth field-effect transistor, the source of which is connected to the third terminal of the voltage input circuit, the gate of which is connected to the first terminal of the voltage input circuit, and the drain of which is connected to the fifth terminal of the voltage input circuit.

[0063] In one optional embodiment, to ensure the accuracy of the received sampling voltage and reference voltage, the voltage input circuit may include a fourth field-effect transistor and a fifth field-effect transistor.

[0064] Specifically, the source of the fourth field-effect transistor can be connected to the third terminal of the voltage input circuit, the gate of the fourth field-effect transistor can be connected to the second terminal of the voltage input circuit, and the drain of the fourth field-effect transistor can be connected to the fourth terminal of the voltage input circuit. The voltage input circuit can receive the sampling voltage through the fourth field-effect transistor.

[0065] Then connect the source of the fifth field-effect transistor to the third terminal of the voltage input circuit, connect the gate of the fifth field-effect transistor to the first terminal of the voltage input circuit, and connect the drain of the fifth field-effect transistor to the fifth terminal of the voltage input circuit. The voltage input circuit can receive the reference voltage through the fourth field-effect transistor.

[0066] Furthermore, the voltage enhancement circuit includes: a sixth field-effect transistor, the drain of which is connected to a first terminal of the voltage enhancement circuit, and the source of which is grounded; a seventh field-effect transistor, the drain of which is connected to a second terminal of the voltage enhancement circuit, the source of which is grounded, and the gate of which is connected to the gate of the sixth field-effect transistor; and an eighth field-effect transistor, the source of which is grounded, the drain of which is connected to the gate of the seventh field-effect transistor, the gate of which is used to receive a second control signal, and the eighth field-effect transistor is used to control the voltage enhancement circuit to turn on based on the second control signal.

[0067] In one alternative embodiment, to improve the accuracy of the output voltage comparison signal, the voltage enhancement circuit may include a sixth field-effect transistor, a seventh field-effect transistor, and an eighth field-effect transistor.

[0068] Specifically, the drain of the sixth field-effect transistor can be connected to the first terminal of the voltage enhancement circuit, while the source of the sixth field-effect transistor is grounded. The power-on reset system can use the sixth field-effect transistor to ensure that the gain of the comparator module's output signal is adjustable, thereby improving the accuracy and reliability of the output signal.

[0069] Connect the drain of the seventh field-effect transistor to the second terminal of the voltage boosting circuit, ground the source of the seventh field-effect transistor, and connect the gate of the seventh field-effect transistor to the gate of the sixth field-effect transistor. The power-on reset system can enhance the output signal of the entire voltage boosting circuit through the seventh field-effect transistor, improving the system's response speed and sensitivity to voltage changes.

[0070] The drain of the eighth field-effect transistor is connected to the gate of the seventh field-effect transistor, and the gate of the eighth field-effect transistor is used to receive the second control signal. The power-on reset system can control the voltage enhancement circuit to turn on according to the second control signal through the eighth field-effect transistor.

[0071] Further, the sampling circuit includes: a third resistor, the first end of which is connected to the first end of the sampling circuit, and the second end of which is connected to the second end of the sampling circuit; a fourth resistor, the first end of which is connected to the second end of the third resistor; a fifth resistor, the first end of which is connected to the second end of the fourth resistor, and the second end of which is grounded; and a ninth field-effect transistor, the source of which is grounded, the gate of which is used to receive a third control signal, the drain of which is connected to the second end of the fourth resistor, and the ninth field-effect transistor is used to control the connection of the fourth resistor and the fifth resistor or ground.

[0072] In one alternative embodiment, in order to stably sample the power supply voltage, the sampling circuit may include at least: a third resistor, a fourth resistor, a fifth resistor, and a ninth field-effect transistor.

[0073] Specifically, the first terminal of the third resistor can be connected to the first terminal of the sampling circuit, and the second terminal of the third resistor can be connected to the second terminal of the sampling circuit. The first terminal of the fourth resistor can be connected to the second terminal of the third resistor. The first terminal of the fifth resistor can be connected to the second terminal of the fourth resistor, and the second terminal of the fifth resistor can be grounded. The source of the ninth field-effect transistor is grounded, the gate of the ninth field-effect transistor is used to receive the third control signal, the drain of the ninth field-effect transistor is connected to the second terminal of the fourth resistor, and the ninth field-effect transistor is used to control the OR connection between the fourth resistor and the fifth resistor and ground.

[0074] The power-on reset system can gradually reduce and stabilize the power supply voltage to a level suitable for the operation of the sampling circuit through the third, fourth and fifth resistors. It can also use the ninth field-effect transistor as a switch for the sampling circuit, and control the sampling circuit to sample the power supply according to the third control signal.

[0075] Further, the inverter module 110 includes: a signal enhancement inverter, the first terminal of which is connected to the first terminal of the inverter module 110, the second terminal of which is connected to the second terminal of the inverter module 110, the signal enhancement inverter being used to enhance the load-carrying capacity of the voltage comparison signal; a logic flip inverter, the first terminal of which is connected to the third terminal of the signal enhancement inverter, the second terminal of which is connected to the third terminal of the signal enhancement inverter, the third terminal of which is connected to the third terminal of the inverter module 110, and the fourth terminal of which is grounded, the logic flip inverter being used to logically flip the voltage comparison signal to obtain a logic flip signal; and a Schmitt trigger, connected in series between the second terminal of the logic flip inverter and the third terminal of the signal enhancement inverter, used to separate the reset signal flip point when the power supply voltage rises and falls based on the logic flip signal.

[0076] In one optional embodiment, to improve the accuracy of the output reset control signal, the inverter module may include: a signal enhancement inverter, a logic flip inverter, and a Schmitt trigger.

[0077] Specifically, the first terminal of the signal enhancement inverter can be connected to the first terminal of the inverter module 110, and the second terminal of the signal enhancement inverter can be connected to the second terminal of the inverter module 110. The first terminal of the logic flip inverter can be connected to the third terminal of the signal enhancement inverter, the second terminal of the logic flip inverter can be connected to the third terminal of the signal enhancement inverter, the third terminal of the logic flip inverter can be connected to the third terminal of the inverter module 110, and the fourth terminal of the logic flip inverter can be grounded. A circuit is connected between the second terminal of the logic flip inverter and the third terminal of the signal enhancement inverter.

[0078] The power-on reset system can use a signal enhancement inverter to enhance the load-carrying capacity of the voltage comparison signal, use a logic flip inverter to perform a logic flip signal on the voltage comparison signal, and use a Schmitt trigger to separate the reset signal flip point when the power supply voltage rises and falls based on the logic flip signal.

[0079] For ease of understanding, Figure 2 This is a circuit diagram of a power-on reset system according to an embodiment of this application, wherein V dd The resistors represent the power supply voltage, R1 represents the third resistor, R2 represents the fourth resistor, R3 represents the first resistor, R4 represents the second resistor, R5 represents the fifth resistor, N0 represents the sixth field-effect transistor, N1 represents the seventh field-effect transistor, N3 represents the ninth field-effect transistor, N4 represents the eighth field-effect transistor, Q0 represents the first bipolar transistor, Q1 represents the second bipolar transistor, P0 represents the first field-effect transistor, P1 represents the second field-effect transistor, P2 represents the fourth field-effect transistor, P3 represents the fifth field-effect transistor, N2 and P4 form a logic flip-flop inverter, P5 represents the third field-effect transistor, VBP represents the sampling point voltage, VBG represents the reference voltage, I0-I4 represent signal boosting inverters, SMITT represents a Schmitt trigger, PORN represents the feedback signal (third control signal), and POR represents the reset control signal.

[0080] like Figure 2As shown, when the power supply voltage Vdd gradually rises over time, after voltage division by a resistor, it can provide a bias current IB for two transistors Q1 and Q2. Since a transistor can be regarded as a current-controlled current source and IC = IB, the currents in the two transistor branches gradually build up, causing VBP to gradually rise. VBP is the sampled voltage obtained after sampling the power supply voltage. At this time, P0 and P1 operate in the saturation region, forming a current mirror to make the two currents equal. The VBG generated by the bandgap reference core is adjusted by R1, R2, R3, and R4 to make VBG a voltage with zero temperature coefficient. Then, it is compared with the sampled voltage VBP by a comparator composed of P2, P3, N0, and N1. When VBP > VBG, the output is at a low level, and after inversion by an inverter, the POR signal is obtained. When the power supply voltage gradually drops over time, similarly, VBG remains unchanged. When VBP < VBG, the output signal of the comparator flips to a high level, and after inversion by an inverter, a low-level signal is obtained to control the entire circuit to stop working, thus achieving a normal flip reset during power-on and power-off.

[0081] In a conventional power-on reset circuit, generally, the reset signal is irreversible after being given, and the voltage threshold points during power-on and power-off are the same. This will cause mis-triggering of this module if the power supply voltage is unstable during the overall chip operation, resulting in mis-triggering and making the entire circuit inoperable. Therefore, in order to enhance the stability of the power-on reset circuit module and improve the anti-disturbance ability against power supply voltage fluctuations, the threshold voltage points for upward and downward flipping of the overvoltage signal need to be separated. Thus, a Schmitt trigger is connected to the output terminal of an inverter composed of P4 and N2 at the end. And in order to improve the overall stability and adaptability, the signal delayed by the Schmitt trigger is inverted and set as PORN. PORN is a negative feedback signal that controls the turn-off of N3 to control whether R5 is connected to the sampling circuit, thereby changing the sampled voltage value and further controlling the stable output of the comparator. Also, a capacitor is connected at the input position of the Schmitt trigger to filter out the voltage signal noise. The signal is enhanced in its stability and control ability after passing through multiple inverters. In addition, a digital control signal EN is added to control the startup of the bandgap reference core and the comparator, further increasing the stability of the entire circuit.

[0082] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. And the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or reject.

[0083] Embodiments of this application also provide a battery management chip, which includes a stored executable program, wherein, when the executable program runs, it sends a control signal to the power-on reset system of any of the above-mentioned methods to control the operation of the power-on reset system.

[0084] According to another aspect of the embodiments of this application, a vehicle is also provided, including: a battery management chip storing an executable program; and a processor for running the program, wherein the program sends a control signal to the power-on reset system of any one of the above-mentioned embodiments during runtime to control the operation of the power-on reset system.

[0085] Embodiments of this application also provide a computer-readable storage medium including a stored executable program, wherein, when the executable program is running, it controls the device where the computer-readable storage medium is located to execute the systems of various embodiments of this application.

[0086] Embodiments of this application also provide a computer program product, including a computer program that, when executed by a processor, implements the systems of various embodiments of this application.

[0087] Embodiments of this application also provide a computer program product, including a non-volatile computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the systems of various embodiments of this application.

[0088] Embodiments of this application also provide a computer program that, when executed by a processor, implements the systems described in the various embodiments of this application.

[0089] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.

[0091] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0093] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the system of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0094] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A power-on reset system, characterized in that, include: A sampling circuit, wherein the first terminal of the sampling circuit is connected to a power supply, and the sampling circuit is used to sample the power supply voltage output by the power supply to obtain a sampled voltage; A bandgap reference core, wherein a first end of the bandgap reference core is connected to a second end of the sampling circuit, and the second end of the bandgap reference core is connected to the power supply, for transmitting the sampling voltage and obtaining a reference voltage by temperature compensation of the sampling voltage, wherein the reference voltage is the voltage output by the power supply at zero temperature coefficient; A comparator module, wherein the first end of the comparator module is connected to the third end of the bandgap reference core, the second end of the comparator module is connected to the fourth end of the bandgap reference core, and the third end of the comparator module is connected to the power supply. The comparator module is used to compare the sampled voltage and the reference voltage to obtain a voltage comparison signal. An inverter module is provided, wherein a first terminal of the inverter module is connected to a fourth terminal of the comparator module, a second terminal of the inverter module is connected to a target device, and a third terminal of the inverter module is connected to a power supply. The inverter module is used to generate a reset control signal based on the voltage comparison signal, wherein the reset control signal is used to characterize whether the target device needs to be reset.

2. The system according to claim 1, characterized in that, The bandgap reference core includes: A temperature compensation circuit is provided, wherein the first terminal of the temperature compensation circuit is connected to the second terminal of the sampling circuit, and the second terminal of the temperature compensation circuit is connected to the first terminal of the comparator module. The temperature compensation circuit is used to perform temperature compensation on the sampling voltage when the ambient temperature of the environment in which the power-on reset system is located changes, so as to output the reference voltage. A current mirror circuit is provided, wherein the first terminal of the current mirror circuit is connected to the second terminal of the temperature compensation circuit, the second terminal of the current mirror circuit is connected to the third terminal of the temperature compensation circuit, the third terminal of the current mirror circuit is connected to the power supply, and the fourth terminal of the current mirror circuit is connected to the second terminal of the comparator module, for performing current mirroring on the current flowing into the temperature compensation circuit to output the sampling voltage; A voltage regulation circuit is provided, wherein the first terminal of the voltage regulation circuit is connected to the fourth terminal of the temperature compensation circuit, the second terminal of the voltage regulation circuit is connected to the fifth terminal of the temperature compensation circuit, and the third terminal of the voltage regulation circuit is grounded. The voltage regulation circuit is used to maintain the reference voltage with zero temperature coefficient.

3. The system according to claim 2, characterized in that, The temperature compensation circuit includes: A first bipolar transistor, wherein the base of the first bipolar transistor is connected to the first terminal of the temperature compensation circuit, the collector of the first bipolar transistor is connected to the third terminal of the temperature compensation circuit, and the emitter of the first bipolar transistor is connected to the fourth terminal of the temperature compensation circuit. The second bipolar transistor has its base connected to the base of the first bipolar transistor, its collector connected to the second terminal of the temperature compensation circuit, and its emitter connected to the fifth terminal of the temperature compensation circuit.

4. The system according to claim 2, characterized in that, The current mirror circuit includes: The first field-effect transistor has its source connected to the third terminal of the current mirror circuit, its gate connected to its drain and the fourth terminal of the current mirror circuit, and its drain connected to the second terminal of the current mirror circuit. The second field-effect transistor has its source connected to the third terminal of the current mirror circuit, its gate connected to the gate of the first field-effect transistor, and its drain connected to the first terminal of the current mirror circuit. The third field-effect transistor has its source connected to the power supply, its gate used to receive a first control signal, and its drain connected to the gates of the first and second field-effect transistors. The third field-effect transistor is used to control the current mirror circuit to conduct based on the first control signal. The voltage regulation circuit includes: A first resistor, the first end of which is connected to the first end of the voltage regulation circuit, and the second end of which is connected to the second end of the voltage regulation circuit; The second resistor has its first end connected to the first end of the first resistor, and its second end grounded.

5. The system according to claim 1, characterized in that, The comparator module includes: A voltage input circuit, wherein a first terminal of the voltage input circuit is connected to a first terminal of the comparator module, a second terminal of the voltage input circuit is connected to a second terminal of the comparator module, and a third terminal of the voltage input circuit is connected to a third terminal of the comparator module, the voltage input circuit being used to receive the sampled voltage and the reference voltage; A voltage enhancement circuit is provided, wherein a first terminal of the voltage enhancement circuit is connected to a fourth terminal of the voltage input circuit, a second terminal of the voltage enhancement circuit is connected to a fifth terminal of the voltage input circuit and a fourth terminal of the comparator module, and a third terminal of the voltage enhancement circuit is grounded. The voltage enhancement circuit is used to enhance the sampled voltage and compare the enhanced sampled voltage with the reference voltage to obtain the voltage comparison signal.

6. The system according to claim 5, characterized in that, The voltage input circuit includes: A fourth field-effect transistor, wherein the source of the fourth field-effect transistor is connected to the third terminal of the voltage input circuit, the gate of the fourth field-effect transistor is connected to the second terminal of the voltage input circuit, and the drain of the fourth field-effect transistor is connected to the fourth terminal of the voltage input circuit; A fifth field-effect transistor, wherein the source of the fifth field-effect transistor is connected to the third terminal of the voltage input circuit, the gate of the fifth field-effect transistor is connected to the first terminal of the voltage input circuit, and the drain of the fifth field-effect transistor is connected to the fifth terminal of the voltage input circuit; The voltage enhancement circuit includes: A sixth field-effect transistor, wherein the drain of the sixth field-effect transistor is connected to the first terminal of the voltage enhancement circuit, and the source of the sixth field-effect transistor is grounded; A seventh field-effect transistor, wherein the drain of the seventh field-effect transistor is connected to the second terminal of the voltage enhancement circuit, the source of the seventh field-effect transistor is grounded, and the gate of the seventh field-effect transistor is connected to the gate of the sixth field-effect transistor. The eighth field-effect transistor has its source grounded and its drain connected to the gate of the seventh field-effect transistor. The gate of the eighth field-effect transistor is used to receive a second control signal, and the eighth field-effect transistor is used to control the voltage enhancement circuit to turn on based on the second control signal.

7. The system according to claim 1, characterized in that, The sampling circuit includes: A third resistor, wherein the first end of the third resistor is connected to the first end of the sampling circuit, and the second end of the third resistor is connected to the second end of the sampling circuit; A fourth resistor, the first end of which is connected to the second end of the third resistor; The fifth resistor has its first end connected to the second end of the fourth resistor, and its second end is grounded. The ninth field-effect transistor has its source grounded, its gate used to receive a third control signal, its drain connected to the second terminal of the fourth resistor, and its use to control the fourth resistor to be connected to the fifth resistor or ground.

8. The system according to claim 1, characterized in that, The inverter module includes: A signal enhancement inverter, wherein a first terminal of the signal enhancement inverter is connected to a first terminal of the inverter module, and a second terminal of the signal enhancement inverter is connected to a second terminal of the inverter module, and the signal enhancement inverter is used to enhance the load-carrying capacity of the voltage comparison signal; A logic flip inverter is provided, wherein the first terminal of the logic flip inverter is connected to the third terminal of the signal enhancement inverter, the second terminal of the logic flip inverter is connected to the third terminal of the signal enhancement inverter, the third terminal of the logic flip inverter is connected to the third terminal of the inverter module, and the fourth terminal of the logic flip inverter is grounded. The logic flip inverter is used to logically flip the voltage comparison signal to obtain a logic flip signal. A Schmitt trigger, connected in series between the second terminal of the logic flip-flop inverter and the third terminal of the signal boost inverter, is used to separate the reset signal flip-point when the power supply voltage rises and falls based on the logic flip-flop signal.

9. A battery management chip, characterized in that, include: The power-on reset system according to any one of claims 1 to 8 sends a control signal to control the operation of the power-on reset system.

10. A vehicle, characterized in that, include: The battery management chip stores an executable program. A processor for running the program, wherein the program, when running, sends a control signal to the power-on reset system according to any one of claims 1 to 8 to control the operation of the power-on reset system.

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