Circuit devices and real-time clock devices

Abstract

A circuit arrangement and a real-time clock arrangement are provided, capable of appropriately performing a power-on reset action during initial startup. The circuit arrangement includes a first power line supplied with a first power supply voltage, a second power line supplied with a second power supply voltage, a third power line, a power supply circuit, a specified circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When the first and second power-on reset circuits are at reset release levels, the reset control circuit causes a third power-on reset signal output to at least a portion of the specified circuit to become a reset release level.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit device and a real-time clock device, etc. BACKGROUND

[0002] There is known a power-on reset circuit which, when a power supply is turned on to a circuit device or when a power supply voltage drops, makes an internal state of the circuit device an initial state by generating an internal reset signal. In Patent Literature 1, there is disclosed a technology in which, in a circuit device having a switching circuit which switches between a main power supply and a backup power supply, there is provided a power-on reset circuit which is capable of being connected to either one of the main power supply and the backup power supply.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2014-017965

[0004] In each circuit of the circuit device, a period until a constant voltage is supplied is preferably set to a reset state, and thus a minimum drive voltage is set. The circuit device described in Patent Literature 1, for example, sets the voltage of the main power supply to be lower in a case where it is to operate with low power consumption, and thus it can not be possible to properly cause the power-on reset circuit to operate. SUMMARY

[0005] One embodiment of the present disclosure relates to a circuit device including: a first power supply line to which a first power supply voltage is supplied; a second power supply line to which a second power supply voltage is supplied; a third power supply line; a power supply circuit connected to the first power supply line and the second power supply line, selecting the first power supply voltage or the second power supply voltage, and outputting a third power supply voltage based on the selected power supply voltage to the third power supply line; a prescribed circuit operating by the third power supply voltage; a first power-on reset circuit connected to the first power supply line, outputting a first power-on reset signal based on the first power supply voltage; a second power-on reset circuit connected to the third power supply line, outputting a second power-on reset signal based on the third power supply voltage; and a reset control circuit making a third power-on reset signal output to at least a part of the prescribed circuit a reset release level when the first power-on reset signal and the second power-on reset signal are a reset release level.

[0006] Further, another embodiment of the present disclosure relates to a real-time clock device including the above-described circuit device, and a vibrator, the circuit device including: a regulator generating the third power supply voltage from a power supply voltage output by selecting the first power supply voltage; and an oscillation circuit generating a clock signal by oscillating the vibrator, the prescribed circuit including a timing circuit which performs a timing process based on the clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a graph showing a comparative example.

[0008] Figure 2 is a waveform chart showing a motion example in the comparative example.

[0009] Figure 3 is a graph showing a structure example of the circuit device of the present embodiment.

[0010] Figure 4 is a graph showing a detailed structure example of the reset control circuit.

[0011] Figure 5 is a graph showing a detailed structure example of the power supply circuit.

[0012] Figure 6 is a graph showing a detailed structure example of the switch circuit.

[0013] Figure 7 is a graph showing a structure example of the first power-on reset circuit.

[0014] Figure 8 is a graph showing a structure example of the second power-on reset circuit.

[0015] Figure 9 is a waveform chart showing a motion example in the circuit device of the present embodiment.

[0016] Figure 10 is a waveform chart showing another motion example in the comparative example.

[0017] Figure 11 is a waveform chart showing another motion example in the circuit device of the present embodiment.

[0018] Explanation of Reference Numerals

[0019] 10: transducer; 100: circuit device; 110: power supply circuit; 111: switching circuit; 112, 113: P-type transistor; 114: switching control circuit; 115: 1st detection circuit; 116: 2nd detection circuit; 120: processing circuit; 121: timing circuit; 122: temperature compensation circuit; 124: arithmetic circuit; 125: logic circuit; 127: memory; 129: reset control circuit; 130: 2nd power-on reset circuit; 131: 2nd bias circuit; 132: 2nd reference voltage generation circuit; 133: 2nd comparator; 135: connection control circuit; 136: CR circuit; 139: power-on reset circuit; 150: oscillation circuit; 151: regulator VOSC_REG; 152: regulator VDDA_REG; 153: regulator VLOG_REG; 160: temperature detection circuit; 170: interface circuit; 180: memory; 190: 1st power-on reset circuit; 191: 1st bias circuit; 192: 1st reference voltage generation circuit; 193: 1st comparator; 195: current mirror circuit; 196: 1st current source; 197: 2nd current source; 199: 3rd current source; 200: real time clock device; N1: 1st input node; N2: 2nd input node; NVREF1: 1st reference voltage node; NVREF2: 2nd reference voltage node; SWPU: switch; TC11: 1st transistor; TC12: 2nd transistor; VDD: 1st power supply voltage; VBAT: 2nd power supply voltage; VLOG: 3rd power supply voltage; VOUT: 4th power supply voltage; VREF1: 1st reference voltage; VREF2: 2nd reference voltage; VSS: ground voltage; PORQ: power-on reset signal; PORQ1: 1st power-on reset signal; PORQ2: 2nd power-on reset signal; PORQ3: 3rd power-on reset signal. DETAILED DESCRIPTION

[0020] Hereinafter, a preferred embodiment of the present disclosure will be described in detail. In addition, the present embodiment described below does not unduly limit the content recited in the claims, and the structures described in the present embodiment are not necessarily all essential components.

[0021] 1. Basic structure

[0022] Figure 1 As the basic structure, a figure is explained which is a comparative example of applying the method of Patent Literature 1 to the circuit device 100 of the present embodiment. The circuit device 100 includes a 1st power supply line supplied with a 1st power supply voltage VDD, a 2nd power supply line supplied with a 2nd power supply voltage VBAT, a 3rd power supply line, a power supply circuit 110, and a prescribed circuit 120. The 3rd power supply line is a power supply line which supplies a 3rd power supply voltage VLOG through the power supply circuit 110. For the following use of the 3rd power supply voltage VLOG, the 3rd power supply line is also referred to as a VLOG line. Figure 3The circuit device 100 of the embodiment described above is the same. In addition, the configuration of the circuit device 100 is not limited to the above configuration, and various modifications such as omitting a part of the configuration elements or adding other configuration elements can be implemented. For example, the circuit device 100 can include a power-on reset circuit 139 in addition to the above configuration. In addition, the circuit device 100 can include an interface circuit 170. In addition, the circuit device 100 can include terminals TVDD, TVBAT, TVOUT, TIF, XI, and XQ. In addition, the terminals such as TVDD, TVBAT, TVOUT, TIF, XI, and XQ in the embodiment are, for example, pads in the circuit device 100.

[0023] The power supply circuit 110 monitors the first power supply voltage VDD and the second power supply voltage VBAT, and performs a selection operation of the first power supply voltage VDD and the second power supply voltage VBAT based on the monitoring result, and outputs the selected voltage as the fourth power supply voltage VOUT. In addition, a power supply line to which the fourth power supply voltage VOUT is supplied is referred to as a fourth power supply line. In other words, the power supply circuit 110 is connected to the first power supply line and the second power supply line, and selects the first power supply voltage VDD or the second power supply voltage VBAT. The selection operation of the first power supply voltage VDD and the second power supply voltage VBAT can be implemented by using a transistor that functions as a switch, and the details will be described later. In addition, the connection in the embodiment is an electrical connection. The electrical connection refers to a connection that can transmit an electrical signal, and is a connection that can transmit information by an electrical signal. The electrical connection can also be a connection via an active element or the like. A stabilization capacitor that is not shown and that is used to stabilize the fourth power supply voltage VOUT is connected to the terminal TVOUT. The power supply circuit 110 outputs a power supply voltage VOSC to the oscillation circuit 150 described later, a power supply voltage VDDA to the temperature detection circuit 160 described later, and a third power supply voltage VLOG to the specification circuit 120 based on the fourth power supply voltage VOUT. In other words, the power supply circuit 110 outputs the third power supply voltage VLOG based on the selected power supply voltage to the third power supply line. In addition, the power supply circuit 110 also outputs the third power supply voltage VLOG to the power-on reset circuit 139.

[0024] The specification circuit 120 performs an operation by the third power supply voltage VLOG input from the power supply circuit 110 described above. In other words, the specification circuit 120 performs an operation by the third power supply voltage VLOG. The specification circuit 120 includes, for example, a logic circuit 125 and a memory 127, and the details will be described later. In addition, the specification circuit 120 communicates with the processor via the interface circuit 170. The interface circuit 170 is connected to the processor via the terminal TIF. In addition, the interface circuit 170 is connected to the terminal XI and the terminal XQ. In addition, the interface circuit 170 is connected to the terminal TVDD and the terminal TVBAT. Figure 1The TIF terminal is omitted as one, but in reality, multiple TIF terminals are provided for interface use. A power-on reset signal PORQ is input from the power-on reset circuit 139 to the designated circuit 120, and then the designated circuit 120 performs reset and reset release through the power-on reset signal PORQ.

[0025] Furthermore, lower operating voltage limits are specified for logic circuit 125 and memory 127. It is assumed that the lower operating voltage limit VOLM of memory 127 is higher than the lower operating voltage VOLL of logic circuit 125. Using this as a premise, [further details are needed]. Figure 2 The waveform diagram illustrates the operation during initial startup in a comparative example where the method of Patent Document 1 is applied to the circuit device 100. Furthermore, Figure 2 The vertical axis length does not represent the specific voltage magnitude, and the horizontal axis length does not represent the specific time duration. (For details to be discussed later...) Figure 9 , Figure 10 , Figure 11 The same applies.

[0026] After the first power supply voltage VDD is applied to the circuit device 100, the fourth power supply voltage VOUT and the third power supply voltage VLOG rise in tandem with the power supply voltage VDD. Furthermore, at the timing shown in A1, the logic level of the power-on reset signal PORQ changes from low to high. That is, at the timing shown in A1, the power-on reset circuit 139 outputs the power-on reset signal PORQ indicating that the reset has been released. Here, in this embodiment, it is assumed that when the power-on reset signal is low, the circuit to which the power-on reset signal is input is in a reset state, and when the power-on reset signal is high, the reset state of the circuit to which the power-on reset signal is input is released.

[0027] In addition, Figure 2 Although the diagram is omitted, the premise is that the logic level of the timing power-on reset signal PORQ before the timing shown in A1 is determined to be low. The explanation regarding the timing at which the power-on reset signal PORQ is determined to be low is omitted. For the following discussion... Figure 9 to Figure 11 The same applies to the first power-on reset signal PORQ1 and the second power-on reset signal PORQ2 shown.

[0028] exist Figure 2In this case, since the operation of the circuit device 100 is premised on the first power supply voltage VDD being set high enough as described above, the voltage of the third power supply voltage VLOG is higher than either of the lower limit voltage VOLL of the logic circuit 125 and the lower limit voltage VOLM of the memory 127 at the timing Al, and no adverse situation occurs. In other words, as long as the first power supply voltage VDD can be set high enough, the power-on reset circuit 139 supplied with the third power supply voltage VLOG can be caused to operate properly. Here, the power-on reset circuit operating properly means that the power-on reset circuit properly outputs a power-on reset signal indicating release of reset when the power supply voltage becomes the assumed voltage level.

[0029] However, when the circuit device 100 is caused to operate, a situation can occur in which the first power supply voltage VDD cannot be set high. Therefore, there is a possibility that the power-on reset circuit 139 supplied with the third power supply voltage VLOG cannot be caused to operate properly. The situation in which the first power supply voltage VDD cannot be set high includes a situation in which a system including the circuit device 100 is intended to be used with low power consumption, and a situation in which the circuit device 100 is initially started using the second power supply voltage VBAT, for example, and details will be described later. Figure 9 In addition, the system here includes a processor of a host device which is the real-time clock device 200 described later, and the processor operates by the first power supply voltage VDD.

[0030] Therefore, as described in detail later in Figure 3 the embodiment, the circuit device 100 of the present embodiment further includes a first power-on reset circuit 190, a second power-on reset circuit 130, and a reset control circuit 129. The first power-on reset circuit 190 is connected to the first power supply line and outputs a first power-on reset signal PORQl based on the first power supply voltage VDD. The second power-on reset circuit 130 is connected to the third power supply line and outputs a second power-on reset signal PORQ2 based on the third power supply voltage VLOG. When the first power-on reset signal PORQl and the second power-on reset signal PORQ2 become a reset release level, the reset control circuit 129 causes a third power-on reset signal PORQ3 output to at least a part of the circuits of the prescribed circuit 120 to become a reset release level.

[0031] Thus, even in a situation in which the first power supply voltage VDD from the main power supply cannot be set high, or a situation in which the circuit device 100 is initially started using a battery, the power-on reset operation can be performed properly.

[0032] In addition, the circuit device 100 of the present embodiment can also be a circuit device of a real-time clock device 200 including the resonator 10, the oscillation circuit 150, and the time measuring circuit 121. In other words, the real-time clock device 200 of the present embodiment includes the circuit device 100 and the resonator 10. The circuit device 100 includes, as a regulator, the VLOG_REG 153 that generates a third power supply voltage VLOG from a power supply voltage output by selecting the first power supply voltage VDD, and the oscillation circuit 150 that generates a clock signal by causing the resonator 10 to oscillate, and the time measuring circuit 121 included in the circuit 120 performs a time measuring process based on the clock signal. In addition, the VLOG_REG 153 as a regulator is described later in Figure 5

[0033] The oscillation circuit 150 causes the resonator 10 to oscillate. For example, the oscillation circuit 150 is electrically connected to the terminal XI and the terminal XQ, and generates an oscillation signal by causing the resonator 10 to oscillate. For example, the oscillation circuit 150 drives the resonator 10 via a signal line connected to the terminal XI and the terminal XQ, and causes the resonator 10 to oscillate. For example, the oscillation circuit 150 includes a drive circuit for oscillation or the like provided between the terminal XI and the terminal XQ. For example, the oscillation circuit 150 can be implemented by a transistor such as a bipolar transistor and an active element such as a capacitor and a resistor that implement the drive circuit. As the oscillation circuit 150, various types of oscillation circuits such as a Pierce type, a Colpitts type, an inverter type, or a Hartley type can be used. In addition, the oscillation circuit 150 can include a variable capacitance circuit not shown, and can adjust the oscillation frequency by capacitance adjustment of the variable capacitance circuit.

[0034] The time measuring circuit 121 performs a time measuring process based on the clock signal generated by the oscillation circuit 150, and generates time information. The time measuring circuit 121 has a counter that performs a counting operation by the clock signal, and outputs data of a count value of the counter as the time information. The time information is information indicating the current time of the system, and for example, after the real-time clock device 200 is started and initialized, the current time or the like time information can be written from the processor via the interface circuit 170, and the current time or the like time information can be read out to the processor.

[0035] ​The vibrator 10 generates mechanical vibrations by an electric signal. The vibrator 10 can be implemented by, for example, a vibrating piece such as a quartz vibrating piece. The vibrator 10 can be implemented by, for example, a quartz vibrating piece that performs thickness shear vibration by an AT-cut or an SC-cut, or the like. The vibrator 10 is, for example, a vibrator built in a temperature-compensated quartz oscillator (TCXO) that does not have a temperature-controlled bath, but can be a vibrator built in an oven-controlled crystal oscillator (OCXO) that has a temperature-controlled bath. In addition, the vibrator 10 of the present embodiment can be implemented by various vibrating pieces other than a thickness shear vibration type, a piezoelectric vibrating piece formed of a material other than quartz, or the like. As the vibrator 10, for example, a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator formed using a silicon substrate as a silicon vibrator, or the like can be used.

[0036] Thus, the circuit device 100 of the present embodiment can be applied to the real-time clock device 200.

[0037] In addition, the real-time clock device 200 of the present embodiment can further include a temperature detection circuit 160 and a temperature compensation circuit 122. Specifically, as shown in Figure 1 is implemented by including the temperature detection circuit 160 in the circuit device 100 and including the temperature compensation circuit 122 in the prescribed circuit 120.

[0038] The temperature compensation circuit 122 outputs temperature compensation data for keeping the oscillation frequency of the oscillation circuit 150 constant regardless of temperature, based on temperature detection data output from the temperature detection circuit 160. The temperature compensation circuit 122 extracts temperature compensation data corresponding to temperature from a lookup table in which the temperature characteristics of the oscillation frequency are tabulated, or substitutes temperature into a polynomial function that approximates the temperature characteristics of the oscillation frequency, thereby outputting the temperature compensation data. In addition, the lookup table can be stored in the memory 127, for example.

[0039] The temperature detection circuit 160 includes a temperature sensor and an A / D conversion circuit, and operates with a power supply voltage VDDA. The temperature sensor outputs a temperature detection voltage that depends on temperature, using the temperature dependence of the forward voltage in a diode. The A / D conversion circuit A / D-converts the temperature detection voltage and outputs temperature detection data.

[0040] Thus, even if the vibrator 10 has temperature dependence, temperature compensation can be performed, and thus the real-time clock device 200 can be made to operate more appropriately.

[0041] 2. Method of the present embodiment

[0042] Next, the details of the circuit device 100 of the present embodiment will be described. Figure 3 is a diagram illustrating a configuration example of the circuit device 100 of the present embodiment. The circuit device 100 of the present embodiment includes a first power supply line supplied with a first power supply voltage VDD, a second power supply line supplied with a second power supply voltage VBAT, a third power supply line, a power supply circuit 110, and a prescribed circuit 120. In addition, the power supply circuit 110 is connected to the first power supply line and the second power supply line, selects the first power supply voltage VDD or the second power supply voltage VBAT, and outputs a third power supply voltage VLOG based on the selected power supply voltage to the third power supply line. In addition, the prescribed circuit 120 operates by the third power supply voltage VLOG. These parts are the same as the aforementioned comparative example.

[0043] In addition, the circuit device 100 of the present embodiment further includes a first power-on reset circuit 190 and a second power-on reset circuit 130. The details will be described later in Figure 7 , the first power-on reset circuit 190 outputs a first power-on reset signal PORQ1 based on the first power supply voltage VDD, a first reference voltage VREF1, and the like. In other words, the first power-on reset circuit 190 is connected to the first power supply line and outputs the first power-on reset signal PORQ1 based on the first power supply voltage VDD. In addition, the details will be described later in Figure 8 , the second power-on reset circuit 130 outputs a second power-on reset signal PORQ2 based on a second reference voltage VREF2, the third power supply voltage VLOG, and the like. In other words, the second power-on reset circuit 130 is connected to the third power supply line and outputs the second power-on reset signal PORQ2 based on the third power supply voltage VLOG.

[0044] In addition, the circuit device 100 of the present embodiment further includes a reset control circuit 129. Specifically, this can be realized by causing the prescribed circuit 120 to include the reset control circuit 129. The details will be described later in Figure 4A specific circuit configuration example of the reset control circuit 129 will be described. The first power-on reset signal PORQ1 output from the first power-on reset circuit 190 and the second power-on reset signal PORQ2 output from the second power-on reset circuit 130 are input to the reset control circuit 129. Also, in a case where both the first power-on reset signal PORQ1 and the second power-on reset signal PORQ2 are signals at a reset release level, the reset control circuit 129 outputs the third power-on reset signal PORQ3 to at least a part of the prescribed circuits 120. The reset release level is, for example, a high level. In other words, when the first power-on reset signal PORQ1 and the second power-on reset signal PORQ2 are at the reset release level, the reset control circuit 129 causes the third power-on reset signal PORQ3 output to at least a part of the prescribed circuits 120 to be at the reset release level. Thereby, in a prescribed condition, it is possible to perform the reset release to the part of the circuits after the first power-on reset signal PORQ1 from the first power-on reset circuit 190 reaches the reset release level, and thus it is possible to appropriately perform the power-on reset operation. The prescribed condition is, as described above, a condition in which the circuit device 100 wants to use the system with low power consumption, a condition in which the circuit device 100 is initially started using the second power supply voltage VBAT.

[0045] Next, the logic circuit 125 and the memory 127 will be described in detail. As described above, the logic circuit 125 and the logic circuit 125 of the memory 127 are included in the prescribed circuits 120. The logic circuit 125 performs control of each part of the circuit device 100. For example, the logic circuit 125 causes the memory 127 to store the aforementioned temperature compensation data, and controls the temperature compensation circuit 122 based on the temperature compensation data. In other words, the prescribed circuits 120 include the memory 127 and the logic circuit 125 that performs processing based on data from the memory 127.

[0046] In addition, the prescribed circuits 120 can control the power supply circuit 110 by performing the reset release. Therefore, at the time of initial start, the switch circuit 111 described later remains off.

[0047] The memory 127 stores data required for the circuit device 100. The required data is, for example, the aforementioned temperature compensation data and the like. The memory 127 can be realized by, for example, a nonvolatile memory. The nonvolatile memory is, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory, or the like. The EEPROM can be realized by, for example, a floating gate type memory cell or the like. The flash memory can be realized by, for example, a MONOS (Metal Oxide Semiconductor) memory cell or the like.

[0048] like Figure 3 As shown, the third power-on reset signal PORQ3 is input to the memory 127 from the reset control circuit 129 described above. In other words, the third power-on reset signal PORQ3 is input to the memory 127. That is, the aforementioned part of the circuit is, for example, the memory 127. Therefore, if it is desired to delay the startup of the memory 127 during initial startup, since the third power-on reset signal PORQ3 can be input to perform a reset release on the memory 127 for the first time, the power-on reset operation can be performed appropriately. In addition, the situation where it is desired to delay the startup of the memory 127 during initial startup is, for example, when the lower operating limit voltage of the memory 127 is high, but it may also be other situations. Furthermore, the aforementioned part of the circuit is not limited to the memory 127 and may be other circuits.

[0049] Furthermore, similar to the aforementioned comparative example, the logic circuit 125 operates via the third power supply voltage VLOG, but requires a voltage higher than the first operating lower limit voltage VOLL for operation. Similarly, the memory 127 operates via the third power supply voltage VLOG, but requires a voltage higher than the second operating lower limit voltage VOLM. Moreover, the second operating lower limit voltage VOLM is a higher specification than the aforementioned first operating lower limit voltage VOLL. In other words, the first operating lower limit voltage VOLL, which is the operating lower limit voltage of the logic circuit 125, is lower than the second operating lower limit voltage VOLM, which is the operating lower limit voltage of the memory 127.

[0050] In addition, such as Figure 3 As shown, logic circuit 125 performs reset and reset release based on the second power-on reset signal PORQ2 output from the second power-on reset circuit 130. In other words, the second power-on reset signal PORQ2 is input to logic circuit 125. Thus, logic circuit 125 with a low operating lower limit voltage can perform reset release based on the second power-on reset signal PORQ2, and then perform reset release on memory 127 with a high operating lower limit voltage, thereby enabling appropriate power-on reset operation.

[0051] Next, use Figure 4A detailed structural example of the reset control circuit 129 will be described. The reset control circuit 129 includes an AND circuit 302, a NAND circuit 304, an RS-type trigger circuit 306, and an OR circuit 310. The first power-on reset signal PORQ1 from the first power-on reset circuit 190, after being voltage-adjusted via a level shifter 308, is input to one input terminal of the OR circuit 310. The third power-on reset signal PORQ3 (described later) is input to the other input terminal of the OR circuit 310. The second power-on reset signal PORQ2 from the second power-on reset circuit 130 and the output signal of the aforementioned OR circuit 310 are input to the AND circuit 302. The second power-on reset signal PORQ2 from the second power-on reset circuit 130, the output signal of the OR circuit 310, and the output signal of the AND circuit 302 are input to the NAND circuit 304. The second power-on reset signal PORQ2 from the second power-on reset circuit 130 is input to the reset terminal of the RS-type trigger circuit 306, and the output signal of the NAND circuit 304 is input to the set terminal of the RS-type trigger circuit 306.

[0052] When the second power-on reset signal from the second power-on reset circuit 130 is low, the RS-type trigger circuit 306 enters a reset state, and the third power-on reset signal PORQ3 output by the RS-type trigger circuit 306 becomes a reset level, i.e., low. Furthermore, when the first power-on reset signal PORQ1 from the first power-on reset circuit 190 is high and the second power-on reset signal PORQ2 from the second power-on reset circuit 130 is high, the output signal of the NAND circuit 304 becomes low. Therefore, the RS-type trigger circuit 306 enters a set state, and the third power-on reset signal PORQ3 output by the RS-type trigger circuit becomes a reset release level, i.e., high. Thus, the memory 127, which has been reset by the input third power-on reset signal PORQ3, is released from reset.

[0053] Furthermore, when the third power-on reset signal PORQ3 goes high, the output signal of the OR circuit 310 is fixed at a high level, and consequently, the output signal of the AND circuit 302 is also fixed at a high level. Consequently, the output signal of the NAND circuit 304 is fixed at a low level, maintaining the set state of the RS-type trigger circuit 306. Therefore, even after the third power-on reset signal PORQ3 goes high, for example, if the first power supply voltage VDD drops, causing the first power-on reset signal PORQ1 to go low, the third power-on reset signal PORQ3 will still be maintained at a high level.

[0054] Next, use Figure 5A detailed structural example of the power supply circuit 110 will be described below. The power supply circuit 110 includes a switching circuit 111, P-type transistors 112 and 113, a switching control circuit 114, a first detection circuit 115, a second detection circuit 116, a VOSC_REG 151 as a regulator, a VDDA_REG 152 as a regulator, and a VLOG_REG 153 as a regulator. Furthermore, details regarding the switching circuit 111 will be provided in... Figure 6 This will be discussed later.

[0055] For example, a first power supply voltage VDD is supplied to terminal TVDD from the power supply of an external system. In other words, the first power supply voltage VDD is an external power supply voltage input from the outside. Furthermore, the external system may be, for example, a system including the aforementioned real-time clock device 200, but may also be other systems. The first detection circuit 115 detects whether the first power supply voltage VDD of node NVDD, which is a power supply voltage node, is lower than a first detection voltage, and outputs the result as a first detection signal DET1 to the switch control circuit 114. The first detection circuit 115 includes a resistor divider circuit that divides the first power supply voltage VDD, and a comparator that compares the divided voltage with the first detection voltage. The second detection circuit 116 detects whether the second power supply voltage VBAT of node NVBAT, which is a battery voltage node, is lower than a second detection voltage, and outputs the result as a second detection signal DET2 to the switch control circuit 114.

[0056] The battery is connected to terminal TVBAT, from which the second power supply voltage VBAT is supplied. In other words, the second power supply voltage VBAT is the battery power voltage input from the battery. The battery can be a secondary battery or a primary battery, serving as a backup power source for the system. That is, when the first power supply voltage VDD is not supplied and the system's processor is not operating, the system operates using the second power supply voltage VBAT. The second detection circuit 116 includes a resistor divider circuit that divides the second power supply voltage VBAT, and a comparator that compares the divided voltage with the second detection voltage. The first and second detection voltages are generated, for example, by a voltage generation circuit (not shown).

[0057] By configuring the first power supply voltage VDD and the second power supply voltage VBAT in this way, even if the voltage of the first power supply voltage VDD drops, the third power supply voltage VLOG can be output based on the second power supply voltage VBAT, and the power-on reset operation of the circuit device 100 can be performed appropriately.

[0058] The switch control circuit 114 controls the switch circuit 111 and P-type transistors 112 and 113 to be turned on or off based on the first detection signal DET1 and the second detection signal DET2. That is, the P-type transistors 112 and 113 function as switches. One of the source and drain terminals of the P-type transistor 112 is connected to node NA, and the other terminal and back gate are connected to node NVOUT. One of the source and drain terminals of the P-type transistor 113 is connected to node NA, and the other terminal and back gate are connected to node NVBAT. In addition, the diodes represented by dashed lines in the P-type transistors 112 and 113 are parasitic diodes generated between one of the source and drain terminals and the back gate. Furthermore, during initial operation, the switch circuit 111 and P-type transistor 112 are off, and P-type transistor 113 is on, receiving power from the first power supply voltage VDD or the second power supply voltage VBAT.

[0059] Next, use Figure 6 A detailed structural example of the switching circuit 111 will be described. The switching circuit 111 includes a P-type transistor 320 and a parasitic diode 322 (shown by dashed lines). One of the source and drain terminals of the switching circuit 111 is connected to node NVDD, and the other is connected to node NVOUT. Node NVOUT is the node on the fourth power supply line described in the comparative example. In other words, the circuit arrangement of this embodiment includes a fourth power supply line supplied based on a selected power supply voltage, namely the fourth power supply voltage VOUT. Furthermore, as... Figure 6 As shown, the switching circuit 111 is configured between node NVOUT on the first power line and the fourth power line, which are supplied with the first power supply voltage VDD. In other words, the power supply circuit 110 includes the switching circuit 111 disposed between the first power line and the fourth power line.

[0060] In addition, such as Figure 6 As shown, the parasitic diode 322 is forward-biased from the first power line to the fourth power line. In other words, the switching circuit 111 includes a diode 322 that is forward-biased from the first power line to the fourth power line. Therefore, regardless of whether the switching circuit is on or off, power can be continuously supplied to the specified circuit 120, etc., by allowing current to flow from the first power line side to the fourth power line, and appropriate power-on reset operations can be performed. Furthermore, this allows the circuit device 100 to be applied to systems including the real-time clock device 200, etc.

[0061] return Figure 5The regulators VOSC_REG 151, VDDA_REG 152, and VLOG_REG 153 will be described below. The power supply circuit 110 includes VOSC_REG 151, VDDA_REG 152, and VLOG_REG 153. VOSC_REG 151 generates a power supply voltage VOSC by adjusting the fourth power supply voltage VOUT and outputs this voltage to the oscillation circuit 150. VDDA_REG 152 generates a power supply voltage VDDA by adjusting the fourth power supply voltage VOUT and outputs this voltage to the temperature detection circuit 160. VLOG_REG 153, acting as a regulator, generates a third power supply voltage VLOG by adjusting the fourth power supply voltage VOUT. Furthermore, as described above, node NVOUT is connected to one side of the switching circuit 111, and the other side of the switching circuit 111 is connected to the first power supply line supplying the first power supply voltage VDD. Furthermore, VLOG_REG 153 outputs the third power supply voltage VLOG to the designated circuit 120. In other words, one end of the switching circuit 111 is connected to the first power supply line, and the power supply circuit 110 includes VLOG_REG 153, which is a regulator whose input node is connected to the other end of the switching circuit 111 and outputs the third power supply voltage VLOG from the output node. VOSC_REG 151, VDDA_REG 152, and VLOG_REG 153, as regulators, can be implemented, for example, by a linear regulator composed of operational amplifiers and resistors.

[0062] Thus, by configuring VLOG_REG 153 as a regulator, it is possible to generate a third power supply voltage VLOG based on the first power supply voltage VDD at a desired voltage, and to perform an appropriate power-on reset operation.

[0063] return Figure 6Continuing with the description of switch circuit 111, the gate of switch circuit 111 receives the output signal of NAND circuit 324. Additionally, a first detection signal DET1 is input to one input terminal of NAND circuit 324, and the output signal of OR circuit 326 is input to the other input terminal. The first detection signal DET1 is initially powered on by the first power supply voltage VDD, and outputs a high level when a power supply voltage higher than the first detection voltage is detected. Furthermore, a first power-on reset signal PORQ1 is input to one input terminal of OR circuit 326, and a third power-on reset signal PORQ3 is input to the other input terminal. Thus, when the first power-on reset signal PORQ1 becomes high, switch circuit 111 changes from off to on via the high level of the NAND corresponding to the first detection signal DET1. In other words, when the first power-on reset signal PORQ1 becomes a reset release level, switch circuit 111 changes from off to on. As a result, the fourth power supply voltage VOUT rises to be equal to the first power supply voltage VDD, and therefore the third power supply voltage VLOG can also rise. Therefore, after supplying a voltage higher than the lower operating limit voltage of each circuit in the specified circuit 120, the reset release of the specified circuit 120 can be performed, thus enabling an appropriate power-on reset operation. Specific examples of this operation will be described later.

[0064] Next, use Figure 7 The first power-on reset circuit 190 will be described. The first power-on reset circuit 190 includes a first bias circuit 191, a first reference voltage generation circuit 192, and a first comparator 193.

[0065] A fourth power supply voltage VOUT is supplied to the first bias circuit 191. The first bias circuit 191 generates a bias voltage VNA1 based on the fourth power supply voltage VOUT and outputs the bias voltage VNA1 to the first comparator 193. The first bias circuit 191 includes P-type transistors TA11 and TA12, depletion-type N-type transistors TA13 and TA14. Furthermore, transistors not referred to as depletion-type are enhancement-type. Figure 8 The same applies.

[0066] The sources of P-type transistors TA11 and TA12 are connected to the power supply voltage node NVOUT, which supplies the fourth power supply voltage VOUT. The drain of P-type transistor TA11 is connected to the gates of P-type transistors TA11 and TA12, the drain of N-type transistor TA13, and the bias node NVRP1. The source and gate of N-type transistor TA13 are connected to the ground node NVSS, which supplies the ground voltage VSS. The drain of P-type transistor TA12 is connected to the drain and gate of N-type transistor TA14, and the bias node NVNA1. The source of N-type transistor TA14 is connected to the ground node NVSS. Furthermore, the ground voltage VSS here can be a power supply voltage lower than the fourth power supply voltage VOUT and the first power supply voltage VDD. Additionally, in... Figure 7 In the diagram, the labels for ground voltage VSS and ground node NVSS only represent one location, while other locations are omitted. Figure 8 The same applies.

[0067] A bias voltage VCP1 is generated by allowing the leakage current of N-type transistor TA13 to flow through P-type transistor TA11. The leakage current of N-type transistor TA13 is mirrored to P-type transistor TA12, and the leakage current of P-type transistor TA12 flows through N-type transistor TA14, thereby generating a bias voltage VNA1. The first bias circuit 191 outputs the bias voltage VNA1 from the bias node NVNA1 to the first comparator 193.

[0068] A first power supply voltage VDD is supplied to the first reference voltage generation circuit 192. The first reference voltage generation circuit 192 generates a first reference voltage VREF1 based on the first power supply voltage VDD and outputs the first reference voltage VREF1 to the first comparator 193. The first reference voltage generation circuit 192 includes a P-type transistor TB11, resistors R1, R2, and R3. The first reference voltage generation circuit 192 divides the first power supply voltage VDD using the combined resistance of resistors R1 and R2 and resistor R3, and uses the divided voltage as the first reference voltage VREF1, outputting it from the first reference voltage node NDF1 to the second input node N2 (described later). That is, the first reference voltage generation circuit 192 generates the first reference voltage VREF1 and outputs the first reference voltage VREF1 from the first reference voltage node NDF1. In other words, the first power-on reset circuit 190 includes a first reference voltage generation circuit 192, which outputs a voltage obtained by dividing the first power supply voltage VDD as the first reference voltage VREF1. Furthermore, when the first power-on reset circuit 190 is deactivated by the first power supply voltage VDD, the aforementioned P-type transistor TB11 switches from ON to OFF, thereby suppressing the current consumption of the first reference voltage generation circuit 192. Additionally, when the P-type transistor TB11 is reset again by the first power-on reset circuit 190, it switches from OFF to ON, preparing for voltage level detection of the first power supply voltage VDD.

[0069] The first comparator 193 operates by being supplied with a first power supply voltage VDD. The first comparator 193 compares the first power supply voltage VDD, which is the monitored voltage, with a first reference voltage VREF1, and outputs the result as a first power-on reset signal PORQ1 from the output node NPORQ1. Furthermore, the monitored voltage here is the voltage monitored by the first power-on reset circuit 190 to determine the switching between reset and reset release. Figure 8The same applies in the first power-on reset circuit. Specifically, the first comparator 193 compares the first power supply voltage VDD input to the first input node N1 with the first reference voltage VREF1 input to the second input node N2, and outputs the result as the first power-on reset signal PORQ1 from the output node NPORQ1. In other words, the first power-on reset circuit 190 includes the first comparator 193, which is operated by being supplied with the first power supply voltage VDD. The first input node N1 receives the first power supply voltage VDD, the second input node N2 receives the first reference voltage VREF1, and the first power-on reset signal PORQ1 is output from the output node NPORQ1. Thus, by generating the first reference voltage VREF1 through a resistor-based voltage divider, the responsiveness of the first power-on reset circuit 190 is improved. Therefore, even when the first power supply voltage VDD rises rapidly during initial startup, the first power-on reset signal PORQ1 can be output at the appropriate timing, thus enabling proper power-on reset operation.

[0070] The first comparator 193 includes a first transistor TC11 (N-type), a second transistor TC12 (N-type), N-type transistors TC13, TC14, TC15, TC16, TD12, and TD14, P-type transistors TC17, TC18, and TC19, and depletion-type N-type transistors TD11 and TD13. The sources of P-type transistors TC17 and TC18 are connected to node NVDD, which supplies the first power supply voltage VDD, the voltage to be monitored. The drain and gate of P-type transistor TC18 are connected to the gate of P-type transistor TC17 and the drain of the second transistor TC12. The drain of P-type transistor TC17 is connected to the drain of the first transistor TC11 and the gate of P-type transistor TC19. P-type transistors TC17 and TC18 constitute a current mirror circuit 195. The gate of the second transistor TC12 is connected to the second input node N2, and the gate of the first transistor TC11 is connected to the first input node N1. In other words, the first comparator 193 includes: a current mirror circuit 195 supplied with a first power supply voltage VDD; a first transistor TC11 whose drain is connected to the current mirror circuit 195 and whose first input node N1 is used as the gate node; and a second transistor TC12 whose drain is connected to the current mirror circuit 195 and whose second input node N2 is used as the gate node.

[0071] Additionally, the sources of transistors TC11 and TC12 are connected to the drain of N-type transistor TC13. The source of N-type transistor TC13 is connected to the drain of N-type transistor TC14, and its gate is connected to the bias node NVNA1. The source of N-type transistor TC14 is connected to the ground node NVSS, and its gate is connected to the bias node NVNB1. A bias voltage VNB1 is output to the bias node NVNB1 via a bias circuit not shown. N-type transistors TC13 and TC14 constitute the current source of the first comparator 193, which can be referred to as the first current source 196. In other words, the first comparator 193 includes a first current source 196 with one end connected to the source of transistors TC11 and TC12.

[0072] Furthermore, the sources of the first transistor TC11 and the second transistor TC12 are connected to the drain of the depletion-type N-type transistor TD11. The source of the depletion-type N-type transistor TD11 is connected to the drain of the N-type transistor TD12, and its gate is connected to the ground node NVSS, which supplies the ground voltage VSS. The gate of the N-type transistor TD12 is connected to the bias node NVNC, and its source is connected to the ground node NVSS. A bias voltage VNC is output to the bias node NVNC via a bias circuit not shown. The depletion-type N-type transistors TD11 and TD12 constitute the current source of the first comparator 193, which can be referred to as the second current source 197. In other words, the first comparator 193 includes a second current source 197 with one end connected to the source of the first transistor TC11 and the source of the second transistor TC12. By further configuring the second current source 197 in this way, the responsiveness of the first power-on reset circuit 190 can be improved. Improving the responsiveness of the first power-on reset circuit 190 is important during initial startup. However, since high responsiveness is not required for the first power-on reset circuit 190, as will be described later, low power consumption is achieved by setting the second current source 197 to be off.

[0073] Additionally, the drain of P-type transistor TC19 is connected to the drain of depletion-type N-type transistor TD13. The source of depletion-type N-type transistor TD13 is connected to the drain of N-type transistor TD14, and its gate is connected to the ground node NVSS, which supplies ground voltage VSS. The gate of N-type transistor TD14 is connected to the bias node NVND, and its source is connected to the ground node NVSS. A bias voltage VND is output to the bias node NVND via a bias circuit not shown. Depletion-type N-type transistors TD11 and TD12 constitute the current source of the first comparator 193, which can be referred to as the third current source 199. Furthermore, the bias circuit for outputting the bias voltage VND (not shown) can be the same as the bias circuit for outputting the bias voltage VNC.

[0074] The source of P-type transistor TC19 is connected to node NVDD, and its drain is connected to the drain of N-type transistor TC15 and the output node NPORQ1 of the first power-on reset circuit 190. The source of N-type transistor TC15 is connected to the drain of N-type transistor TC16, and its gate is connected to the bias node NVNA1. The source of N-type transistor TC16 is connected to ground node NVSS, and its gate is connected to the bias node NVNB1.

[0075] Transistor TC11 and transistor TC12 form a differential pair. Input node N2 corresponds to the negative input node of comparator 193, and input node N1 corresponds to the positive input node of comparator 193. A first reference voltage VREF1 is input to the negative input node, and a first power supply voltage VDD is input to the positive input node. When VDD > VREF1, comparator 193 outputs the first power-on reset signal PORQ1 of the first power supply voltage VDD to output node NPORQ1; when VDD < VREF1, it outputs the first power-on reset signal PORQ1 of the ground voltage VSS to output node NPORQ1.

[0076] Furthermore, the aforementioned second current source 197 can also be turned on during initial startup, i.e., when the first power supply voltage VDD is turned on, and then turned off after the third power-on reset signal PORQ3 from the reset control circuit 129 becomes high. In other words, the second current source 197 is turned on when the first power supply voltage VDD is turned on, and turned off after the third power-on reset signal PORQ3 becomes the reset release level. Thus, by turning off the unnecessary current source during periods when a large current flow is not required, the circuit device 100 can be operated with low power consumption. In other words, the first power-on reset circuit 190 enters a low-power mode after the third power-on reset signal PORQ3 becomes the reset release level. Thus, power consumption can be appropriately suppressed, and appropriate power-on reset operations can be performed. In addition, turning off the current source means turning off the current flowing through the current source.

[0077] Similarly, the aforementioned third current source 199 can be turned on during initial startup and then turned off after the third power-on reset signal PORQ3 from the reset control circuit 129 goes high. Thus, by disconnecting unnecessary current sources during periods when a large current flow is not required, the circuit device 100 can be operated with low power consumption.

[0078] Next, use Figure 8 The second power-on reset circuit 130 will be described. The second power-on reset circuit 130 includes a second bias circuit 131, a second reference voltage generation circuit 132, a second comparator 133, and a connection control circuit 135.

[0079] A first power supply voltage VDD is supplied to the second bias circuit 131. The second bias circuit 131 generates a bias voltage VNA2 based on the first power supply voltage VDD and outputs the bias voltage VNA2 to the second reference voltage generation circuit 132 and the second comparator 133. The second bias circuit 131 includes P-type transistors TA1 and TA2, a depletion-type N-type transistor TA3, and an N-type transistor TA4.

[0080] The sources of P-type transistors TA1 and TA2 are connected to node NVDD, which supplies the first power supply voltage VDD. Alternatively, node NVDD can also be referred to as the first power supply voltage node NVDD. The drain of P-type transistor TA1 is connected to the gates of P-type transistors TA1 and TA2, the drain of N-type transistor TA3, and the bias node NVRP2. The source and gate of N-type transistor TA3 are connected to the ground node NVSS, which supplies the ground voltage VSS. The drain of P-type transistor TA2 is connected to the drain and gate of N-type transistor TA4, and the bias node NVNA2. The source of N-type transistor TA4 is connected to the ground node NVSS. Here, the ground voltage VSS can be a power supply voltage lower than both the first power supply voltage VDD and the third power supply voltage VLOG.

[0081] A bias voltage VRP2 is generated by allowing the leakage current of the N-type transistor TA3 to flow through the P-type transistor TA1. The second bias circuit 131 outputs the bias voltage VRP2 from the bias node NVRP2 to the control circuit 135 and the second comparator 133. The leakage current of the N-type transistor TA3 is mirrored to the P-type transistor TA2, whose leakage current flows through the N-type transistor TA4, thereby generating a bias voltage VNA2. The second bias circuit 131 outputs the bias voltage VNA2 from the bias node NVNA2 to the second reference voltage generation circuit 132 and the second comparator 133.

[0082] A third power supply voltage VLOG is supplied to the second reference voltage generation circuit 132 via VLOG_REG 153, which acts as a regulator. The second reference voltage generation circuit 132 generates a second reference voltage VREF2 based on the third power supply voltage VLOG and outputs the second reference voltage VREF2 to the second comparator 133. The second reference voltage generation circuit 132 includes depletion-type N-type transistors TB1 and TB2. The drain of N-type transistor TB1 is connected to the first power supply voltage node NVDD, and its source is connected to the drain of N-type transistor TB2 and the second reference voltage node NFREF2. The source of N-type transistor TB2 is connected to the ground node NVSS. The gates of N-type transistors TB1 and TB2 are connected to the bias node NVNA2. That is, the second reference voltage generation circuit 132 generates the second reference voltage VREF2 and outputs the second reference voltage VREF2 to the second reference voltage node NFREF2. In other words, the second power-on reset circuit 130 includes a second reference voltage generation circuit 132 that generates the second reference voltage VREF2 and outputs the second reference voltage VREF2 to the second reference voltage node NVREF2.

[0083] A bias voltage VNA is applied to the gates of N-type transistors TB1 and TB2, causing current to flow through them. A second reference voltage VREF2 is determined based on this current and the dimensions of N-type transistors TB1 and TB2. This second reference voltage VREF2 is a reference voltage that converges to a predetermined voltage. For example, by changing the mirror ratio of N-type transistors TA4 and TB2, the current flowing through N-type transistor TB1 changes, thus adjusting the second reference voltage VREF2. Alternatively, by changing the dimensions of N-type transistor TB1, the source-drain voltage of N-type transistor TB1 changes, thus adjusting the second reference voltage VREF2. The dimensions of the transistors include, for example, the gate length, the gate width, or both.

[0084] A third power supply voltage VLOG is supplied to the second comparator 133. The second comparator 133 compares the third power supply voltage VLOG, which is the voltage being monitored, with a second reference voltage VREF2, and outputs the result as a second power-on reset signal PORQ2. In other words, the second power-on reset circuit 130 includes a second comparator 133 that outputs a second power-on reset signal PORQ2 by comparing the third power supply voltage VLOG with the second reference voltage VREF2.

[0085] The second comparator 133 includes N-type transistors TC1-TC6 and P-type transistors TC7-TC9. The sources of P-type transistors TC7 and TC8 are connected to the monitoring node NVLOG, which supplies the third power supply voltage VLOG as the monitoring target voltage. The gate and source of P-type transistor TC7 are connected to the gate of P-type transistor TC8 and the drain of N-type transistor TC1. The drain of P-type transistor TC8 is connected to the drain of N-type transistor TC2 and the gate of P-type transistor TC9. The sources of N-type transistors TC1 and TC2 are connected to the drain of N-type transistor TC3. The gate of N-type transistor TC1 is connected to the second reference voltage node NVREF2, and the gate of N-type transistor TC2 is connected to the monitoring node NVLOG. The source of N-type transistor TC3 is connected to the drain of N-type transistor TC4, and its gate is connected to the bias node NVNA2. The source of N-type transistor TC4 is connected to the ground node NVSS, and its gate is connected to the bias node NVNB2. A bias voltage VNB2 is output to the bias node NVNB2 via a bias circuit not shown.

[0086] The source of P-type transistor TC9 is connected to the monitored node NVLOG, and its drain is connected to the drain of N-type transistor TC5 and the output node NPORQ2 of the second power-on reset circuit 130. The source of N-type transistor TC5 is connected to the drain of N-type transistor TC6, and its gate is connected to the bias node NVNA2. The source of N-type transistor TC6 is connected to the ground node NVSS, and its gate is connected to the bias node NVNB2.

[0087] N-type transistors TC1 and TC2 form a differential pair. The gate of N-type transistor TC1 corresponds to the negative input node of the second comparator 133, and the gate of N-type transistor TC2 corresponds to the positive input node of the second comparator 133. A second reference voltage VREF2 is input to the negative input node, and a third power supply voltage VLOG is input to the positive input node. When VLOG > VREF2, the second comparator 133 outputs a second power-on reset signal PORQ2 of the power supply voltage VLOG to the output node NPORQ2; when VLOG < VREF2, it outputs a second power-on reset signal PORQ2 of the ground voltage VSS to the output node NPORQ2.

[0088] The connection control circuit 135 includes a CR circuit 136 and a switch SWPU. The switch SWPU is composed of a transistor, assumed here to be a P-type transistor. The source of the P-type transistor constituting the switch SWPU is connected to the first power supply voltage node NVDD, the drain is connected to the second reference voltage node NFREF2, and the gate is connected to the control signal node NCRQ. In other words, the second power-on reset circuit 130 includes the connection control circuit 135 connected between the first power supply voltage node NVDD and the second reference voltage node NFREF2, which supplies the first power supply voltage VDD.

[0089] The CR circuit 136 outputs a control signal CRQ to the control signal node NCRQ based on the first power supply voltage VDD, controlling the switch SWPU to be on or off. Although not shown in the figure, the CR circuit 136 can be implemented by including a P-type transistor, an N-type transistor, a capacitor, and an inverter. During a predetermined period after the first power supply voltage VDD is turned on, the CR circuit 136 maintains the switch SWPU on by keeping the control signal CRQ low. After the predetermined period has elapsed, the CR circuit 136 changes the control signal CRQ from low to high, thereby turning the switch SWPU off. Furthermore, the predetermined period can be set based on the constant current flowing through the capacitor and the capacitance value of the capacitor.

[0090] That is, the connection control circuit 135 includes a switch SWPU and a CR circuit 136. The switch SWPU is located between the first power supply voltage node NVDD and the second reference voltage node NVREF2. The CR circuit 136 outputs a control signal CRQ from the on-to-off state to the switch SWPU after a predetermined period has elapsed after the power supply voltage VDD is turned on. Thus, during the predetermined period after the power supply voltage VDD is turned on, the switch SWPU is turned on, and therefore, the second reference voltage node NVREF2 is connected to the first power supply voltage node NVDD2. In other words, the connection control circuit 135 connects the second reference voltage node NVREF2 to the first power supply voltage node NVDD during the predetermined period after the first power supply voltage VDD is turned on. Thus, during the predetermined period after the first power supply voltage VDD is turned on, the second reference voltage VREF2 input to the second comparator 133 becomes the first power supply voltage VDD. Then, after a specified period, the switch SWPU changes from on to off, so the second comparator 133 can compare the second reference voltage VREF2 with the third power supply voltage VLOG, which is the voltage being monitored.

[0091] Therefore, even if temporary instability occurs such as overshoot of the third power supply voltage VLOG, the reset can be released after the third power supply voltage VLOG stabilizes within a specified period. This allows for coordinated and appropriate power-on reset actions.

[0092] 3. Example of operation in this embodiment

[0093] Next, an example of operation will be described when the circuit device 100 of this embodiment is applied. Figure 9 This diagram illustrates an example of the operation of the circuit device 100 of this embodiment when the battery is first connected and the circuit is initially started. Figure 9In the process, firstly, the second power supply voltage VBAT rises, and the fourth power supply voltage VOUT and the third power supply voltage VLOG rise in a manner that follows the second power supply voltage VBAT. However, the voltage values ​​of the fourth power supply voltage VOUT and the third power supply voltage VLOG will not become equal to the second power supply voltage VBAT, but rather, for example... Figure 9 As shown, the voltage drops to the value between the first operating lower limit voltage VOLL and the second operating lower limit voltage VOLM. This is because the second power supply voltage VBAT is supplied from the second power supply voltage line via the parasitic diodes of P-type transistors 112 and 113, and is output as the fourth power supply voltage VOUT. Then, at the timing shown in B1, the second power-on reset signal PORQ2 from the second power-on reset circuit 130 becomes the reset release level, i.e., a high level.

[0094] In this case, the following problem exists: the entire circuit of the specified circuit 120 is reset when the first power supply voltage VDD is not supplied, or when the first power supply voltage VDD has not reached the second operating lower limit voltage VOLM. This problem cannot be solved in the structure shown in the comparative example.

[0095] Therefore, by applying the circuit device 100 of this embodiment, even if the second power-on reset signal PORQ2 at time B1 becomes high, the memory 127, which is to be reset at a voltage higher than the second operating lower limit voltage VOLM, will not be reset. At time B2, the first power supply voltage VDD begins to rise, and at time B3, after the first power supply voltage VDD exceeds the second operating lower limit voltage VOLM, the first power-on reset signal PORQ1 becomes high. As a result, the switching circuit 111 is turned on, and the fourth power supply voltage VOUT and the third power supply voltage VLOG rise. Afterwards, the fourth power supply voltage VOUT becomes equal to the first power supply voltage VDD, and the third power supply voltage VLOG is adjusted by the regulator VLOG_REG 153 to a voltage value lower than the fourth power supply voltage VOUT.

[0096] Therefore, even when the circuit device 100 is started by connecting a battery as a backup power source, the reset control circuit 129 can reset the circuit after the first power supply voltage, which is the main power supply, reaches the lower limit voltage of the circuit 120, so that the power-on reset operation can be performed appropriately.

[0097] Furthermore, it is preferable to adjust the timing of inputting the third power-on reset signal PORQ3 high into the memory 127 to be delayed by a certain period compared to the timing of turning on the switch circuit 111. This allows the memory 127 to be reset when the third power supply voltage VLOG exceeds the second operating lower limit voltage VOLM.

[0098] Figure 10This means that in Figure 1 In the comparative example, a diagram illustrates the operation of the circuit device 100 when the first power supply voltage VDD is set to a lower value for initial startup. The first power supply voltage VDD is supplied from the first power supply voltage line via the parasitic diode 322 of the switching circuit 111 and output as the fourth power supply voltage VOUT. Therefore, compared to... Figure 9 Similarly, the voltage values ​​of the fourth power supply voltage VOUT and the third power supply voltage VLOG will not become equal to the first power supply voltage VDD, but will drop to the voltage values ​​between the first operating lower limit voltage VOLL and the second operating lower limit voltage VOLM. In this case, when the timing second power-on reset signal PORQ2 on C1 goes high, the memory 127 will be reset even though the third power supply voltage VLOG has not exceeded the second operating lower limit voltage VOLM, which may cause malfunctions in the memory 127.

[0099] Figure 11 This diagram illustrates the operation of the circuit device 100 when the first power supply voltage VDD is applied and the circuit device 100 of this embodiment is initially started. As the first power supply voltage VDD rises, the first power-on reset signal PORQ1 goes high at timing D1, thus turning on the switching circuit 111. Therefore, the voltage values ​​of the fourth power supply voltage VOUT and the third power supply voltage VLOG rise in line with the first power supply voltage VDD. Then, the fourth power supply voltage VOUT becomes equal to the first power supply voltage VDD, and the third power supply voltage VLOG, through the regulator VLOG_REG 153, is lower than the fourth power supply voltage VOUT, but exhibits a voltage value higher than the second operating lower limit voltage VOLM. Then, at timing shown in D2, the second power-on reset signal PORQ2 goes high, and both the logic circuit 125 and the memory 127 are reset. Thus, even when the first power supply voltage VDD cannot be set high, a proper power-on reset operation can be performed.

[0100] The circuit arrangement described above relates to the following circuit arrangement, comprising: a first power supply line supplied with a first power supply voltage; a second power supply line supplied with a second power supply voltage; a third power supply line; a power supply circuit; a predetermined circuit; a first power-on reset circuit; a second power-on reset circuit; and a reset control circuit. The power supply circuit is connected to the first and second power supply lines, selects between the first and second power supply voltages, and outputs a third power supply voltage based on the selected voltage to the third power supply line. The predetermined circuit operates using the third power supply voltage. The first power-on reset circuit is connected to the first power supply line and outputs a first power-on reset signal based on the first power supply voltage. The second power-on reset circuit is connected to the third power supply line and outputs a second power-on reset signal based on the third power supply voltage. When the first and second power-on reset signals reach a reset release level, the reset control circuit causes the third power-on reset signal, which is output to at least a portion of the predetermined circuit, to reach a reset release level.

[0101] Therefore, even when the first power supply voltage cannot be set high, the power-on reset circuit can be properly activated by supplying an appropriate voltage value to a portion of the specified circuit and then resetting that portion of the circuit.

[0102] Additionally, the specified circuit may include: a memory; and logic circuitry that processes data from the memory and inputs a third power-on reset signal to the memory.

[0103] Therefore, in the case where it is desired to delay the startup of the memory during the initial startup, the memory can be reset for the first time by inputting the third power-on reset signal, thus enabling the appropriate power-on reset action to be performed.

[0104] Alternatively, the first lower operating limit voltage, which serves as the lower operating limit voltage of the logic circuit, can be lower than the second lower operating limit voltage, which serves as the lower operating limit voltage of the memory, and a second power-on reset signal can be input to the logic circuit.

[0105] Therefore, the logic circuit with a low operating lower limit voltage can be reset according to the second power-on reset signal, and then the memory with a high operating lower limit voltage can be reset, thus enabling the appropriate power-on reset action.

[0106] Alternatively, the first power supply voltage can be an external power supply voltage input from the outside, and the second power supply voltage can be a battery power supply voltage input from the battery.

[0107] Therefore, even if the voltage of the first power supply voltage drops, the third power supply voltage can be output based on the second power supply voltage, and the power-on reset action of the circuit device can be performed appropriately.

[0108] Alternatively, it may include a fourth power supply line supplied as a fourth power supply voltage based on a selected power supply voltage, and the power supply circuit includes a switching circuit disposed between the first power supply line and the fourth power supply line. The switching circuit may also include a diode that is forward-biased from the first power supply line toward the fourth power supply line.

[0109] Therefore, regardless of whether the switching circuit is on or off, it can continuously supply power to the specified circuit by allowing current to flow from the first power line to the fourth power line, and can perform appropriate power-on reset actions.

[0110] Alternatively, one end of the switching circuit can be connected to the first power supply line, and the power supply circuit includes a regulator whose input node is connected to the other end of the switching circuit, and the third power supply voltage is output from the output node of the regulator.

[0111] Therefore, a third power supply voltage can be generated based on the first power supply voltage at a desired voltage, and an appropriate power-on reset action can be performed.

[0112] In addition, the switching circuit can also change from open to closed when the first power-on reset signal becomes the reset release level.

[0113] Therefore, as the fourth power supply voltage rises to be equal to the first power supply voltage, the third power supply voltage can also rise. Thus, after supplying a voltage higher than the operating lower limit voltage of each circuit in the specified circuit, the reset release of the specified circuit can be performed, thereby enabling appropriate power-on reset operations.

[0114] In addition, the first power-on reset circuit can also enter low-power mode after the third power-on reset signal becomes the reset release level.

[0115] Therefore, power consumption can be appropriately suppressed, and appropriate power-on reset actions can be performed.

[0116] Alternatively, the first power-on reset circuit may also include: a first reference voltage generation circuit, whose output is a voltage obtained by dividing the first power supply voltage as the first reference voltage; and a first comparator, which is supplied with the first power supply voltage and operates thereon, wherein the first input node of the first comparator is input with the first power supply voltage, the second input node of the first comparator is input with the first reference voltage, and the first power-on reset signal is output from the output node of the first comparator.

[0117] Therefore, since the first reference voltage is generated by voltage division based on resistors, the responsiveness of the first power-on reset circuit is improved. Even when the first power supply voltage rises rapidly, the first power-on reset signal can be output at the appropriate timing, thus enabling appropriate power-on reset actions.

[0118] Alternatively, the first comparator may include a current mirror circuit, a first transistor, a second transistor, a first current source, and a second current source. A first power supply voltage may also be supplied to the current mirror circuit. Alternatively, the current mirror circuit may be connected to the drain of the first transistor, with the first input node becoming the gate node of the first transistor. Alternatively, the current mirror circuit may be connected to the drain of the second transistor, with the second input node becoming the gate node of the second transistor. Alternatively, one end of the first current source may be connected to the source of the first transistor and the source of the second transistor. Alternatively, one end of the second current source may be connected to the source of the first transistor and the source of the second transistor. Furthermore, the second current source may be turned on when the first power supply voltage is applied and turned off after the third power-on reset signal becomes a reset de-level.

[0119] Therefore, when low current demand is not required, the circuit can operate with low power consumption by disconnecting unnecessary current sources. This allows for appropriate power consumption suppression and proper power-on reset.

[0120] Alternatively, the second power-on reset circuit may also include a second comparator, a second reference voltage generation circuit, and a connection control circuit. The second comparator may also output a second power-on reset signal by comparing the third power supply voltage and the second reference voltage. Alternatively, a second reference voltage may be generated and output to a second reference voltage node. Alternatively, the connection control circuit may be connected between the first power supply voltage node supplied with the first power supply voltage and the second reference voltage node, connecting the second reference voltage node to the first power supply voltage node for a predetermined period after the first power supply voltage is turned on.

[0121] Therefore, even if the performance of the third power supply voltage temporarily becomes unstable, the second power-on reset signal becomes high after a specified period, thus enabling a coordinated and appropriate power-on reset action.

[0122] Furthermore, the real-time clock device of this embodiment may also include a circuit device and an oscillator. Additionally, the circuit device may include: a regulator that generates a third power supply voltage based on a power supply voltage output by selecting a first power supply voltage; and an oscillation circuit that generates a clock signal by oscillating the oscillator. Furthermore, the circuit is specified to include a timing circuit that performs timing processing based on the clock signal.

[0123] Therefore, the circuit device can be applied to the real-time clock device.

[0124] Furthermore, although this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the novel aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Additionally, the structure and operation of the circuit device and the real-time clock device are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit arrangement, characterized by comprises: a first power supply line supplied with a first power supply voltage; a second power supply line supplied with a second power supply voltage; a third power supply line; a power supply circuit connected to the first power supply line and the second power supply line, selects the first power supply voltage or the second power supply voltage, and outputs a third power supply voltage based on the selected power supply voltage to the third power supply line; a prescribed circuit that operates with the third power supply voltage; a first power-on reset circuit connected to the first power supply line, which outputs a first power-on reset signal based on the first power supply voltage; a second power-on reset circuit connected to the third power supply line, which outputs a second power-on reset signal based on the third power supply voltage; and a reset control circuit that, when the first power-on reset signal and the second power-on reset signal become reset release levels, causes the third power-on reset signal output to at least a part of the prescribed circuit to become a reset release level, the first power-on reset circuit enters a low power consumption mode after the third power-on reset signal becomes a reset release level.

2. The circuit device according to claim 1, wherein the prescribed circuit comprises: a memory; and a logic circuit that processes data from the memory, the third power-on reset signal is input to the memory.

3. The circuit device according to claim 2, wherein a first operating lower limit voltage that is an operating lower limit voltage of the logic circuit is lower than a second operating lower limit voltage that is an operating lower limit voltage of the memory, the second power-on reset signal is input to the logic circuit.

4. The circuit device according to any one of claims 1 to 3, wherein the first power supply voltage is an external power supply voltage input from the outside, the second power supply voltage is a battery power supply voltage input from a battery.

5. The circuit device according to any one of claims 1 to 3, wherein the circuit device comprises a fourth power supply line supplied with a fourth power supply voltage that is the fourth power supply voltage based on the selected power supply voltage, the power supply circuit comprises a switching circuit provided between the first power supply line and the fourth power supply line, the switching circuit comprises a diode that takes a direction from the first power supply line toward the fourth power supply line as a forward direction.

6. The circuit device according to claim 5, wherein one end of the switching circuit is connected to the first power supply line, the power supply circuit comprises a regulator whose input node is connected to the other end of the switching circuit, and whose output node outputs the third power supply voltage.

7. The circuit device according to claim 5, wherein when the first power-on reset signal becomes a reset release level, the switching circuit changes from off to on.

8. The circuit device according to any one of claims 1 to 3, wherein the first power-on reset circuit comprises: a first reference voltage generation circuit that outputs a voltage obtained by dividing the first power supply voltage as a first reference voltage; and a second reference voltage generation circuit that outputs a voltage obtained by dividing the second power supply voltage as a second reference voltage. A first comparator which is supplied with the first power supply voltage, a first input node of which is input with the first power supply voltage, a second input node of which is input with the first reference voltage, and from an output node of which the first power-on reset signal is output.

9. The circuit device according to claim 8, wherein the first comparator includes: a current mirror circuit which is supplied with the first power supply voltage; a first transistor whose drain is connected to the current mirror circuit and whose gate node is the first input node; a second transistor whose drain is connected to the current mirror circuit and whose gate node is the second input node; a first current source whose one end is connected to a source of the first transistor and a source of the second transistor; and a second current source whose one end is connected to the source of the first transistor and the source of the second transistor, the second current source is turned on when the first power supply voltage is turned on and is turned off after the third power-on reset signal becomes a reset release level.

10. The circuit device according to any one of claims 1 to 3, wherein the second power-on reset circuit includes: a second comparator which compares the third power supply voltage and a second reference voltage, and outputs the second power-on reset signal therefrom; a second reference voltage generation circuit which generates the second reference voltage and outputs the second reference voltage to a second reference voltage node; and a connection control circuit which is connected between a first power supply voltage node to which the first power supply voltage is supplied and the second reference voltage node, the connection control circuit connects the second reference voltage node to the first power supply voltage node for a prescribed period after the first power supply voltage is turned on. includes: the circuit device according to any one of claims 1 to 10; and 11. A real-time clock device, characterized by a vibrator, the circuit device includes: a regulator which generates the third power supply voltage from a power supply voltage which is output by selecting the first power supply voltage; and an oscillation circuit which generates a clock signal by oscillating the vibrator, the prescribed circuit includes a timing circuit which performs a timing process based on the clock signal. ​ ​

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