A chip startup flow simulation verification method and related device

Abstract

The application provides a chip starting process simulation verification method and related device, when the power supply controller simulation model detects a power-on indication simulation signal output by a simulation chip, the power supply controller simulation model simulates a power-on operation of the simulation chip according to the power-on indication simulation signal, and then realizes simulation of a power-on reset process of the simulation chip; a safety starting engine simulation model, a power consumption management engine simulation model and a processor simulation model corresponding to the simulation chip are constructed; the safety starting engine simulation model, the power consumption management engine simulation model and the processor simulation model are initialized and simulated to start, so as to simulate a chip starting process, and to determine a chip path verification result and a system function verification result. The whole front-end hardware verification and software development can be separated, so that the whole verification starting point of a large chip is at least half a year earlier, most problems of the whole chip are exposed as early as possible and solved in time, the development progress is improved, and possible economic losses are reduced.

Description

Technical Field

[0001] This invention relates to the field of chip verification, and more specifically, to a chip startup process simulation verification method and related apparatus. Background Technology

[0002] The chip boot flow refers to the entire initialization process from power-on (power-on reset) to full system normal operation, until the operating system has started. This initialization process involves the collaboration of multiple hardware and software phases to ensure the chip can correctly load and execute the required programs or operating system.

[0003] Existing chip development verification methods require chip development to be completed before verification can be performed. However, the chip development completion time is already close to the chip tape-out time. If a major error in the Register Transfer Level (RTL) is discovered at this time, it may lead to a redesign of the chip, delaying the chip tape-out time and greatly impacting the project cycle. Summary of the Invention

[0004] The purpose of this invention is to provide a chip startup process simulation and verification method and related apparatus to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a chip boot process simulation verification method, the method comprising:

[0007] When the power controller simulation model detects the power-on indication simulation signal output by the simulation chip, it simulates the power-on action of the simulation chip according to the power-on indication simulation signal, thereby realizing the simulation of the power-on reset process of the simulation chip.

[0008] Construct simulation models for the secure boot engine, power management engine, and processor corresponding to the simulation chip;

[0009] The secure boot engine simulation model, the power management engine simulation model, and the processor simulation model are initialized and simulated to simulate the chip boot process in order to determine the chip path verification results and system function verification results.

[0010] Secondly, embodiments of the present invention provide a chip boot process simulation and verification device, the device comprising:

[0011] The first processing unit is used to simulate the power-on action of the simulation chip according to the power-on indication simulation signal when the power controller simulation model detects the power-on indication simulation signal output by the simulation chip, thereby realizing the simulation of the power-on reset process of the simulation chip.

[0012] The first processing unit is also used to construct a secure boot engine simulation model, a power management engine simulation model, and a processor simulation model corresponding to the simulation chip;

[0013] The second processing unit is used to initialize and simulate the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model to simulate the chip boot process and determine the chip path verification results and system function verification results.

[0014] Thirdly, embodiments of the present invention provide a storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0015] Fourthly, embodiments of the present invention provide an electronic device, the electronic device comprising: a processor and a memory, the memory being used to store one or more programs; when the one or more programs are executed by the processor, the above-described method is implemented.

[0016] Compared to existing technologies, the chip startup process simulation verification method and related apparatus provided in this invention involve a power controller simulation model simulating the power-on action of the simulation chip based on the power-on indication simulation signal output by the simulation chip when the power controller simulation model detects the power-on indication simulation signal, thereby simulating the power-on reset process of the simulation chip; constructing a secure boot engine simulation model, a power management engine simulation model, and a processor simulation model corresponding to the simulation chip; and initializing and simulating the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model to simulate the chip startup process and determine the chip path verification results and system function verification results. This method can separate the entire front-end hardware verification from software development, thereby advancing the entire verification starting point of a large chip by at least six months. This allows most of the chip's problems to be exposed and resolved early, improving development progress and reducing potential significant economic losses.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0020] Figure 2 This is a flowchart illustrating the chip startup process simulation verification method provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of a chip startup process simulation and verification device provided in an embodiment of the present invention.

[0022] In the diagram: 10-Processor; 11-Memory; 12-Bus; 13-Communication interface; 501-First processing unit; 502-Second processing unit. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0025] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0027] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0028] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] This invention provides an electronic device, which may be a computer device, a server device, or a mobile phone device, etc. Please refer to... Figure 1 This is a schematic diagram of the structure of an electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected via the bus 12. The processor 10 is used to execute executable modules, such as computer programs, stored in the memory 11.

[0031] Processor 10 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the chip startup process simulation verification method can be completed through the integrated logic circuits in the hardware of processor 10 or through software instructions. The aforementioned processor 10 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0032] The memory 11 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage.

[0033] Bus 12 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. Figure 1 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus 12 or one type of bus 12.

[0034] The memory 11 is used to store programs, such as the program corresponding to a chip boot process simulation and verification device. The chip boot process simulation and verification device includes at least one software functional module that can be stored in the memory 11 in the form of software or firmware, or embedded in the operating system (OS) of the electronic device. Upon receiving an execution instruction, the processor 10 executes the program to implement the chip boot process simulation and verification method.

[0035] The electronic device provided in this embodiment of the invention may further include a communication interface 13. The communication interface 13 is connected to the processor 10 via a bus.

[0036] It should be understood that, Figure 1The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0037] The chip boot process simulation and verification method provided in this embodiment of the invention can be applied to, but is not limited to, applications. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The simulation and verification method for the chip startup process includes S10, S20 and S30, which are described in detail below.

[0038] S10, when the power controller simulation model detects the power-on indication simulation signal (S3, S0) output by the simulation chip, it simulates the power-on action of the simulation chip according to the power-on indication simulation signal, thereby realizing the power-on reset process of the simulation chip.

[0039] The power controller simulation model is also called the PMIC simulation model, and the power-on indication simulation signals include the S3 power-on indication simulation signal and the S0 power-on indication simulation signal.

[0040] If the power-on reset process is correct, then perform simulation verification of the subsequent chip startup process.

[0041] S20 constructs simulation models for the secure boot engine, power management engine, and processor corresponding to the simulation chip.

[0042] Among them, the Security Engine (SE) simulation model corresponds to the secure boot engine in the simulation chip; the Power Management engine (PM) simulation model corresponds to the power management engine in the simulation chip; and the Application engine (AP) simulation model corresponds to the Central Processing Unit (CPU) in the simulation chip.

[0043] By constructing simulation models of the secure boot engine, power management engine, and processor corresponding to the simulation chip, simulation verification is performed, thus decoupling hardware function verification from boot firmware and related underlying software development.

[0044] S30 initializes and simulates the startup of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model to simulate the chip startup process and determine the chip path verification results and system function verification results.

[0045] If the initial simulation starts successfully, it means that both the chip path verification result and the system function verification result are qualified. If any step of the simulation cannot be completed, it means that it is unqualified.

[0046] The chip boot process simulation verification method provided in this invention can separate the entire SoC front-end hardware verification from software development, thereby advancing the entire verification starting point of the large chip by at least six months. This allows most of the chip's problems to be exposed and resolved as early as possible before the Boot ROM & FW development is completed, thus greatly improving the overall SoC development progress and reducing potential major economic losses.

[0047] During the initialization and simulation startup process, external functions need to be called. To accurately identify the execution entity of the called functions and ensure the correctness of the startup process, this embodiment of the invention also provides an optional implementation method, please refer to the following. S30, Initialize and start the simulation of the secure boot engine model, the power management engine model, and the processor simulation model, including: S3A, S3B, and S3C, which are described in detail below.

[0048] S3A introduces a state machine to monitor the state of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model.

[0049] The state machine in this embodiment of the invention can be an initial stage (init_stage) state machine.

[0050] When S3B receives a function call request, it determines the current initialization model based on the monitoring results of the state machine.

[0051] The current initialization model is any one of the following: the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model.

[0052] S3C configures the target function to the current initialization model to complete the corresponding initialization actions. The target function is the calling function specified by the function call request, which can be, but is not limited to, a UVM function.

[0053] Even for the same function call request, different simulation models can be configured at different stages based on the monitoring results of the state machine.

[0054] Optionally, the safe startup engine simulation model is initialized and simulated, including steps S311 to S317.

[0055] S311, Determine whether the Boot ROM (including the Boot firmware in the Secure Boot Engine simulation model) in the Secure Boot Engine simulation model is complete.

[0056] The emulation boot read-only memory, also known as Boot ROM, includes the emulation boot firmware in the secure boot engine emulation model.

[0057] S312, under the condition that the read-only memory is intact during simulation startup, checks and repairs the static memory in the safe startup engine simulation model.

[0058] Optionally, the static RAM in the secure boot engine simulation model can be checked and repaired by generating relevant function call requests.

[0059] S313, if the static memory is successfully tested and repaired, simulate the boot security program (Boot SE FW) loading process, load the boot security program into the static memory, and verify the loaded boot security program according to the current lifecycle.

[0060] Optionally, different signatures can correspond to different lifecycles.

[0061] S314, after the security procedure verification is successful, simulates the loading process of the power management program (PM FW), loads the power management program into the power management engine simulation model, and verifies the loaded power management program according to the current life cycle.

[0062] S315 initializes the data network router and memory controller in the emulation chip after the power management program passes the verification.

[0063] Optionally, the data network router (Datafabir) and memory controller (DDR Control) in the simulation chip can be initialized by generating relevant function call requests.

[0064] Alternatively, the initialization configuration data can be written directly into it, thereby shortening the initialization startup time.

[0065] S316, after confirming that the data network router and memory controller have been successfully initialized, simulates the primary boot loader (PBL) loading process, loads the primary boot loader into the processor simulation model, and verifies the loaded primary boot loader according to its current lifecycle.

[0066] S317, if the processor bootloader verification passes, confirms that the secure boot engine simulation model initialization simulation has successfully started.

[0067] After confirming that the safe startup engine simulation model has successfully initialized and started, the power management engine simulation model can be started.

[0068] Optionally, the power management engine simulation model is initialized and started, including: S321, S322 and S323, which are described in detail below.

[0069] S321 initializes the sensors in the simulation chip.

[0070] Optionally, the sensors in the simulation chip can be initialized by generating relevant function call requests. The sensors can be various sensors within the chip, such as gravity sensors, temperature sensors, etc.

[0071] S322: After successful sensor initialization, configure the clock simulation model.

[0072] S323, after the clock simulation model is successfully configured, confirm that the power management engine simulation model initialization and simulation start are successful.

[0073] After confirming that the power management engine simulation model has been successfully initialized and started, the processor simulation model can be started.

[0074] Optionally, the processor simulation model is initialized and the simulation is started, including S331 and S332.

[0075] S331 initializes the graphics engine, video stream encryption / decryption engine, display engine, and bus network card in the simulation chip.

[0076] Optionally, the graphics engine (GPU), video stream encryption / decryption engine (VPU), display engine (DPU), and network interface card (GMAC) in the simulation chip can be initialized by generating relevant function call requests.

[0077] With the graphics engine, video stream encryption / decryption engine, display engine, and bus network card successfully initialized, the processor simulation model initialization and simulation startup of S332 is successful.

[0078] Optionally, the chip startup process simulation verification method also includes: S41, S42 and S43.

[0079] S41, upon receiving a warm reset signal (a type of system reset signal) or a power-on signal, starts by determining whether the simulation boot read-only memory in the secure boot engine simulation model is intact, and repeatedly initializes and simulates the boot engine simulation model, power management engine simulation model, and processor simulation model.

[0080] S42, upon receiving the sleep-wake signal (STR), checks and repairs the static memory in the secure boot engine simulation model, and repeatedly initializes and simulates the secure boot engine simulation model, power management engine simulation model, and processor simulation model.

[0081] S43, upon receiving a power-off signal (SD), shuts down the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model.

[0082] By building more complex system scenarios, we can discover system design issues related to security and low-power processes earlier.

[0083] Optionally, the chip startup process simulation verification method also includes: a fast simulation switch (Fast sim) in the startup clock simulation model to achieve the purpose of accelerating simulation verification.

[0084] The Fast Sim switch in the clock simulation model enables the clock-controlled voltage-controlled vibrator (CLKVCO) to lock quickly.

[0085] In an alternative implementation, the low-frequency clock signal input to the power management simulation unit inside the simulation chip can also be boosted, for example, by boosting the 32K clock frequency, thereby accelerating the simulation verification.

[0086] Please see Figure 3 , Figure 3 The present invention provides a chip startup process simulation and verification device, which is optionally applied to the electronic device described above.

[0087] The chip startup process simulation and verification device includes: a first processing unit 501 and a second processing unit 502.

[0088] The first processing unit 501 is used to simulate the power-on action of the simulation chip according to the power-on indication simulation signal when the power controller simulation model detects the power-on indication simulation signal output by the simulation chip, thereby realizing the power-on reset process of the simulation chip.

[0089] The first processing unit 501 is also used to construct the simulation model of the secure boot engine, the simulation model of the power management engine, and the simulation model of the processor corresponding to the simulation chip.

[0090] The second processing unit 502 is used to initialize and simulate the startup of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model to simulate the chip startup process and determine the chip path verification results and system function verification results.

[0091] It should be noted that the chip boot process simulation and verification device provided in this embodiment can execute the method flow shown in the above method flow embodiment to achieve the corresponding technical effects. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments.

[0092] This invention also provides a storage medium storing computer instructions and programs, which, when read and run, execute the chip boot process simulation verification method described in the above embodiments. The storage medium may include memory, flash memory, registers, or a combination thereof.

[0093] The following provides an electronic device, which may be a computer device, a server device, or a mobile phone device, etc. This electronic device, for example... Figure 1 As shown, the chip startup process simulation and verification method described above can be implemented. Specifically, the electronic device includes: a processor 10, a memory 11, and a bus 12. The processor 10 may be a CPU. The memory 11 is used to store one or more programs, and when one or more programs are executed by the processor 10, the chip startup process simulation and verification method of the above embodiment is executed.

[0094] In summary, the chip startup process simulation verification method and related apparatus provided by this invention involve a power controller simulation model simulating the power-on action of the simulation chip when it detects a power-on indication simulation signal output by the simulation chip, thereby simulating the power-on reset process of the simulation chip. The method constructs a secure boot engine simulation model, a power management engine simulation model, and a processor simulation model corresponding to the simulation chip. It then initializes and simulates these models to simulate the chip startup process, thereby determining the chip path verification results and system function verification results. This approach separates the entire front-end hardware verification from software development, allowing the entire verification process for large chips to begin at least six months earlier. This enables the majority of chip problems to be exposed and resolved early, improving development progress and reducing potential significant economic losses.

[0095] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0096] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for simulating and verifying the chip boot process, characterized in that, The method includes: When the power controller simulation model detects the power-on indication simulation signal output by the simulation chip, it simulates the power-on action of the simulation chip according to the power-on indication simulation signal, thereby realizing the simulation of the power-on reset process of the simulation chip. Construct simulation models for the secure boot engine, power management engine, and processor corresponding to the simulation chip; The secure boot engine simulation model, the power management engine simulation model, and the processor simulation model are initialized and simulated to simulate the chip boot process in order to determine the chip path verification results and system function verification results. The initialization and simulation startup of the secure boot engine simulation model includes: determining whether the simulation boot read-only memory in the secure boot engine simulation model is complete; if the simulation boot read-only memory is complete, checking and repairing the static memory in the secure boot engine simulation model; if the static memory is successfully detected and repaired, simulating the boot security program loading process, loading the boot security program into the static memory, and verifying the loaded boot security program according to its current lifecycle; if the boot security program verification is successful, simulating the power management program loading process, loading the power management program into the power management engine simulation model, and verifying the loaded power management program according to its current lifecycle; if the power management program verification is successful, initializing the data network router and memory controller in the simulation chip; if the data network router and memory controller initialization is successful, simulating the processor bootloader loading process, loading the processor bootloader into the processor simulation model, and verifying the loaded processor bootloader according to its current lifecycle; if the processor bootloader verification is successful, the initialization and simulation startup of the secure boot engine simulation model is determined to be successful.

2. The chip boot process simulation verification method as described in claim 1, characterized in that, The initialization and simulation startup of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model includes: A state machine is introduced to monitor the states of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model; When a function call request is received, the current initialization model is determined based on the monitoring results of the state machine, wherein the current initialization model is any one of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model; The objective function is configured into the current initialization model to complete the corresponding initialization action, wherein the objective function is the calling function specified by the function call request.

3. The chip boot process simulation verification method as described in claim 1, characterized in that, The initialization and simulation startup of the power management engine simulation model includes: Initialize the sensors in the simulation chip; After the sensor is successfully initialized, configure the clock simulation model; After the clock simulation model is successfully configured, it is confirmed that the power management engine simulation model initialization and simulation startup are successful.

4. The chip boot process simulation verification method as described in claim 3, characterized in that, The processor simulation model is initialized and the simulation is started, including: Initialize the graphics engine, video stream encryption / decryption engine, display engine, and bus network card in the simulation chip; With the graphics engine, video stream encryption / decryption engine, display engine, and bus network card successfully initialized, the processor simulation model initialization and simulation startup are successful.

5. The chip boot process simulation verification method as described in claim 4, characterized in that, The method further includes: Upon receiving the temperature reset signal, starting from determining whether the simulation boot read-only memory in the secure boot engine simulation model is intact, the initialization simulation boot of the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model is repeatedly performed. Upon receiving the sleep / wake signal, the static memory in the secure boot engine simulation model is checked and repaired, and the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model are repeatedly initialized and simulated for startup.

6. The chip boot process simulation verification method as described in claim 3, characterized in that, The method further includes: Activate the acceleration simulation switch in the clock simulation model to accelerate simulation verification.

7. A chip boot process simulation and verification device, characterized in that, The device includes: The first processing unit is used to simulate the power-on action of the simulation chip according to the power-on indication simulation signal when the power controller simulation model detects the power-on indication simulation signal output by the simulation chip, thereby realizing the simulation of the power-on reset process of the simulation chip. The first processing unit is also used to construct a secure boot engine simulation model, a power management engine simulation model, and a processor simulation model corresponding to the simulation chip; The second processing unit is used to initialize and simulate the secure boot engine simulation model, the power management engine simulation model, and the processor simulation model to simulate the chip boot process and determine the chip path verification results and system function verification results. The initialization and simulation startup of the secure boot engine simulation model includes: determining whether the simulation boot read-only memory in the secure boot engine simulation model is complete; if the simulation boot read-only memory is complete, checking and repairing the static memory in the secure boot engine simulation model; if the static memory is successfully detected and repaired, simulating the boot security program loading process, loading the boot security program into the static memory, and verifying the loaded boot security program according to its current lifecycle; if the boot security program verification is successful, simulating the power management program loading process, loading the power management program into the power management engine simulation model, and verifying the loaded power management program according to its current lifecycle; if the power management program verification is successful, initializing the data network router and memory controller in the simulation chip; if the data network router and memory controller initialization is successful, simulating the processor bootloader loading process, loading the processor bootloader into the processor simulation model, and verifying the loaded processor bootloader according to its current lifecycle; if the processor bootloader verification is successful, the initialization and simulation startup of the secure boot engine simulation model is determined to be successful.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-6.

9. An electronic device, characterized in that, include: Processor and memory, the memory being used to store one or more programs; When the one or more programs are executed by the processor, the method as described in any one of claims 1-6 is implemented.

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