High-stability power-on reset circuit with automatic hysteresis adjusting function
The power-on reset circuit, composed of a power detection module, a hysteresis comparison module, and a bootstrap bias unit, solves the problems of logic malfunction and reset threshold drift caused by power fluctuations and slow power-on in the prior art. It achieves a highly stable and low-power reset signal output, which is suitable for highly integrated circuit designs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-02-11
- Publication Date
- 2026-05-19
AI Technical Summary
Existing power-on reset circuits are prone to problems such as logic malfunction, reset threshold drift, and insufficient anti-interference capability in scenarios where the power supply is unstable, fluctuating, or slow-power-on.
By employing a power detection module, a hysteresis comparison module, a bootstrap bias unit, and an automatic hysteresis switch structure, combined with a dynamic regulated power rail generation unit, automatic hysteresis adjustment function is achieved, improving the stability and anti-interference capability of the reset signal, and optimizing the circuit structure to reduce chip area.
Under complex conditions such as no steady-state power supply, power fluctuations, and slow power-up, the system maintains the logical determinism of the reset signal, reduces the impact of process and temperature changes, suppresses reset signal jitter and false triggering, reduces chip area footprint, and meets the requirements of high integration and low power consumption.
Smart Images
Figure CN122068883A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically to a highly stable power-on reset circuit with automatic hysteresis adjustment function. Background Technology
[0002] Existing power-on reset circuits are mainly divided into two categories: POR structures based on RC charging delay and POR structures based on voltage divider or MOSFET voltage detection. Both types of structures have significant drawbacks.
[0003] 1. The POR structure based on RC charging delay relies on the charging and discharging of capacitors and resistors to achieve delayed triggering. Its problems include: when the power supply rise time is slow, the capacitor overcharges, causing the delay signal to become inaccurate; when the power supply rise time is much longer than the RC delay time, the reset pulse width and amplitude are insufficient, making it unable to drive the subsequent logic circuits; large-value resistors and large capacitors occupy a large chip area (typically exceeding 30%), which is not conducive to high integration and low power consumption design.
[0004] 2. The POR structure based on voltage divider resistors or MOSFET voltage detection monitors the power supply voltage through MOSFET voltage divider or diode connection. Its problems include: the threshold voltage of MOSFET devices and the flip-flop threshold fluctuate greatly due to process angle, temperature changes and power supply noise, resulting in significant offset of the reset trigger point; false triggering or reset signal jitter is prone to occur in power supply fluctuation environment, and stability is difficult to guarantee; deterministic logic output cannot be maintained in the absence of steady-state power supply, which can easily lead to system initialization failure.
[0005] While existing technologies, including published patents, have made some improvements in local performance, they have not effectively solved the core problems such as logic confusion, unstable reset threshold, and weak anti-interference ability under conditions of no steady-state power supply. Summary of the Invention
[0006] To address the aforementioned technical problems in existing technologies, this invention provides a highly stable power-on reset circuit with automatic hysteresis adjustment. This circuit addresses the shortcomings of existing power-on reset circuits, which are prone to logic malfunction, reset threshold drift, and insufficient anti-interference capability under unstable, fluctuating, or slow power-on scenarios. The circuit achieves the following objectives: maintaining the logical determinism of the reset signal under complex conditions such as no steady-state power supply, power fluctuations, and slow power-on; improving the stability of the reset threshold and reducing the impact of process and temperature changes; automatically adapting to power fluctuation amplitude and suppressing reset signal jitter and false triggering; and optimizing the circuit structure to reduce chip area and meet the requirements of high integration and low power consumption.
[0007] A highly stable power-on reset circuit with automatic hysteresis adjustment function is characterized in that it comprises: a power supply detection module, a hysteresis comparison module, a bootstrap bias unit, and an automatic hysteresis switch structure.
[0008] The power supply detection module is connected to the external power supply voltage VDD to monitor the rise process, stable state and fluctuation of the power supply voltage in real time, and outputs the voltage detection signal to the hysteresis comparison module.
[0009] As an optimized circuit design option, the input of the hysteresis comparator module receives the voltage detection signal from the power supply detection module. Its built-in reference threshold circuit can compare the voltage detection signal with the reference threshold and generate an initial reset signal based on the comparison result. The hysteresis comparator module is also coupled with an automatic hysteresis switch structure and receives a threshold adjustment signal to dynamically change the reference threshold range.
[0010] The input of the automatic hysteresis switch structure is connected to both the output of the power detection module and the output of the hysteresis comparison module. The automatic hysteresis switch structure can detect the power rise rate and voltage fluctuation amplitude, and output a threshold adjustment signal to the hysteresis comparison module based on the detection results, automatically expanding or narrowing the reference threshold range of the hysteresis comparison module.
[0011] Furthermore, the power-on reset circuit also includes a dynamic regulated power rail generation unit, which can improve the system's ability to suppress power supply noise.
[0012] Furthermore, the dynamic regulated power rail generation unit includes a ninth MOS transistor M9, whose gate is connected to ground via a first inverter INV1 and a second inverter INV2; the source of the ninth MOS transistor M9 is connected to the output terminal of the external power supply voltage VDD, and the drain is connected to one end of the first resistor R1, and serves as the internal regulated power rail V_steady.
[0013] Furthermore, a first capacitor C1 is also provided between the internal regulated power rail V_steady and ground.
[0014] As an optimized circuit design option, the power detection module includes the following circuit structure: the gate and drain of the first MOSFET M1 are shorted, and the internal regulated power rail V_steady is transmitted to the gate of the first MOSFET M1 through the first resistor R1 and the second resistor R2 connected in series in sequence, thereby realizing the detection of the internal regulated power rail V_steady.
[0015] As an optimized circuit design option, the hysteresis comparator module can detect the gate voltage change of the first MOS transistor M1, determine and generate a reset signal based on a preset threshold, and the reset signal is sent out from the output of the fourth inverter INV4.
[0016] As an optimized circuit design option, the automatic hysteresis switching structure includes a fourth MOS transistor M4. The input terminal of the fourth inverter INV4D is connected to the gate of the fourth MOS transistor M4 through a third inverter INV3. The drain and source of the fourth MOS transistor M4 are connected in parallel across the two ends of a second resistor R2.
[0017] As an optimized circuit design option, the power-on reset circuit also includes a bootstrap bias unit. One end of the bootstrap bias unit is connected to the external power supply voltage VDD, and the other end is coupled to the power detection module and the hysteresis comparison module respectively. It provides an internal reference current during the initial power-on phase to achieve self-biasing of the circuit and ensure that the power-on reset output maintains a defined logic state.
[0018] This invention offers the following advantages: The proposed power-on reset circuit features deterministic logic, high stability, high integration, wide adaptability, and rapid response. Under conditions of no steady-state power supply, slow power-on, and power fluctuations, the bootstrap bias unit and positive feedback mechanism ensure that the POR output remains in a deterministic logic state, preventing system initialization failure. Its automatic hysteresis adjustment function dynamically adapts to power fluctuations, suppressing reset signal jitter and false triggering, reducing the impact of process corner and temperature changes on the reset threshold, and improving the circuit's anti-interference capability. Furthermore, it eliminates the need for large-size RC components, resulting in a compact circuit structure that significantly reduces chip area footprint, meeting the design requirements of highly integrated integrated circuits. It not only operates stably over a wide voltage rise rate range but is also suitable for complex power supply environments such as automotive electronics and industrial control, balancing low power consumption and high reliability. The current-voltage coupled positive feedback mechanism enables rapid resetting of the reset signal, ensuring timely initialization of subsequent logic circuits and improving system startup efficiency. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the circuit structure of the present invention;
[0020] Figure 2 This is a schematic diagram of the power-on reset circuit of the present invention.
[0021] Figure 3 This is a schematic diagram illustrating the principle of inverter flip-threshold adjustment.
[0022] Figure 4 This is a schematic diagram of the circuit operation characteristics under the first power supply rise rate.
[0023] Figure 5 This is a schematic diagram of the circuit operation characteristics under the second power supply rise rate.
[0024] Figure 6 This is a schematic diagram of the circuit operation characteristics under the third power supply rise rate. Detailed Implementation
[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0026] To fully illustrate the specific implementation of the technical solution of this invention, the circuit structure and working process of each unit are described in detail below.
[0027] like Figure 1 As shown, the power-on reset circuit of the present invention includes a power detection module, a hysteresis comparison module, and an automatic hysteresis switch structure. The modules work together to achieve a highly stable reset function.
[0028] Power supply detection module: Composed of resistors R1 and R2, and NMOS transistor M1, it monitors the rise of the external power supply voltage VDD, reflecting the power-on state of VDD through changes in the gate voltage of M1. Hysteresis comparator module: Composed of PMOS transistors M3, M2, M5, M6, M7, and M8, and inverter INV4, it detects changes in the gate voltage of M1, determines and generates a reset signal based on a preset threshold, and implements hysteresis functionality through device characteristics. Automatic hysteresis switch structure: Composed of NMOS transistor M4, connected in parallel with resistors R1 and R2, it adjusts the total equivalent resistance of the circuit according to the state of the POR signal, thereby automatically adjusting the hysteresis range and suppressing output jitter.
[0029] The key design points of the circuit are explained below: NMOS transistor M1 is a diode-connected transistor (gate and drain shorted) used for voltage detection and current limiting. The inverter structure composed of MOS transistor M2 and PMOS transistor M3 is used for voltage comparison; its switching threshold is determined by the size ratio of NMOS transistor M2 to PMOS transistor M3 and the mobility ratio of PMOS to NMOS transistors due to process variations. The output of inverter INV43 is the POR signal output terminal, used to output a reset signal to subsequent circuits. The gate of NMOS transistor M4 is connected to the output of inverter INV3 at node V1. NMOS transistor M4 is a switch transistor connected in parallel with a resistor, used to adjust the equivalent resistance of the loop to achieve hysteresis characteristics.
[0030] To further explain the circuit's working principle, the timing parameters will be discussed in detail below.
[0031] like Figure 2As shown, the horizontal axis represents time t, and the vertical axis represents voltage V. The graph contains three timing curves: VDD (supply voltage), VGS (gate-source voltage of NMOS transistor M1), and POR (reset signal) voltage output (POR_OUT). The meanings of each timing parameter are as follows:
[0032] VDD: External power supply voltage, which rises linearly from 0V to a stable operating voltage (e.g., 5V) at a fixed rate (typically 0.1V / ms to 1V / ms).
[0033] VGS1: Gate-source voltage of NMOS transistor M1. Since M1 operates in the saturation region, its voltage change is proportional to the square root of the current I flowing through M1, and the rate of increase gradually slows down as VDD increases.
[0034] POR_OUT: Reset signal, initially high (VDD). When the difference between VGS1 and VDD increases to the critical threshold VTHP, it flips to low (0V) and remains stable. Simultaneously, the automatic hysteresis switch turns off and remains stable.
[0035] To further illustrate the reset signal generation process of this invention, fine lines provide a detailed explanation of the timing process.
[0036] Phase 1 (Initial Power Rise Phase, 0~t1): At time 0, VDD begins to power on. At this time, VDD = I(R1+R2) + VGS1. The current I flowing through the loop is extremely small, and most of the voltage drops across the diode-connected NMOS transistor M1, so VGS1 ≈ VDD. Since VGS1 is recognized as high by the inverter composed of NMOS transistor M2 and PMOS transistor M3, node V2 outputs a low level. After being inverted by subsequent inverters INV1~INV4, POR outputs a high level (VDD). When VDD rises to the point where the gate-source voltage difference of NMOS transistor M4 reaches its conduction threshold at time t1, M4 turns on, connecting in parallel with resistor R2 to reduce the equivalent resistance of the loop and accelerate the rise rate of the voltage VA at node B. At this time, VDD = I*R1 + VGS1.
[0037] Phase 2 (Power Supply Rise and Hysteresis Setup Phase, t1~t2): After time t1, VDD continues to rise linearly. Since M1 operates in the saturation region, the current I flowing through M1 is proportional to the square of VGS (I∝VGS²), while VDD rises linearly, causing the rise rate of VGS to be much lower than that of VDD. As VDD increases, the difference between VDD and VGS gradually increases. When the relative difference between the power supply voltage VDD and the VGS1 of the diode-connected NMOS transistor M1 increases to the critical threshold VTHP at time t2, VGS1 is identified as low by the inverter composed of NMOS transistors M2 and M3. The inverter INV1 input is low, and after being inverted by INV1~INV4, node V1 flips from VDD to low, controlling NMOS transistor M4 to turn off. The total equivalent resistance of the loop increases, the current I decreases, and VGS1 further decreases, forming positive feedback. This positive feedback process causes the node voltage to flip rapidly. Simultaneously, after being reversed by INV2~INV3, the POR signal flips from high level to low level (0V), completing the reliable release of the reset signal.
[0038] Stable phase (after t2): After time t2, VDD stabilizes at the operating voltage, VGS1 stabilizes at a level below VTHP, the POR signal remains low, and the subsequent circuit switches from the reset state to the normal operating state.
[0039] To further explain the working principle of the hysteresis comparator of this invention, the working principle of the circuit structure composed of PMOS transistor M3 and NMOS transistor M2 is described in detail.
[0040] like Figure 3 As shown, inverter INV1 consists of a PMOS transistor M3 and an NMOS transistor M2. The source of PMOS transistor M3 is connected to the power supply voltage VDD, and its drain is connected to the drain of NMOS transistor M2, serving as the inverter's output. The gate of PMOS transistor M3 is connected to the gate of NMOS transistor M2, serving as the inverter's input (receiving the VGS1 signal). The source of NMOS transistor M2 is grounded. The figure shows the variation curves of the flip-threshold voltage of the inverter composed of PMOS transistor M3 and NMOS transistor M2 under three different size ratios. The principle of flip-threshold adjustment is further explained below.
[0041] The switching threshold VTH of inverter INV1 is determined by the size ratio of PMOS transistor M3 and NMOS transistor M2 (N = (W / L)P / (W / L)N), and its core principle is as follows:
[0042] The flip-flop threshold VTH of an inverter refers to the critical voltage at which the input voltage causes the inverter's output level to flip. For CMOS inverters, the ideal flip-flop threshold is VDD / 2, but the actual value is significantly affected by the device size.
[0043] The on-current capability of PMOS transistor M3 is proportional to its width-to-length ratio (W / L)P, while the on-current capability of NMOS transistor M2 is proportional to its width-to-length ratio (W / L)N. By adjusting the ratio of (W / L)P to (W / L)N, the switching threshold VTH of the inverter can be changed.
[0044] When it is necessary to reduce the switching threshold VTH, the width-to-length ratio (W / L)N of NMOS transistor M2 can be increased or the width-to-length ratio (W / L)P of PMOS transistor M3 can be decreased, making NMOS transistor M2 easier to turn on and PMOS transistor M3 more difficult to turn on, thus requiring a higher input voltage to make the inverter switch. Conversely, when it is necessary to reduce the switching threshold VTH, (W / L)N can be decreased or (W / L)P can be increased.
[0045] By optimizing the size ratio of M2 and M3, this invention can precisely adjust the flip threshold VTH of inverter INV1 to the target critical threshold VTHP, ensuring that the POR signal flips accurately when VGS reaches VTHP, thus achieving precise control of the reset function.
[0046] To further explain the overall working principle of the circuit, the circuit's operating characteristics under different power supply rise rates are described in detail below.
[0047] Characteristic curve description: such as Figure 4 , 5 As shown in Figure 6, the horizontal axis represents time t and the vertical axis represents voltage V. The figure shows the variation curves of VDD, VGS, and POR_OUT signals under three different power supply rise rates (v1>v2>v3), which are used to illustrate the adaptability of the circuit of the present invention under different power-on conditions.
[0048] Characteristic Analysis: When the power supply rise rate is v1 (fast power-on slew_rate = 1V / ns), VDD rises rapidly from 0V to a stable voltage. VGS, affected by the saturation region characteristics, gradually slows its rise rate, but still manages to decrease to VTHP before VDD reaches the target voltage. The POR signal flips on time, without premature or delayed triggering. When the power supply rise rate is v2 (normal power-on slew_rate = 1V / us), VDD rises linearly, and the difference between VGS and VDD increases as expected, accurately triggering the POR signal flip at time t2. The reset function is stable and reliable. When the power supply rise rate is v3 (slow power-on slew_rate = 1V / ms), although VDD rises slowly, because VGS is proportional to the square root of current I, its rise rate is even slower, still satisfying the trigger condition of "VGS eventually decreasing to VTHP." The POR signal flips normally, avoiding the reset failure problem of traditional RC delay circuits during slow power-on. Under all three operating conditions, NMOS transistor M1 can automatically adjust the equivalent resistance of the circuit according to the POR signal status, expand the hysteresis range, effectively suppress POR signal jitter caused by power supply fluctuations, and ensure the stability of the circuit under complex power-on environments.
[0049] Furthermore, to enhance the system's ability to suppress power supply noise, this invention innovatively introduces a dynamic regulated power rail generation unit. This unit includes: a PMOS switch M9, whose source is connected to the external power supply voltage VDD, and whose drain is connected to the first terminal of a filter resistor R1. The gate of M9 is connected to a clean ground level via inverters INV1 and INV2, allowing it to operate in the deep linear region, equivalent to a controlled resistor. The filter resistor R1 has its first terminal connected to the drain of M9, and its second terminal connected to the first terminal of a filter capacitor C1 and the internal regulated power rail V_steady. The filter capacitor C1 has its first terminal connected to R1 and V_steady, and its second terminal grounded to GND, forming a low-pass filter network. V_steady serves as the power supply for the internal core circuitry (including the POR module), and its voltage ripple is significantly lower than VDD. M9, R1, and C1 work together to form an active RC low-pass filter. The dynamic on-resistance of M9 is connected in series with R1, jointly setting the filter's cutoff frequency. When VDD experiences high-frequency disturbances (such as glitches), the channel resistance of M9 and C1 form a strong filtering effect, ensuring that V_steady remains stable. When VDD experiences a slow drop, the low-impedance characteristic of M9 (deep linear region) still ensures that V_steady follows VDD, avoiding false resets. Compared with the original POR circuit's cooperative working mechanism, a system-level anti-interference strategy has been added, specifically reflected in:
[0050] 1. First-stage filtering: VDD noise is first filtered out by the M9-R1-C1 network to generate clean V_steady.
[0051] 2. Secondary detection: The POR power detection module (R1, R2, M1) directly monitors V_steady instead of VDD. V_steady reflects the stable internal power state, avoiding false triggering caused by external transient interference.
[0052] 3. Three-level hysteresis: V_steady simultaneously powers the hysteresis comparator modules (M5, M6, M7, M8) to ensure comparator threshold stability and further improve noise immunity.
[0053] 4. Closed-loop regulation: The reset signal POR_OUT output by POR, in addition to controlling the subsequent circuits, is also fed back to the automatic hysteresis switch M4 to dynamically adjust the detection sensitivity, forming a closed-loop system of monitoring → filtering → comparison → feedback.
[0054] To fully explain the circuit's working mechanism, the following is a detailed explanation of the linear region operation of MOSFET M9: By setting V_bias << VDD (i.e., V_bias = GND), the gate-source voltage Vgs of M9 is always kept high, allowing it to operate in the deep linear region. At this time, the on-resistance Rdson of M9 ≈ 1 / [μp * Cox * (W / L) * (Vgs - Vthp)], exhibiting small-signal resistance characteristics. When connected in series with a fixed resistance R1, the total impedance Z_total = Rdson + R1. Filtering characteristic quantification: The -3dB bandwidth of the low-pass filter is fc = 1 / (2π * (Rdson + R1) * C1). By reasonably designing the (W / L), R1, and C1 values of M9, setting fc within the range of 1kHz to 100kHz, high-frequency switching noise (such as DC-DC ripple) and environmental EMI interference can be effectively filtered out. Drop resistance response: When VDD drops slowly, M9 maintains low resistance (Vgs - Vthp > 0), and V_steady ≈ VDD - I * Rdson. The POR module can still generate a reset signal in time by monitoring the drop in V_steady, thus avoiding system logic disorder.
[0055] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A highly stable power-on reset circuit with automatic hysteresis adjustment function, characterized in that, It includes: a power detection module, a hysteresis comparison module, a bootstrap bias unit, and an automatic hysteresis switch structure; The power supply detection module is used to monitor the rise, steady state and fluctuation of the power supply voltage in real time, and outputs the voltage detection signal to the hysteresis comparison module. The input terminal of the hysteresis comparison module receives the voltage detection signal from the power supply detection module. Its built-in reference threshold circuit can compare the voltage detection signal with the reference threshold and generate an initial reset signal based on the comparison result. The hysteresis comparison module is also coupled with an automatic hysteresis switch structure and receives a threshold adjustment signal to dynamically change the reference threshold range. The input of the automatic hysteresis switch structure is connected to both the output of the power detection module and the output of the hysteresis comparison module. The automatic hysteresis switch structure can detect the power rise rate and voltage fluctuation amplitude, and output a threshold adjustment signal to the hysteresis comparison module based on the detection results, automatically expanding or narrowing the reference threshold range of the hysteresis comparison module.
2. The high-stability power-on reset circuit with automatic hysteresis adjustment function according to claim 1, characterized in that, The power-on reset circuit also includes a dynamic regulated power rail generation unit, which can improve the system's ability to suppress power supply noise.
3. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 2, characterized in that, The dynamic regulated power rail generation unit includes a ninth MOS transistor M9, whose gate is connected to ground via a first inverter INV1 and a second inverter INV2; the source of the ninth MOS transistor M9 is connected to the output terminal of the external power supply voltage VDD, and the drain is connected to one end of the first resistor R1, serving as the internal regulated power rail V_steady.
4. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 3, characterized in that, A first capacitor C1 is also provided between the internal regulated power rail V_steady and ground.
5. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 1, 2, 3 or 4, characterized in that, The power supply detection module includes the following circuit structure: the gate and drain of the first MOSFET M1 are shorted, and the internal regulated power rail V_steady is transmitted to the gate of the first MOSFET M1 through the first resistor R1 and the second resistor R2 connected in series in sequence, so as to realize the detection of the internal regulated power rail V_steady.
6. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 1, 2, 3 or 4, characterized in that, The hysteresis comparison module can detect the gate voltage change of the first MOS transistor M1, judge and generate a reset signal based on a preset threshold, and the reset signal is sent out from the output terminal of the fourth inverter INV4.
7. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 1, 2, 3 or 4, characterized in that, The automatic hysteresis switch structure includes a fourth MOS transistor M4. The input terminal of the fourth inverter INV4D is connected to the gate of the fourth MOS transistor M4 through a third inverter INV3. The drain and source of the fourth MOS transistor M4 are connected in parallel across the two ends of a second resistor R2.
8. A highly stable power-on reset circuit with automatic hysteresis adjustment function according to claim 1, 2, 3 or 4, characterized in that, The power-on reset circuit also includes a bootstrap bias unit. One end of the bootstrap bias unit is connected to the external power supply voltage VDD, and the other end is coupled to the power detection module and the hysteresis comparison module respectively. It provides an internal reference current during the initial power-on phase to achieve self-biasing of the circuit and ensure that the power-on reset output maintains a defined logic state.