A low-power power-on reset circuit and a power-on reset method

Abstract

The application provides a low-power power-on reset circuit and a power-on reset method. The circuit comprises a bias current generating circuit, a current hysteresis comparator circuit and an anti-interference delay circuit. The bias current generating circuit is connected to the hysteresis comparator circuit, the hysteresis comparator circuit is connected to the anti-interference circuit, and the hysteresis comparator circuit is connected to the first bias current output end and the second bias current output end in the bias current generating circuit. During the chip power-on process, the required reset signal is output by controlling the generation sequence of the upper branch current and the lower branch current of the current hysteresis comparator circuit in the power-on reset circuit and judging the current size change between them. Meanwhile, the function of input voltage hysteresis detection is realized by controlling the lower branch current of the current hysteresis comparator circuit through the output feedback signal. Most of the components used in the circuit are CMOS devices, and the circuit has the characteristics of strong anti-interference ability, low cost, low power consumption and high reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a low-power power-on reset circuit and power-on reset method. Background Technology

[0002] With the development of technology, the functions of various electronic products are becoming more and more powerful, which is inseparable from the rapid development of integrated circuits. A product often integrates various types of chips, which makes the power-on process of each chip in the product system more complex. For example, the main control chip often intermittently and quickly controls the power supply system of the peripheral auxiliary chips. If the power-on process of the cooperating chips is not handled well, yield problems often occur in the reliability verification of the product, affecting the quality and user experience of the product.

[0003] Furthermore, most portable electronic products currently use lithium batteries for power. Customer applications require longer battery life, which necessitates lower power consumption for each chip in the product system. Low-power product design is already an industry consensus. However, for chip design, achieving lower power consumption while maintaining reliability often increases chip size, thus increasing the design cost per chip.

[0004] The power-on reset (POR) circuit is an essential functional module in various chip systems. Its purpose is to detect the voltage stability during the power-on and power-off processes of the chip, and then generate a POR enable signal to determine whether the chip can start or stop working. The POR enable signal can also provide a definite, stable, and reliable enable signal for other modules within the system, such as resetting inverters, registers, and latches to ensure that these circuits can function normally after each power-on.

[0005] Existing power-on reset circuit designs, in application-level situations, often exhibit upward and downward spikes under harsh power supply environments, such as those with significant power interference. Issues like rapid power-on, slow power-on, or rapid secondary or multiple power-on / off cycles can easily generate false reset signals, affecting the overall chip operation. Furthermore, the design often incorporates high-resistance resistors and large-capacitance capacitors, resulting in a larger circuit area and increased chip cost. Chinese invention patent CN112290923A discloses a low-power power-on reset circuit and method based on a bias circuit. This circuit includes a low-power bias circuit and a power-on reset circuit. During power-on, the bias current generated by the low-power bias circuit flows into it, turning on the third PMOS transistor, the fourth PMOS transistor, and the third NMOS transistor. This causes the Schmitt trigger to output a reset signal of 0. When the power-on voltage increases, the fourth NMOS transistor turns on, pulling up the rising edge delay circuit to achieve a delayed reset signal from 0 to 1. However, although this solution can achieve power-on reset, it is susceptible to voltage fluctuations, which can lead to incorrect resets. Summary of the Invention

[0006] The primary objective of this invention is to provide a low-power power-on reset circuit with stronger anti-interference capabilities.

[0007] The second objective of this invention is to provide a low-power power-on reset circuit with stronger anti-interference capabilities.

[0008] A third objective of this invention is to provide a reset method for a low-power power-on reset circuit.

[0009] The fourth objective of this invention is to provide a reset method for a low-power power-on reset circuit.

[0010] To achieve the first objective of this invention, a low-power power-on reset circuit includes a bias current generating circuit, which includes a first bias current output terminal and a second bias current output terminal; further comprising: a current hysteresis comparator circuit, the bias current generating circuit being connected to the current hysteresis comparator circuit; the current hysteresis comparator circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a first inverter; The gate of the third PMOS transistor is connected to the second bias current output terminal, the source of the third PMOS transistor is connected to the power supply terminal, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second bias current output terminal, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply terminal. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply terminal, and the drain of the fifth PMOS transistor is connected to the input terminal of the first inverter. The gates of the sixth and seventh NMOS transistors are both connected to the first bias current output terminal, the sources of the sixth and seventh NMOS transistors are both grounded, the drain of the sixth NMOS transistor is connected to the input terminal of the first inverter, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the drain of the eighth NMOS transistor is connected to the input terminal of the first inverter, and the gate of the eighth NMOS transistor is connected to the output terminal of the first inverter. The first inverter outputs a first reset signal.

[0011] As can be seen from the above scheme, the present invention controls the order of current generation in the upper and lower branches of the current hysteresis comparator circuit by controlling the fifth NMOS transistor, and the first inverter judges the change in current magnitude between them, thereby obtaining the reset signal output by the power-on reset circuit of the present invention; at the same time, the lower branch current of the current hysteresis comparator circuit is controlled by the output feedback signal to realize the function of input voltage hysteresis detection.

[0012] A further embodiment is that the bias current generating circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the second bias current output terminal. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the first bias current output terminal. The source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor is grounded.

[0013] A further solution is that the anti-interference delay circuit includes a fifth inverter; the output of the first inverter is connected to the input of the fifth inverter, and the output of the fifth inverter outputs a fourth reset signal.

[0014] Therefore, the level of the reset signal in the power-on reset circuit can be designed according to actual needs.

[0015] To achieve the second objective of this invention, a low-power power-on reset circuit is provided, comprising a bias current generating circuit, which includes a first bias current output terminal and a second bias current output terminal; further comprising: a current hysteresis comparator circuit and an anti-interference delay circuit, wherein the bias current generating circuit is connected to the current hysteresis comparator circuit, and the anti-interference delay circuit is connected to the anti-interference delay circuit; the current hysteresis comparator circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a first inverter; the anti-interference delay circuit includes a second inverter, a first capacitor, a feedback terminal, and a third inverter; The gate of the third PMOS transistor is connected to the second bias current output terminal, the source of the third PMOS transistor is connected to the power supply terminal, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second bias current output terminal, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply terminal, the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the fifth PMOS transistor is connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the input of the first inverter; the gates of the sixth and seventh NMOS transistors are both connected to the first bias current output, the sources of the sixth and seventh NMOS transistors are both grounded, the drain of the sixth NMOS transistor is connected to the input of the first inverter, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the drain of the eighth NMOS transistor is connected to the input of the first inverter, and the gate of the eighth NMOS transistor is connected to the feedback terminal of the anti-interference delay circuit; the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to ground, the first terminal of the first capacitor is connected to the input of the third inverter, and the output of the third inverter outputs the second reset signal.

[0016] As can be seen from the above scheme, the present invention controls the order of current generation in the upper and lower branches of the current hysteresis comparator circuit by controlling the fifth NMOS transistor, and the first inverter judges the change in current magnitude between them, thereby obtaining the reset signal output by the power-on reset circuit of the present invention; at the same time, the lower branch current of the current hysteresis comparator circuit is controlled by the output feedback signal to realize the function of input voltage hysteresis detection; in addition, the present invention uses the charging and discharging of the capacitor to create a delay circuit, which can replace the RC delay circuit that requires a large resistor and capacitor. At the same time, since most of the components used in the power-on reset circuit of the present invention are CMOS devices, the capacitance and resistance values ​​in the circuit are small, saving chip design area and reducing power consumption.

[0017] A further embodiment is that the second inverter includes a seventh PMOS transistor and a ninth NMOS transistor. The gate of the seventh PMOS transistor is connected to the output terminal of the first inverter, the source of the seventh PMOS transistor is connected to the power supply terminal, the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor is connected to the output terminal of the first inverter, and the source of the ninth NMOS transistor is grounded. The anti-interference delay circuit includes a sixth PMOS transistor. The source of the sixth PMOS transistor is connected to the power supply terminal, the gate of the sixth PMOS transistor is connected to the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor, and the drain of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor.

[0018] Therefore, it can be seen that the first capacitor can be charged quickly by using the second bias current.

[0019] A further embodiment is that the bias current generating circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the second bias current output terminal. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the first bias current output terminal. The source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is connected to the first terminal of the first resistor. The second terminal of the first resistor is grounded.

[0020] A further solution is that the anti-interference delay circuit includes a fourth inverter; the output of the third inverter is connected to the input of the fourth inverter, and the output of the fourth inverter outputs a third reset signal.

[0021] Therefore, the level of the reset signal in the power-on reset circuit can be designed according to actual needs.

[0022] To achieve the third object of the present invention, the present invention provides a power-on reset method applying the above low-power power-on reset circuit. After the power supply terminal is powered on, the power supply voltage VDD increases. When VDD < Vgs_N1 + Min_Vds_P1, the logic level output by the first inverter is uncertain; where Vgs_N1 is the gate-source voltage of the first NMOS transistor, and Min_Vds_P1 is the minimum drain-source voltage of the first PMOS transistor; when Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the upper-branch current flowing into the first inverter via the fifth PMOS transistor to be the target current; the first bias current output terminal outputs the first bias current, the first lower-branch current flows out of the first inverter via the sixth NMOS transistor, the first inverter outputs the first high-level signal, and the first high-level signal controls the eighth NMOS transistor to conduct, so that the second lower-branch current flows out of the first inverter via the eighth NMOS transistor and the seventh NMOS transistor; where Vgs_P2 is the gate-source voltage of the second PMOS transistor, Vgs_N5 is the gate-source voltage of the fifth NMOS transistor, and the first reset signal is the first high-level signal; the lower-branch current is equal to the sum of the first lower-branch current and the second lower-branch current; when the power supply voltage VDD > Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the second bias current output by the second bias current output terminal to be processed by the third PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor, so that the upper-branch current is greater than the lower-branch current, and the output terminal of the first inverter outputs the first low-level signal, and the first low-level signal controls the eighth NMOS transistor to cut off. At this time, the lower-branch current is only the first lower-branch current; before the power supply voltage VDD drops to the preset threshold, the output terminal of the first inverter outputs the first low-level signal. When the power supply voltage drops to the preset threshold, the output terminal of the first inverter outputs the first reset signal, and the preset threshold is less than Vgs_P2 + Vgs_N5.

[0023] As can be seen from the above solution, through the power-on reset circuit of the present invention, the change of the power supply voltage can be effectively detected. When the power supply voltage is rising, if the power supply voltage is less than the threshold Vgs_P2 + Vgs_N5, the power-on reset circuit outputs the first reset signal; once the voltage is greater than the threshold Vgs_P2 + Vgs_N5, after the delay of the anti-interference delay circuit and maintaining for a certain delay time, a level signal with a logic opposite to that of the first reset signal is output. At the same time, the detection threshold of the current hysteresis comparator circuit becomes a preset threshold smaller than Vgs_P2 + Vgs_N5; when the power supply voltage drops to the preset threshold, the reset signal outputs the first reset signal again. Thus, the power supply voltage can fluctuate within a certain range without interfering with the output of the reset signal, and the anti-interference ability is strong.

[0024] A further solution is that the anti-interference delay circuit includes a fifth inverter. The output end of the first inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter outputs a fourth reset signal.

[0025] It can be seen that the level of the reset signal can be designed according to specific actual requirements.

[0026] To achieve the fourth object of the present invention, the present invention provides a power-on reset method applying the above-mentioned low-power power-on reset circuit. After the power supply terminal is powered on, the power supply voltage VDD increases. When VDD < Vgs_N1 + Min_Vds_P1, the logic level output by the third inverter is uncertain; where Vgs_N1 is the gate-source voltage of the first NMOS transistor, and Min_Vds_P1 is the minimum drain-source voltage of the first PMOS transistor; when Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the upper branch current flowing into the first inverter via the fifth PMOS transistor to be the target current; the first bias current output terminal outputs a first bias current, the first lower branch current flows out of the first inverter via the sixth NMOS transistor, the first inverter outputs a first high-level signal, after the first high-level signal is inverted by the second inverter and then inverted by the third inverter, the output end of the third inverter outputs a second high-level signal, and the second high-level signal controls the eighth NMOS transistor to conduct through the feedback terminal, so that the second lower branch current flows out of the first inverter via the eighth NMOS transistor and the seventh NMOS transistor; where Vgs_P2 is the gate-source voltage of the second PMOS transistor, Vgs_N5 is the gate-source voltage of the fifth NMOS transistor, and the third reset signal is a low-level signal output after the second high-level signal is inverted by the fourth inverter; the lower branch current is equal to the sum of the first lower branch current and the second lower branch current; when the power supply voltage VDD > Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the second bias current output by the second bias current output terminal to be processed by the third PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor, so that the upper branch current is greater than the lower branch current, the output end of the first inverter outputs a first low-level signal, the first low-level signal is inverted by the second inverter and the third inverter, the third inverter outputs a second low-level signal, and the second low-level signal controls the eighth NMOS transistor to cut off through the feedback terminal. At this time, the lower branch current is only the first lower branch current; the second low-level signal outputs a third high-level signal via the fourth inverter; before the power supply voltage VDD drops to the preset threshold, the output end of the fourth inverter outputs a third high-level signal, and when the power supply voltage drops to the preset threshold, the output end of the fourth inverter outputs a third reset signal, and the preset threshold is less than Vgs_P2 + Vgs_N5.

[0027] As can be seen from the above scheme, the power-on reset circuit of the present invention can effectively detect changes in the power supply voltage. When the power supply voltage is rising, if the power supply voltage is less than the threshold Vgs_P2 + Vgs_N5, the power-on reset circuit outputs a third reset signal. Once the voltage exceeds the threshold Vgs_P2 + Vgs_N5, after the delay effect of the anti-interference delay circuit, it is maintained for a period of time longer, and then outputs a level signal with the logic opposite to the third reset signal. At the same time, the detection threshold of the current hysteresis comparator circuit becomes a preset threshold smaller than Vgs_P2 + Vgs_N5. When the power supply voltage drops to the preset threshold, the power-on reset circuit outputs the third reset signal. This allows the power supply voltage to fluctuate within a certain range without interfering with the output of the reset signal, resulting in strong anti-interference capability. Attached Figure Description

[0028] Figure 1 This is a circuit diagram of a low-power power-on reset circuit according to the first embodiment of the present invention.

[0029] Figure 2 This is a circuit diagram of a low-power power-on reset circuit according to the second embodiment of the present invention.

[0030] Figure 3 This is a timing diagram of the low-power power-on reset circuit of the present invention.

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0032] The power-on reset circuit of this invention generates two bias currents through a bias current generating circuit. As the voltage rises during power-on, the magnitude of the current flowing into the current hysteresis comparator circuit changes, thereby changing the level signal output by the current hysteresis comparator. The reset signal is then delayed through an anti-interference delay circuit. The feedback terminal of the anti-interference delay circuit is connected to the current hysteresis comparator circuit to achieve the voltage hysteresis function.

[0033] In this invention, the first reset signal, the second reset signal, the third reset signal, and the fourth reset signal all refer to reset signals, wherein the first reset signal and the second reset signal both refer to high-level signals, and the third reset signal and the fourth reset signal both refer to low-level signals.

[0034] In the first and second embodiments, the reset signal output by the power-on reset circuit is a low-level signal.

[0035] The names of each voltage are explained below:

[0036] VDD: Power supply voltage at the power supply terminal;

[0037] Vgs_N1: Gate-source voltage of the first NMOS transistor N1;

[0038] Min_Vds_P1: The minimum drain-source voltage of the first PMOS transistor;

[0039] Vgs_P2: Gate-source voltage of the second PMOS transistor;

[0040] Vgs_N5: Gate-source voltage of the fifth PMOS transistor;

[0041] First embodiment:

[0042] See Figure 1 The low-power power-on reset circuit of this embodiment includes a bias current generating circuit 11, a current hysteresis comparator circuit 12, and an anti-interference delay circuit 13. The bias current generating circuit 11 is connected to the current hysteresis comparator circuit 12, and the current hysteresis comparator circuit 12 is connected to the anti-interference delay circuit 13.

[0043] The bias current generating circuit 11 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2.

[0044] The sources of both the first PMOS transistor P1 and the second PMOS transistor P2 are connected to the power supply terminal, with a voltage of VDD. The gates of both PMOS transistors are connected to the second bias current output terminal. The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, and the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2. The gates of both NMOS transistors N1 and N2 are connected to the first bias current output terminal. The source of the first NMOS transistor N1 is grounded, and the source of the second NMOS transistor N2 is connected to the first end of the first resistor R1 (the end of R1 furthest from ground). The second end of the first resistor R1 is connected to ground (the end of R1 furthest from the second NMOS transistor N2). The magnitude of the second bias current can be adjusted by changing the value of the first resistor in the bias current generation circuit.

[0045] The current hysteresis comparator circuit 12 includes a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first inverter SMIT1. The first inverter SMIT1 is a Schmitt trigger inverter.

[0046] The gate of the third PMOS transistor is connected to the second bias current output terminal, the source of the third PMOS transistor is connected to the power supply terminal, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor N3, the source of the third NMOS transistor N3 is grounded, the gate of the third NMOS transistor N3 is connected to the drain of the third NMOS transistor N3, the gate of the third NMOS transistor N3 is connected to the gate of the fourth NMOS transistor N4, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor N4 is connected to the source of the fifth NMOS transistor N5, the gate of the fifth NMOS transistor N5 is connected to the second bias current output terminal, and the drain of the fifth NMOS transistor N5 is connected to the drain of the fourth PMOS transistor P4. The source of the MOSFET is connected to the power supply terminal. The gate of the fourth PMOS transistor P4 is connected to the gate of the fifth PMOS transistor P5. The source of the fifth PMOS transistor P5 is connected to the power supply terminal. The drain of the fifth PMOS transistor P5 is connected to the input terminal of the first inverter SMIT1. The sources of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are both grounded. The drain of the sixth NMOS transistor N6 is connected to the input terminal of the first inverter SMIT1. The source of the seventh NMOS transistor N7 is connected to the source of the eighth NMOS transistor N8. The drain of the eighth NMOS transistor N8 is connected to the input terminal of the first inverter SMIT1. The gate of the eighth NMOS transistor N8 is connected to the feedback terminal of the anti-interference delay circuit 13.

[0047] The anti-interference delay circuit 13 includes a second inverter, a first capacitor C1, a feedback terminal, a third inverter SMIT2, and a sixth PMOS transistor P6. The third inverter SMIT2 is a Schmitt trigger inverter.

[0048] The feedback terminal is located between the third inverter SMIT2 and the fourth inverter INV1, and is connected to the gate of the eighth NMOS transistor N8. The second inverter includes a seventh PMOS transistor P7 and a ninth NMOS transistor N9. The gate of the seventh PMOS transistor P7 is connected to the output of the first inverter SMIT1, the source of the seventh PMOS transistor P7 is connected to the power supply, and the drain of the seventh PMOS transistor P7 is connected to the drain of the ninth NMOS transistor N9. The gate of the ninth NMOS transistor N9 is connected to the output of the first inverter SMIT1, and the source of the ninth NMOS transistor N9 is grounded. The source of the sixth PMOS transistor P6 is connected to the power supply, the gate of the sixth PMOS transistor P6 is connected to the gates of the fourth PMOS transistor P4 and the fifth PMOS transistor P5, and the drain of the sixth PMOS transistor P6 is connected to the source of the seventh PMOS transistor P7.

[0049] The output terminal of the first inverter SMIT1 is connected to the input terminal of the second inverter. That is, the output terminal of the first inverter SMIT1 is connected to the gates of the seventh PMOS transistor P7 and the ninth NMOS transistor N9. The input terminal of the second inverter is the connection point of the gates of the seventh PMOS transistor P7 and the ninth NMOS transistor N9. The output terminal of the second inverter is the connection point of the drains of the seventh PMOS transistor P7 and the ninth NMOS transistor N9. The output terminal of the second inverter is connected to the first end of the first capacitor C1. The first end of the first capacitor C1 is also connected to the input terminal of the third inverter SMIT2. The second end of the first capacitor C1 is grounded. The first end of the first capacitor C1 is the end far from the ground, and the second end of the first capacitor C1 is the end far from the third inverter SMIT2. The output terminal of the third inverter is connected to the input terminal of the fourth inverter INV1. The signal output by the third inverter is inverted by the fourth inverter INV1, and the reset signal POR is output from the output terminal of the fourth inverter INV1.

[0050] The following combines Figure 3 Specifically illustrate the process and working principle of the power-on reset circuit during the power-on process.

[0051] When the power supply terminal starts to power on, VDD gradually increases. When VDD < Vgs_N1 + Min_Vds_P1, since Vgs_N1 + Min_Vds_P1 is the minimum operating voltage required for the power-on reset circuit, the bias current generation circuit 11 does not generate a bias current, and the reset signal POR output by the power-on reset circuit has an indeterminate logic output. Moreover, most of the circuits inside the general chip still cannot work at this time, so the output cannot be used as a valid reset signal at this time.

[0052] When Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5 (Vgs_P2 + Vgs_N5 corresponds to Figure 2When the VH in it), the bias current generation circuit can normally generate a bias current. Since the gates of the first NMOS transistor N1, the sixth NMOS transistor N6, and the seventh NMOS transistor N7 are all connected together, that is, connected to the first bias current output terminal, the first NMOS transistor N1, the sixth NMOS transistor N6, and the seventh NMOS transistor NN7 form a current mirror, and the currents flowing through the sixth NMOS transistor and the seventh NMOS transistor are both equal to the first bias current flowing through the first NMOS transistor N1. The first lower branch current is the current flowing through the sixth NMOS transistor N6, and the second lower branch current is the current flowing through the seventh NMOS transistor N7. Similarly, since the gates of the second PMOS transistor P2 and the third PMOS transistor P3 are connected together, that is, connected to the second bias current output terminal, the second PMOS transistor P2 and the third PMOS transistor P3 form a current mirror, and the current flowing through the third PMOS transistor P3 is equal to the second bias current of the second PMOS transistor P2. The third NMOS transistor N3 and the fourth NMOS transistor N4 form a current mirror, so that the current flowing through the third PMOS transistor P3 can be mirrored to the fourth NMOS transistor N4. Since VDD < Vgs_P2 + Vgs_N5, the gate voltage of the fifth NMOS transistor is relatively low, and the mirrored current of the fourth NMOS transistor cannot be effectively output to the fourth PMOS transistor, and thus the current flowing through the third PMOS transistor cannot fully flow into the input terminal of the first inverter SMIT1. At this time, the upper branch current flowing into the input terminal of the first inverter SMIT1 is the target current, and the target current is almost 0. The upper branch current is the current flowing through the fifth PMOS transistor P5. The lower branch current is equal to the sum of the first lower branch current and the second lower branch current. At this time, the magnitude of the lower branch current is greater than the magnitude of the upper branch current, and the downward pulling ability of the lower branch current is greater than the upward pulling ability of the upper branch current, thereby pulling down the input level of the first inverter SMIT1, causing the first inverter SMIT1 to output a first high-level signal. The first high-level signal is inverted by the inverter formed by the seventh PMOS transistor P7 and the ninth NMOS transistor N9, and then inverted by the third inverter SMIT2 to obtain a second high-level signal. The low-level third reset signal obtained by inverting the second high-level signal through the fourth inverter INV1 is the POR signal, and the POR signal can be used for resetting or setting the digital logic circuit in the VDD power supply domain. In addition, the second high-level signal is input to the gate of the eighth NMOS transistor N8 through the feedback terminal to control the eighth NMOS transistor N8 to conduct, so that the second lower branch current flows out of the first inverter SMIT1 through the seventh NMOS transistor N7 and the eighth NMOS transistor N8. It is easy to understand that when the fourth inverter INV1 is not provided, a high-level second reset signal output by the third inverter SMIT2 can be obtained.

[0053] When VDD > Vgs_P2 + Vgs_N5, the gate voltage of the fifth NMOS transistor is relatively high. This allows the second bias current at the second bias current output terminal to be processed through the current mirrors formed by the second and third PMOS transistors, the third NMOS transistor N3 and the fourth NMOS transistor N4, and the fourth and fifth PMOS transistors. This ensures that the upper branch current can flow normally into the input terminal of the first inverter SMIT1. The magnitude of the upper branch current can be adjusted by changing the channel width-to-length ratio of the two MOS transistors in the current mirrors to make it a certain multiple of the second bias current. This invention does not specifically limit this. Since the upper branch current is pre-designed to be greater than the lower branch current, it allows... The current flowing into the input terminal of the first inverter SMIT1 is greater than the current flowing out of the input terminal of the first inverter SMIT1. At this time, the output terminal of the first inverter SMIT1 outputs a first low-level signal, the seventh PMOS transistor P7 is turned on, and the ninth NMOS transistor N9 is turned off. At the same time, since the sixth PMOS transistor P6, the fourth PMOS transistor P4, and the fifth PMOS transistor P5 form a current mirror, the current flowing through the sixth PMOS transistor P6 is equal to the current flowing through the fifth PMOS transistor. The current of the sixth PMOS transistor realizes the rapid charging of capacitor C1, thereby effectively realizing the delay function. After the preset time delay, the signal output by the inverted fourth inverter INV1 is a high-level signal. Since the low-level signal output by the first inverter SMIT1 is inverted by the second inverter and the third inverter SMIT2 to become the second low-level signal, the signal flowing into the feedback terminal at this time is the second low-level signal. The eighth NMOS transistor N8 is turned off, which reduces the current in the lower branch. That is, the total current flowing out of the input terminal of the first inverter SMIT1 is reduced. This allows the current flowing into the input terminal of the first inverter SMIT1 to be reduced synchronously by a certain value while still maintaining the output of the first inverter SMIT1. This reduces the impact of voltage fluctuations on the output signal of the power-on reset circuit and improves the anti-interference capability of the power-on reset circuit.

[0054] Before the power supply voltage VDD drops to the preset threshold VL (about 100 mV lower than Vgs_P2 + Vgs_N5), the bias current generation circuit can still work normally, and the current passing through the fifth NMOS transistor can still maintain the lower branch current, and the POR signal remains at a high level signal. When VDD drops to the preset threshold VL, at this time, due to the control of the fifth NMOS transistor N5, only a weak current of the second bias current obtained from the second bias current generation terminal can pass through the fifth NMOS transistor. Therefore, the magnitude of the upper branch current flowing into the first inverter SMIT1 is almost zero, and the lower branch current is greater than the upper branch current, pulling down the input level of the first inverter SMIT1. The output terminal of the first inverter SMIT1 outputs a first high-level signal, and the reset signal output by the output terminal of the fourth inverter INV1 is a low-level signal. Thus, before VDD drops to 0, other digital logic circuits inside the chip still have enough time to be reset or set, restoring to the original state when the chip is powered on for the first time. In this way, in the next power supply voltage cycle, the chip repeats the above power-on process timing, ensuring the consistency and reliability of the chip.

[0055] Second Embodiment:

[0056] See Figure 2 , the low-power power-on reset circuit of this embodiment includes a bias current generation circuit 11 and a current hysteresis comparator circuit 12. The difference from the first embodiment is that, except for not setting an anti-interference delay circuit and the gate of the eighth NMOS transistor not being connected to the output terminal of the first inverter, the bias current generation circuit 11 and the current hysteresis comparator circuit 12 are both set the same as in the first embodiment.

[0057] In addition, the output terminal of the first inverter SMIT1 is also connected to a fifth inverter INV2.

[0058] Combined with Figure 3 , when the power supply terminal starts to power on, VDD gradually increases. When VDD < Vgs_N1 + Min_Vds_P1, similar to the first embodiment, the reset signal POR output by the power-on reset circuit has an uncertain logic and cannot be used as an effective reset signal.

[0059] When Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5 (Vgs_P2 + Vgs_N5 corresponds to Figure 2When VH is in the first embodiment, the magnitude of the upper branch current is the same as in the first embodiment, and the magnitude of the lower branch current is also the same as in the first embodiment. The magnitude of the upper branch current is less than that of the lower branch current, and the pull-down capability of the lower branch current is greater than that of the upper branch current. This causes the output terminal of the first inverter SMIT1 to output a first high-level signal. The first high-level signal is fed back to the gate of the eighth NMOS transistor, causing the eighth NMOS transistor to conduct. This allows the second lower branch current to flow out from the first inverter SMIT1 through the seventh NMOS transistor N7 and the eighth NMOS transistor N8. The first high-level signal passes through the fifth inverter INV2, thus outputting a fourth reset signal as a low-level signal. It is easy to understand that if the fifth inverter INV2 is not set, the first high-level reset signal can be obtained from the output of the first inverter SMIT1.

[0060] When VDD > Vgs_P2 + Vgs_N5, as in the first embodiment, since the gate voltage of the fifth NMOS transistor is higher, the current of the fourth NMOS transistor can flow normally through the fourth PMOS transistor, so that the current flowing into the input terminal of the first inverter SMIT1 is greater than the current flowing out of the input terminal of the first inverter SMIT1. The output terminal of the first inverter SMIT1 outputs a first low-level signal, and the first low-level signal is input to the fifth inverter SMIT2, so that the output POR signal of the fifth inverter is a high-level signal. Meanwhile, since the first low-level signal output by the first inverter SMIT1 is fed back to the gate of the eighth NMOS transistor, the eighth NMOS transistor is turned off, which prevents the second lower branch current from flowing through the eighth NMOS transistor. This reduces the lower branch current, that is, the total current flowing out of the input terminal of the first inverter SMIT1 is reduced. This allows the current flowing into the input terminal of the first inverter SMIT1 to be reduced synchronously by a certain value while still maintaining the output of the first inverter SMIT1. This reduces the impact of voltage fluctuations on the output signal of the power-on reset circuit and improves the anti-interference capability of the power-on reset circuit.

[0061] Before the power supply voltage VDD drops to the preset threshold VL (approximately 100mV less than Vgs_P2 + Vgs_N5), the bias current generation circuit can still operate normally, and the current through the fifth NMOS transistor can still maintain the lower branch current, allowing the fifth inverter INV2 to maintain a high-level signal output. When VDD drops to the preset threshold VL, due to the control of the fifth NMOS transistor N5, only a weak current from the second bias current generation terminal can pass through the fifth NMOS transistor. Therefore, the upper branch current flowing into the first inverter SMIT1 is almost zero, and the lower branch current is greater than the upper branch current. The output terminal of the first inverter SMIT1 outputs a first high-level signal, thereby the reset signal POR at the output terminal of the fifth inverter INV2 is a low-level signal. Therefore, before VDD drops to 0, the other digital logic circuits inside the chip still have enough time to reset or set, restoring the chip to its original state when it was first powered on. In this way, the chip repeats the above power-on process timing in the next power supply voltage cycle, ensuring the consistency and reliability of the chip.

[0062] In summary, the power-on reset circuit of this invention includes a bias current generation circuit, a current hysteresis comparator circuit, and an anti-interference delay circuit. The bias current generation circuit is connected to the hysteresis comparator circuit, which is connected to the anti-interference circuit. The hysteresis comparator circuit is connected to the first bias current output terminal and the second bias current output terminal in the bias current generation circuit. During the chip power-on process, by controlling the order of the generation of the upper and lower branch currents of the current hysteresis comparator in the power-on reset circuit and judging the change in current magnitude between them, the required reset signal is output. At the same time, the lower branch current of the current hysteresis comparator circuit is controlled by the output feedback signal to realize the function of input voltage hysteresis detection. In addition, most of the components used in the circuit of this invention are CMOS devices, which can realize a power-on reset circuit with strong anti-interference ability, low cost, low power consumption, and high reliability.

[0063] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power power-on reset circuit, comprising a bias current generating circuit, wherein the bias current generating circuit includes a first bias current output terminal and a second bias current output terminal; Its features are, Also includes: A current hysteresis comparator circuit, wherein the bias current generating circuit is connected to the current hysteresis comparator circuit; The current hysteresis comparator circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a first inverter; The gate of the third PMOS transistor is connected to the second bias current output terminal, the source of the third PMOS transistor is connected to the power supply terminal, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second bias current output terminal, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply terminal. The gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply terminal, and the drain of the fifth PMOS transistor is connected to the input terminal of the first inverter. The gates of the sixth NMOS transistor and the seventh NMOS transistor are both connected to the first bias current output terminal, the sources of the sixth NMOS transistor and the seventh NMOS transistor are both grounded, the drain of the sixth NMOS transistor is connected to the input terminal of the first inverter, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the drain of the eighth NMOS transistor is connected to the input terminal of the first inverter, and the gate of the eighth NMOS transistor is connected to the output terminal of the first inverter. The first inverter outputs a first reset signal. The fifth NMOS transistor controls the order in which the upper and lower branch currents of the current hysteresis comparator circuit are generated, and determines the change in current magnitude between the upper and lower branch currents, thereby outputting the first reset signal.

2. The low-power power-on reset circuit as described in claim 1, characterized in that: The bias current generating circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the second bias current output terminal. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the first bias current output terminal. The source of the first NMOS transistor is grounded, and the source of the second NMOS transistor is connected to the first terminal of a first resistor. The second terminal of the first resistor is grounded.

3. A low-power power-on reset circuit as described in claim 1 or 2, characterized in that... It also includes a fifth inverter; The output terminal of the first inverter is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter outputs a fourth reset signal.

4. A low-power power-on reset circuit, comprising a bias current generating circuit, wherein the bias current generating circuit includes a first bias current output terminal and a second bias current output terminal; Its features are, Also includes: The circuit includes a current hysteresis comparator circuit and an anti-interference delay circuit. The bias current generating circuit is connected to the current hysteresis comparator circuit, and the anti-interference delay circuit is connected to the anti-interference delay circuit. The current hysteresis comparator circuit includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a first inverter; the anti-interference delay circuit includes a second inverter, a first capacitor, a feedback terminal, and a third inverter. The gate of the third PMOS transistor is connected to the second bias current output terminal, the source of the third PMOS transistor is connected to the power supply terminal, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fourth NMOS transistor is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the second bias current output terminal, the drain of the fifth NMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the power supply terminal, the gate of the fourth PMOS transistor is connected to the gate of the fifth PMOS transistor, and the source of the fifth PMOS transistor is connected to the power supply terminal. The drain of the fifth PMOS transistor is connected to the input terminal of the first inverter; the gates of the sixth and seventh NMOS transistors are both connected to the first bias current output terminal, the sources of the sixth and seventh NMOS transistors are both grounded, the drain of the sixth NMOS transistor is connected to the input terminal of the first inverter, the source of the seventh NMOS transistor is connected to the source of the eighth NMOS transistor, the drain of the eighth NMOS transistor is connected to the input terminal of the first inverter, and the gate of the eighth NMOS transistor is connected to the feedback terminal of the anti-interference delay circuit; the output terminal of the first inverter is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is connected to ground, the first terminal of the first capacitor is connected to the input terminal of the third inverter, and the output terminal of the third inverter outputs a second reset signal; The fifth NMOS transistor controls the order in which the upper and lower branch currents of the current hysteresis comparator circuit are generated, and determines the change in the magnitude of the current between the upper and lower branch currents, thereby outputting the second reset signal.

5. A low-power power-on reset circuit as described in claim 4, characterized in that: The second inverter includes a seventh PMOS transistor and a ninth NMOS transistor. The gate of the seventh PMOS transistor is connected to the output terminal of the first inverter, the source of the seventh PMOS transistor is connected to the power supply terminal, the drain of the seventh PMOS transistor is connected to the drain of the ninth NMOS transistor, the gate of the ninth NMOS transistor is connected to the output terminal of the first inverter, and the source of the ninth NMOS transistor is grounded. The anti-interference delay circuit includes a sixth PMOS transistor, the source of which is connected to the power supply terminal, the gate of which is connected to the gate of the fourth PMOS transistor and the gate of the fifth PMOS transistor, and the drain of which is connected to the source of the seventh PMOS transistor.

6. A low-power power-on reset circuit as described in claim 4 or 5, characterized in that: The bias current generation circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both connected to the power supply terminal. The gates of the first PMOS transistor and the second PMOS transistor are both connected to the second bias current output terminal. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are both connected to the first bias current output terminal. The source of the first NMOS transistor is grounded. The source of the second NMOS transistor is connected to the first end of a first resistor, and the second end of the first resistor is grounded.

7. The low-power power-on reset circuit according to claim 6, wherein: The anti-interference delay circuit includes a fourth inverter; The output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the fourth inverter outputs a third reset signal.

8. The power-on reset method applying the low-power power-on reset circuit according to claim 2, wherein: After the power supply terminal is powered on, the power supply voltage VDD increases. When VDD < Vgs_N1 + Min_Vds_P1, the logic level output by the first inverter is uncertain; where Vgs_N1 is the gate-source voltage of the first NMOS transistor, and Min_Vds_P1 is the minimum drain-source voltage of the first PMOS transistor; When Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the upper branch current flowing into the first inverter via the fifth PMOS transistor to be the target current; the first bias current output terminal outputs a first bias current, and a first lower branch current flows out of the first inverter via the sixth NMOS transistor. The first inverter outputs a first high-level signal, and the first high-level signal controls the eighth NMOS transistor to conduct, so that a second lower branch current flows out of the first inverter via the eighth NMOS transistor and the seventh NMOS transistor; where Vgs_P2 is the gate-source voltage of the second PMOS transistor, Vgs_N5 is the gate-source voltage of the fifth NMOS transistor, and the first reset signal is the first high-level signal; the lower branch current is equal to the sum of the first lower branch current and the second lower branch current; When the power supply voltage VDD > Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the second bias current output from the second bias current output terminal to pass through the third PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor for processing, so that the upper branch current is greater than the lower branch current. The output terminal of the first inverter outputs a first low-level signal, and the first low-level signal controls the eighth NMOS transistor to cut off. At this time, the lower branch current is only the first lower branch current; Before the power supply voltage VDD drops to the preset threshold, the output terminal of the first inverter outputs the first low-level signal. After the power supply voltage drops to the preset threshold, the output terminal of the first inverter outputs the first reset signal, and the preset threshold is less than Vgs_P2 + Vgs_N5.

9. The power-on reset method of the low-power power-on reset circuit according to claim 7 above, characterized in that: After the power supply terminal is powered on, the power supply voltage VDD increases. When VDD < Vgs_N1 + Min_Vds_P1, the logic level output by the third inverter is uncertain; where Vgs_N1 is the gate-source voltage of the first NMOS transistor, and Min_Vds_P1 is the minimum drain-source voltage of the first PMOS transistor; When Vgs_N1 + Min_Vds_P1 < VDD < Vgs_P2 + Vgs_N5, the fifth NMOS transistor controls the upper branch current flowing into the first inverter via the fifth PMOS transistor to be the target current; the first bias current output terminal outputs a first bias current, and the first lower branch current flows out of the first inverter via the sixth NMOS transistor. The first inverter outputs a first high-level signal. After the first high-level signal is inverted by the second inverter and then inverted by the third inverter, the output terminal of the third inverter outputs a second high-level signal. The second high-level signal controls the eighth NMOS transistor to conduct through the feedback terminal, so that the second lower branch current flows out of the first inverter via the eighth NMOS transistor and the seventh NMOS transistor; where Vgs_P2 is the gate-source voltage of the second PMOS transistor, Vgs_N5 is the gate-source voltage of the fifth NMOS transistor, and the third reset signal is the low-level signal output after the second high-level signal is inverted by the fourth inverter; the lower branch current is equal to the sum of the first lower branch current and the second lower branch current; When the power supply voltage VDD > Vgs_P2 + Vgs_N5, the second bias current output from the second bias current output terminal controlled by the fifth NMOS transistor is processed by the third PMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor, making the upper branch current greater than the lower branch current. The output terminal of the first inverter outputs a first low-level signal, which is inverted by the second and third inverters. The third inverter outputs a second low-level signal, which controls the eighth NMOS transistor to be turned off through the feedback terminal. At this time, the lower branch current is only the first lower branch current. The second low-level signal outputs a third high-level signal through the fourth inverter. Before the power supply voltage VDD drops to a preset threshold, the output terminal of the fourth inverter outputs the third high-level signal. After the power supply voltage drops to the preset threshold, the output terminal of the fourth inverter outputs the third reset signal. The preset threshold is less than Vgs_P2+Vgs_N5.

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