Power-on reset circuit, control method, driver chip, device and storage medium

Abstract

This application discloses a power-on reset circuit, control method, driver chip, device, and storage medium. The circuit includes: a first detection module and a power supply judgment logic module. The first input terminal of the first detection module is connected to the medium-voltage power supply of the driver chip, the second input terminal is connected to the low-voltage power supply of the driver chip, and the output terminal is connected to the first input terminal of the power supply judgment logic module. The second input terminal of the power supply judgment logic module is connected to the low-voltage power supply. The first detection module is used to determine an output level indicating whether the medium-voltage power supply has completed power-on based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply. The power supply judgment logic module is used to determine an enable signal indicating whether both the medium-voltage power supply and the low-voltage power supply have completed power-on based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and in particular to a power-on reset circuit, control method, driver chip, device, and storage medium. Background Technology

[0002] Liquid Crystal Displays (LCDs) are powered by an external Power Management Integrated Circuit (PMIC). This includes a high-voltage power supply AVDD (e.g., 18V) and a medium-voltage power supply HVDD (e.g., 9V) for the analog circuitry, and a low-voltage power supply DVDD (e.g., 3.3V) for the digital circuitry. Only when all three power supplies from the PMIC are powered on can the LCD driver circuit transmit data normally. However, in some technologies, the lack of a Power Response (POR) circuit for detecting the HVDD power supply can lead to abnormal display problems caused by HVDD not being fully powered on. Summary of the Invention

[0003] In view of this, embodiments of this application provide at least one power-on reset circuit, control method, driver chip, device, and storage medium.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] On one hand, embodiments of this application provide a power-on reset circuit, the power-on reset circuit comprising:

[0006] First detection module, power supply judgment logic module;

[0007] The first input terminal of the first detection module is connected to the medium-voltage power supply of the driver chip, the second input terminal is connected to the low-voltage power supply of the driver chip, and the output terminal is connected to the first input terminal of the power judgment logic module; the second input terminal of the power judgment logic module is connected to the low-voltage power supply.

[0008] The first detection module is used to determine, based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply, the output level that characterizes whether the medium-voltage power supply has been powered on.

[0009] The power supply judgment logic module is used to determine an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

[0010] On the other hand, embodiments of this application provide a control method for a power-on reset circuit, applied to the aforementioned power-on reset circuit, the method comprising:

[0011] The first detection module in the power-on reset circuit determines the output level characterizing whether the medium-voltage power supply has completed power-on based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply.

[0012] The power supply judgment logic module of the power-on reset circuit determines an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

[0013] In another aspect, embodiments of this application provide a driver chip, the driver chip including: a power supply for the driver chip and the power-on reset circuit described above.

[0014] In another aspect, embodiments of this application provide an electronic device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0015] In another aspect, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0016] In another aspect, embodiments of this application provide a computer program including computer-readable code, wherein when the computer-readable code is run in a computer device, a processor in the computer device performs some or all of the steps for implementing the above-described method.

[0017] In another aspect, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method.

[0018] This application provides a power-on reset circuit, which includes a first detection module and a power supply judgment logic module. The first detection module is connected to the medium-voltage power supply of the driver chip through a first input terminal and to the low-voltage power supply of the driver chip through a second input terminal. Thus, the first detection module compares the current voltage value of the low-voltage power supply with the current voltage value of the medium-voltage power supply to accurately and quickly determine whether the medium-voltage power supply has been fully powered on. Furthermore, the output terminal of the first detection module is connected to the first input terminal of the power supply judgment logic module, and the second input terminal of the power supply judgment logic module is connected to the low-voltage power supply. Thus, the power supply judgment logic module accurately analyzes whether both the medium-voltage and low-voltage power supplies have been fully powered on by comparing the detected current voltage value of the low-voltage power supply with the output level of the first detection module. Therefore, this power-on reset circuit can detect whether each power supply in the driver chip has been fully powered on, thereby reducing abnormal display caused by incomplete power supply power-on.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0021] Figure 1 A schematic diagram of the power-on reset circuit provided in the embodiments of this application;

[0022] Figure 2A This is a schematic diagram of another component structure of the power-on reset circuit provided in the embodiments of this application;

[0023] Figure 2B This is another schematic diagram of the power-on reset circuit provided in the embodiments of this application;

[0024] Figure 2C This is a schematic diagram of another component structure of the power-on reset circuit provided in the embodiments of this application;

[0025] Figure 3 A schematic diagram illustrating the implementation flow of a control method for a power-on reset circuit provided in an embodiment of this application;

[0026] Figure 4 A schematic diagram of the power-on reset circuit provided in the embodiments of this application;

[0027] Figure 5 A timing diagram showing the power-on status of the PMIC provided in an embodiment of this application;

[0028] Figure 6Another timing diagram showing the power-on status of the PMIC provided in an embodiment of this application;

[0029] Figure 7 Another timing diagram showing the power-on status of the PMIC provided in the embodiments of this application;

[0030] Figure 8 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0033] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0035] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0036] 1) The Power-On Reset (POR) circuit ensures that analog and digital modules are initialized to a known state after power is applied. The basic POR function generates an internal reset pulse to avoid race conditions and keeps the device static until the power supply voltage reaches a threshold voltage that guarantees normal operation. Note that this threshold voltage differs from the minimum power supply voltage given in the datasheet. Once the power supply voltage reaches the threshold voltage, the POR circuit releases the internal reset signal, and the state machine begins initializing the device. Before initialization is complete, the device should ignore external signals, including transmitted data. The only exception is the reset pin (if present), which is internally selected using the POR signal. The POR circuit can be represented as a window comparison circuit; the comparator level VT2 is defined during circuit design and depends on the device's operating voltage and process size.

[0037] 2) The integrated circuit (IC) industry continues to drive the development of the smartphone industry. Touch and display driver integration (TDDI) brings a unified system architecture. The original system architecture, because the display and touch chips were separate, could lead to some display noise. TDDI, however, achieves unified control, resulting in better noise management. TDDI uses a "time-division scanning" method, dividing one frame of display time into two parts: one part for touch scanning and the other for display scanning, without interference, fundamentally reducing the risk of signal interference.

[0038] 3) Liquid Crystal Display (LCD) is a flat, ultra-thin display device composed of a certain number of color or monochrome pixels, placed in front of a light source or reflector. LCDs consume very little power and are suitable for battery-powered electronic devices. The main principle is that an electric current stimulates liquid crystal molecules to produce dots, lines, and surfaces, which, in conjunction with a backlight, form an image.

[0039] The power-on reset circuit provided in this application embodiment has a first detection module that compares the current voltage values ​​of the low-voltage and medium-voltage power supplies to accurately and quickly determine whether the medium-voltage power supply has completed power-on. This power-on reset circuit can detect whether each power supply in the driver chip has completed power-on, thereby resolving abnormal display problems caused by incomplete power-on. The power-on reset circuit provided in this application embodiment can be integrated into the chip of an electronic device, which can be a laptop, tablet, desktop computer, set-top box, mobile device (e.g., mobile phone, portable music player, personal digital assistant, dedicated messaging device, portable gaming device), or a server. The server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms.

[0040] Figure 1 This is a schematic diagram of the power-on reset circuit provided in the embodiments of this application, combined with... Figure 1 The following description is provided: The power-on reset circuit includes: a first detection module 101 and a power judgment logic module 102;

[0041] The first input terminal of the first detection module is connected to the medium-voltage power supply of the driver chip, the second input terminal is connected to the low-voltage power supply of the driver chip, and the output terminal is connected to the first input terminal of the power judgment logic module; the second input terminal of the power judgment logic module is connected to the low-voltage power supply.

[0042] Here, the first detection module includes two input terminals: a first input terminal and a second input terminal. The first input terminal is a positive input terminal, and the second input terminal is a negative input terminal. The first input terminal is connected to the medium-voltage power supply of the driver chip. This medium-voltage power supply can be either already powered on or not. This medium-voltage power supply is an analog medium-voltage power supply (HVDD) provided by an external power management integrated circuit. In a specific example, the voltage value of this medium-voltage power supply after power-on can be 9 volts (V). The second input terminal is connected to the low-voltage power supply of the driver chip. This low-voltage power supply can also be either already powered on or not. This low-voltage power supply is a data circuit low-voltage power supply (DVDD) provided by an external power management integrated circuit. In a specific example, the voltage value of this low-voltage power supply after power-on can be 3.3V. The output of the first detection module is connected to the first input of the power supply judgment logic module, so that the output of the first detection module can be used as the input of the first input of the power supply judgment logic module. In this way, the power supply judgment logic module can accurately determine whether the medium voltage power supply and the low voltage power supply have been powered on by inputting the output of the first detection module and the low voltage power supply.

[0043] The first detection module 101 is used to determine whether the medium-voltage power supply has been powered on, based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply.

[0044] In some embodiments, the current voltage value of the low-voltage power supply is the voltage value detected by the low-voltage power supply at the current moment in the power-on reset circuit. This current voltage value can be less than or equal to the voltage value when the low-voltage power supply completes power-on (i.e., the current voltage value can be less than or equal to the low-voltage standard value of the low-voltage power supply, using the voltage value when the low-voltage power supply completes power-on as the low-voltage standard value). For example, if the voltage value when the low-voltage power supply completes power-on is 3.3V, the current voltage value can be 0V if the low-voltage power supply is not powered on, and greater than 0V and less than or equal to 3.3V if the low-voltage power supply is in the process of powering on. Similarly, the current voltage value of the medium-voltage power supply is less than or equal to the voltage value when the medium-voltage power supply completes power-on (i.e., the current voltage value of the medium-voltage power supply can be less than or equal to the medium-voltage standard value of the medium-voltage power supply).

[0045] In some possible implementations, assuming the high-voltage power supply has been powered on, the current voltage value of the low-voltage power supply is compared with the current voltage value of the medium-voltage power supply, and the power supply's power-on status is determined based on the comparison result. For example, if the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply, then the medium-voltage power supply is considered to have been powered on.

[0046] The power supply judgment logic module 102 is used to determine an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

[0047] In some embodiments, the output level of the first detection module is used as the input of the power supply judgment logic module. This output level serves as the gate voltage of the transistor in the power supply judgment logic module that determines whether the medium-voltage power supply has completed power-on, thereby controlling the on / off state of these transistors. The current voltage value of the low-voltage power supply is used as the gate voltage of the transistor in the power supply judgment logic module that determines whether the low-voltage power supply has completed power-on, controlling the on / off state of these transistors. Then, an enable signal is generated and output based on the on / off states of the transistors controlled by the input level and the transistors controlled by the low-voltage power supply. The high or low level of this enable signal determines whether both the medium-voltage and low-voltage power supplies have completed power-on.

[0048] In some possible implementations, if the output level of the first detection module is low, and / or the current voltage value of the low-voltage power supply is less than the voltage value when the low-voltage power supply completes power-on, then the enable signal is low, and it is determined that at least one of the medium-voltage power supply and the low-voltage power supply has not completed power-on; if the output level of the first detection module is high, and the current voltage value of the low-voltage power supply is the voltage value when the low-voltage power supply completes power-on, then the enable signal is high, and it is determined that both the medium-voltage power supply and the low-voltage power supply have completed power-on.

[0049] In this embodiment, the first input terminal of the first detection module is connected to the medium-voltage power supply of the driver chip, and the second input terminal is connected to the low-voltage power supply of the driver chip. Thus, the first detection module compares the current voltage values ​​of the low-voltage and medium-voltage power supplies to accurately and quickly determine whether the medium-voltage power supply has been fully powered on. Furthermore, the output terminal of the first detection module is connected to the first input terminal of the power supply judgment logic module, and the second input terminal of the power supply judgment logic module is connected to the low-voltage power supply. Thus, the power supply judgment logic module accurately analyzes whether both the medium-voltage and low-voltage power supplies have been fully powered on by detecting the current voltage value of the low-voltage power supply and the output level of the first detection module. Therefore, this power-on reset circuit can detect whether each power supply in the driver chip has been fully powered on, thereby reducing abnormal display caused by incomplete power supply power-on.

[0050] In some embodiments, provided that the high-voltage power supply has been powered on, the first detection module determines whether the medium-voltage power supply has been powered on by comparing the voltage values ​​of the low-voltage power supply and the detected medium-voltage power supply. That is, the first detection module 101 also includes a third input terminal, such as... Figure 2AAs shown, the third input terminal of the first detection module 101 is connected to the high-voltage power supply of the driver chip;

[0051] The first detection module 101 is further configured to, when the high-voltage power supply is powered on, compare the current voltage value of the low-voltage power supply with the current voltage value of the medium-voltage power supply to obtain a comparison result; and determine the output level based on the comparison result.

[0052] In some possible implementations, the first detection module 101 can be implemented using a comparator. The current voltage value of the low-voltage power supply is used as the negative input of the comparator, and the current voltage value of the medium-voltage power supply is used as the positive input. By comparing the current voltage values ​​of the two power supplies, it is determined whether the current voltage value of the medium-voltage power supply is greater than that of the low-voltage power supply, thus obtaining the comparison result. If the current voltage value of the medium-voltage power supply is greater than that of the low-voltage power supply, the output level is high, indicating that the medium-voltage power supply has been powered on, but it cannot be determined whether the low-voltage power supply has been powered on. If the current voltage value of the medium-voltage power supply is less than that of the low-voltage power supply, the output level is low, indicating that the medium-voltage power supply has not been powered on, and it still cannot be determined whether the low-voltage power supply has been powered on. In this case, the first detection module can continue to compare the current voltage values ​​of the two power supplies until the current voltage value of the medium-voltage power supply is greater than that of the low-voltage power supply. Then, a high level is output to the power supply judgment logic module, confirming that the medium-voltage power supply has been powered on. In this way, by using the low-voltage power supply as a reference voltage and comparing the reference voltage with the current voltage value of the medium-voltage power supply, the high or low level of the output can accurately determine whether the medium-voltage power supply has been fully powered on, thereby solving the problem of abnormal display caused by the driver chip not being fully powered on due to HVDD.

[0053] In some embodiments, the first detection module 101 is further configured to determine that the output level is high when the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply.

[0054] In some embodiments, a high output level indicates that the medium-voltage power supply has been successfully powered on. In the first detection module 101, the current voltage value of the low-voltage power supply is used as a reference voltage. If the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply, it indicates that the detected current voltage value of the medium-voltage power supply is relatively large, thus indicating that the medium-voltage power supply has been successfully powered on. Therefore, a high output level from the first detection module indicates that the medium-voltage power supply has been successfully powered on. If the current voltage value of the medium-voltage power supply is smaller than the current voltage value of the low-voltage power supply, it indicates that the detected current voltage value of the medium-voltage power supply is relatively small, thus indicating that the medium-voltage power supply has not been successfully powered on. Therefore, the first detection module can accurately determine whether the medium-voltage power supply has been successfully powered on. However, a high or low output level from the first detection module does not necessarily indicate whether the low-voltage power supply has been successfully powered on.

[0055] In some possible implementations, a second detection module (not shown) is incorporated into the power-on reset circuit to independently detect the power-on status of the low-voltage power supply. The input of this second detection module is connected to the low-voltage power supply, and its output is connected to the driver chip. The second detection module is used to determine, based on a preset voltage value and the current voltage value of the low-voltage power supply, and output a signal to the driver chip indicating whether the low-voltage power supply has completed power-on.

[0056] Here, the preset voltage value is set based on the low-voltage standard value of the low-voltage power supply. This preset voltage value can be set as a certain percentage of the low-voltage standard value. For example, 70% of the low-voltage standard value can be set as the preset voltage value. In the second detection module, the preset voltage value is compared with the current voltage value of the low-voltage power supply to determine whether the low-voltage power supply has completed power-on. If the current voltage value of the low-voltage power supply is greater than or equal to the preset voltage value, the low-voltage power supply is determined to have completed power-on; if the current voltage value is less than the preset voltage value, the low-voltage power supply has not completed power-on. In this way, the second detection module in the power-on reset circuit can quickly detect the low-voltage power supply that has completed power-on, thus facilitating the first detection module to determine whether the medium-voltage power supply has completed power-on using this low-voltage power supply as a reference voltage.

[0057] The power supply judgment logic module 102 is further configured to determine, based on the high level and the current voltage value of the low-voltage power supply, the enable signal that can characterize whether the low-voltage power supply has been powered on.

[0058] In some embodiments, the first detection module outputs a high-level signal to the power supply judgment logic module 102, so that the power supply judgment logic module 102 can control the conduction of the transistor in the module whose gate voltage is the high-level signal through the high-level signal. For example... Figure 4As shown in (b), when HVDD_DET is high, transistors NM4, NM5, and NM6 are all turned on. Conversely, by checking whether the transistors are turned on, the user can determine whether the output level of the first detection module is high, and thus determine whether the medium-voltage power supply has been powered on. The current voltage value of the low-voltage power supply controls the conduction of transistors NM1, NM2, and NM3. If the current voltage value of the low-voltage power supply is high, then NM1, NM2, and NM3 are turned on. Thus, when NM1, NM2, NM3, NM4, NM5, and NM6 are all turned on, transistors NM7 and NM8 are turned off, making the enable terminal Enable high. Conversely, when the power supply judgment logic module 102 outputs a high level, it can be determined that both the low-voltage and high-voltage power supplies have been powered on. Thus, in the first detection module, if the medium-voltage power supply is greater than the low-voltage power supply, a high level is output to the power supply judgment logic module so that the power supply judgment logic module can further determine whether the low-voltage power supply has been powered on, thereby ensuring that both the low-voltage power supply and the medium-voltage power supply have been powered on.

[0059] In some embodiments, assuming the high-voltage power supply has been powered on, if the comparison result of the first detection module is low, the comparison of the two power supplies continues until a high level is output to the power supply judgment logic module. Thus, the first detection module can determine whether the medium-voltage power supply has been powered on. Then, the power supply judgment logic module further confirms whether both power supplies have been powered on. Specifically, the first detection module 101 is also used to, if the current voltage value of the medium-voltage power supply is less than the current voltage value of the low-voltage power supply, continue comparing the current voltage value of the low-voltage power supply with the current voltage value of the medium-voltage power supply until the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply, and then generate and output a high level.

[0060] Here, regardless of whether the low-voltage power supply has completed power-on, it can be used as a reference voltage. By comparing the current voltage value of the medium-voltage power supply with that of the low-voltage power supply, it is determined whether the medium-voltage power supply has completed power-on. If the current voltage value of the medium-voltage power supply is less than that of the low-voltage power supply, it means that the medium-voltage power supply has not yet completed power-on. The current voltage values ​​of the two power supplies are then monitored and compared until the current voltage value of the medium-voltage power supply is greater than that of the low-voltage power supply. In this case, the medium-voltage power supply has completed power-on, and a high-level signal is output to the power supply judgment logic module 102.

[0061] The power supply judgment logic module 102 is further configured to determine and output an enable signal with a high level based on the low voltage standard value and the high level when the current voltage value of the low voltage power supply is a low voltage standard value.

[0062] Here, if the current voltage value of the low-voltage power supply is the low-voltage standard value, it indicates that the low-voltage power supply has completed power-on. Then, the power supply judgment logic module 102, based on the input low-voltage standard value and the high-level output from the first detection module, enables... Figure 4 In (b), transistors NM1, NM2, NM3, NM4, NM5, and NM6 are all turned on, while transistors NM7 and NM8 are turned off, and the enable signal is high, indicating that both the medium-voltage and low-voltage power supplies have been powered on.

[0063] In this embodiment, in the power-on sequence of multiple power supplies provided by the power management integrated circuit, regardless of whether the low-voltage power supply completes power-on earlier than the medium-voltage power supply, if the low-voltage power supply completes power-on earlier than the medium-voltage power supply, then the first detection module can determine whether the medium-voltage power supply has completed power-on. Furthermore, the power supply judgment logic module outputs a high-level enable signal to further confirm that both the medium-voltage and high-voltage power supplies have completed power-on, thereby enabling more accurate detection of whether both the medium-voltage and low-voltage power supplies have completed power-on.

[0064] In some embodiments, the power supply determination logic module 102 can... Figure 2B The illustrated structure includes a power supply judgment logic module 102 comprising: a low-voltage identification submodule 21, a medium-voltage identification submodule 22, a voltage change sensing submodule 23, a shunt submodule 24, and an enable terminal 25. Wherein:

[0065] The first terminal of the low-voltage identification submodule is connected to a low-voltage power supply. The second terminal of the low-voltage identification submodule is connected to the first terminal of the shunt submodule. The third terminal of the low-voltage identification submodule is connected to the second terminal of the shunt submodule. The third terminal of the shunt submodule is connected to the first terminal and the enable terminal of the voltage change sensing submodule. The fourth terminal of the shunt submodule is connected to the second terminal of the voltage change sensing submodule. The third terminal of the voltage change sensing submodule is connected to the third terminal of the medium-voltage identification submodule and grounded. The fourth terminal of the voltage change sensing submodule is connected to the second terminal of the low-voltage identification submodule. The second terminal of the medium-voltage identification submodule is connected to the fourth terminal of the low-voltage identification submodule. The first terminal of the medium-voltage identification submodule is connected to the output level of the first detection module.

[0066] Here, the low-voltage identification submodule 21 can... Figure 4(b) is implemented using transistors NM1, NM2, and NM3. The medium-voltage identification submodule 22 can be implemented using transistors NM4, NM5, and NM6, and the voltage change sensing submodule 23 can be implemented using transistors NM7 and NM8. The second terminal of the low-voltage identification submodule is connected to the fourth terminal of the voltage change sensing submodule; for example, the PWR_DET output from the second terminal of the low-voltage identification submodule is connected to the fourth terminal of the voltage change sensing submodule via a wire. The shunt submodule 25 can be implemented using transistors PM1, PM2, PM3, PM4, and PM5. Thus, the first terminal of the low-voltage identification submodule is the gate of transistor NM1, the second terminal is the drain of transistor NM1, the third terminal may include the drains of transistors NM2 and NM3, and the fourth terminal includes the sources of transistors NM1, NM2, and NM3. The PWR_DET output from the drain of NM1 is connected to the fourth terminal of the voltage change sensing submodule via a wire. The first terminal of the medium-voltage identification submodule is the gate of transistor NM4. The second terminal includes the drains of transistors NM4, NM5, and NM6, which are connected to the sources of transistors NM1, NM2, and NM3, respectively. The third terminal includes the sources of transistors NM4, NM5, and NM6 and is grounded. The first terminal of the voltage change sensing submodule is the drain of NM8, which is connected to the enable terminal. The second terminal is the drain of transistor NM7. The third terminal is the source of transistors NM7 and NM8. The fourth terminal is the gate of transistors NM7 and NM8. The second terminal of the low-voltage identification submodule is connected to the drain of transistor PM1 and the gates of transistors NM7 and NM8. The first end of the shunt submodule is the drain and gate of transistor PM1, the second end is the port connecting the drain and gate of transistor PM4 and the gate of transistor PM3, the port connecting the source of transistor PM4 and the drain of transistor PM2, the third end is the port connecting the drain of transistor PM3 and the source of transistor PM5, and the fourth end is the port connecting the drain and gate of transistor PM5 and the gate of transistor PM2.

[0067] The low-voltage identification submodule 21 is used to identify the level state of the low-voltage power supply and determine the on / off state of the low-voltage identification submodule based on the level state of the low-voltage power supply.

[0068] Here, the low-voltage identification submodule 21 uses three transistors to identify the voltage level of the low-voltage power supply and controls its on / off state according to this voltage level. The voltage level of the low-voltage power supply is affected by its power-on status. If the low-voltage power supply is powered on, its voltage level is high; if it is not powered on, its voltage level is low. When the low-voltage power supply is at a low level, the low-voltage identification submodule is off; when it is at a high level, the low-voltage identification submodule is on.

[0069] The medium-voltage identification submodule 22 is used to identify the output level of the first detection module and determine the on / off state of the medium-voltage identification submodule based on the output level of the first detection module.

[0070] Here, the structure of the medium-voltage identification submodule 22 is similar to that of the low-voltage identification submodule 21, also implemented using three transistors. The on / off state of the medium-voltage identification submodule is controlled according to the voltage level of the medium-voltage power supply. The voltage level of the medium-voltage power supply is affected by the power-on status of the low-voltage power supply. If the medium-voltage power supply is powered on, its voltage level is high; if it is not powered on, its voltage level is low. When the medium-voltage power supply is low, the medium-voltage identification submodule is off; when the medium-voltage power supply is high, the medium-voltage identification submodule is on.

[0071] The current shunt submodule 24 is used to shunt the current generated under the high voltage power supply; and based on the on / off state of the low voltage identification submodule and the on / off state of the medium voltage identification submodule, to determine the detection voltage at the first end of the current shunt submodule, and to output the detection voltage to the voltage change sensing submodule.

[0072] Here, the on / off state of the first terminal of the shunt submodule is controlled by the on / off state of the low-voltage identification submodule and the medium-voltage identification submodule; the first terminal of this shunt submodule can be implemented using a P-type transistor, such as... Figure 4As shown in (b), the first terminal of the shunt submodule can be the gate and drain of transistor PM1. Since the gate and drain of transistor PM1 are shorted, transistor PM1 acts like a resistor, shunting current in the circuit. If at least one of the low-voltage identification submodule and the medium-voltage identification submodule is off, the drain of transistor PM1 cannot be pulled low to ground. Furthermore, since the source of transistor PM1 is connected to the high-voltage power supply AVDD, the drain of transistor PM1 can provide a high level for the detection voltage at the first terminal of the shunt submodule, resulting in a high-level detection voltage output to the voltage change sensing submodule. If both the low-voltage identification submodule and the medium-voltage identification submodule are on, the drain of transistor PM1 can be pulled low to ground, providing a low level for the detection voltage at the first terminal of the shunt submodule, resulting in a low-level detection voltage output to the voltage change sensing submodule. Thus, the detection voltage at the first terminal of the shunt submodule can indicate whether at least one of the medium-voltage or low-voltage power supplies has not been powered on.

[0073] In some embodiments, the splitter submodule 24 can... Figure 4 (b) is implemented by transistors PM1, PM2, PM3, PM4, and PM5; wherein the gate of transistor PM1 is connected to the drain and the second terminal of the low-voltage identification submodule, and the source is connected to the high-voltage power supply.

[0074] The source of transistor PM2 is connected to the high-voltage power supply, the drain is connected to the source of transistor PM4 and the drain of transistor NM2 in the low-voltage identification submodule, and the gate is connected to the gate of transistor PM5.

[0075] The source of transistor PM3 is connected to the high-voltage power supply, the drain is connected to the enable terminal and the source of transistor PM5, and the gate is connected to the gate of transistor PM4.

[0076] The gate of transistor PM4 is connected to the drain and the third terminal of the low-voltage identification submodule.

[0077] The drain of transistor PM5 is connected to the gate and the second terminal of the voltage change sensing submodule, respectively.

[0078] Transistors PM1, PM4, and PM5 are used to limit the current flowing through transistors PM2 and PM3 when they are in the on state.

[0079] Here, with transistors PM1, PM4, and PM5 all conducting, since transistors PM1, PM4, and PM2, as well as PM3 and PM5, are connected in parallel, transistor PM1 can shunt the current generated by the high-voltage power supply AVDD. Transistor PM4 is connected in series with PM2, so it can limit the current flowing through PM2 from the current generated by the high-voltage power supply AVDD, preventing it from becoming excessive. Similarly, since transistor PM5 is connected in series with PM3, it can limit the current flowing through PM3 from the current generated by the high-voltage power supply AVDD, preventing it from becoming excessive.

[0080] Transistors PM2 and PM3 are used to perform voltage conversion between the medium-voltage and low-voltage power supplies that have already been powered on.

[0081] Here, transistors PM2 and PM3, in their on-state, convert the already powered medium-voltage and low-voltage power supplies into a high-voltage power supply. For example, as... Figure 4 As shown in (b), when the low-voltage DVDD is powered on but the medium-voltage HVDD is not, transistors NM1, NM2, and NM3 are turned on, while transistors NM4, NM5, and NM6 are turned off. Because the detection voltage output of the logic detection signal PER_DET is high, transistors NM7 and NM8 are turned on, thereby turning on transistors PM2 and PM5. Since transistor NM3 is turned on and transistor NM6 is turned off, the drain of transistor NM3 is at a high level, causing transistors PM3 and PM4 to turn off. Thus, transistor PM2, in its on state, can perform voltage conversion on the powered-on low-voltage DVDD.

[0082] Transistors PM3 and PM5 are used to control the enable signal based on its on / off state.

[0083] Here, since the drain of transistor PM3 and the source of transistor PM5 are connected to the enable terminal, the on / off state of transistors PM3 and PM5 affects the level of the enable signal. For example, if the low-voltage power supply DVDD is powered on but the medium-voltage power supply HVDD is not powered on, transistor PM5 is turned on, so the source of transistor PM5 is at a low level. Transistor PM3 is turned off, so the drain of transistor PM3 is at a low level. Therefore, transistors PM3 and PM5 provide a low level to the enable terminal, and the level of the enable signal is low, indicating that at least one of the high-voltage and low-voltage power supplies has not been powered on.

[0084] The voltage change sensing submodule 23 is used to determine the on / off state based on the detected voltage.

[0085] Here, the voltage change sensing submodule 23 can be implemented using two transistors, and the detected voltage is used as the gate voltage of these two transistors to control their on / off state. For example, if the detected voltage is high, the voltage change sensing submodule 23 is turned on; if the detected voltage is low, the voltage change sensing submodule 23 is turned off.

[0086] Enable terminal 25 is used to determine the enable signal based on the on / off state of the voltage change sensing submodule and the level state of the third terminal of the shunt submodule.

[0087] Here, the on / off state of the voltage change sensing submodule controls the voltage level of its first terminal. For example, if the voltage change sensing submodule is on and its third terminal is grounded, the first terminal is at a low level; if the voltage change sensing submodule is off, its first terminal is at a high level. In some possible implementations, if the voltage change sensing submodule is on, a low level is provided to the enable terminal; and the on / off state of the voltage change sensing submodule indicates that the detected voltage is high, which is then controlled by... Figure 4 (b) It is known that transistors PM2 and PM5 in the shunt submodule are turned on, while transistors PM3 and PM4 are turned off. Therefore, the third terminal of the shunt submodule, i.e., the drain of transistor PM3 and the source of transistor PM5, is at a low level. Consequently, the enable terminal is also supplied with a low level signal; thus, the enable signal is a low-level signal. This low-level enable signal confirms that at least one of the medium-voltage and low-voltage power supplies has not been fully powered on. If the voltage change sensing submodule is turned off, a high level is provided to the enable terminal; and the turn-on of the voltage change sensing submodule indicates that the detected voltage is low. Figure 4 (b) It can be seen that transistors PM2 and PM5 in the shunt submodule are disconnected, while transistors PM3 and PM4 are turned on. Thus, the third terminal of the shunt submodule, i.e., the drain of transistor PM3 and the source of transistor PM5, is at a high level. Therefore, the enable terminal is also at a high level, and the enable signal is a high-level signal. Thus, the high-level enable signal can be used to determine that both the medium-voltage power supply and the low-voltage power supply have been powered on.

[0088] In this embodiment, by setting a low-voltage identification submodule, a medium-voltage identification submodule, a voltage change sensing submodule, a shunt submodule, and an enable terminal in the power supply judgment logic module, the voltage levels of the low-voltage and high-voltage power supplies can be analyzed by each submodule to determine the level state of the enable signal. Then, based on the level state of the enable signal, it can accurately determine whether the medium-voltage and low-voltage power supplies have been fully powered on, so that the driver chip can transmit data normally and reduce data transmission errors caused when working when the medium-voltage power supply has not been fully powered on.

[0089] In some embodiments, the voltage change sensing submodule 23 can be implemented using a first sensing transistor and a second sensing transistor, such as... Figure 2C As shown, where:

[0090] The gate of the first sensing transistor 231 is connected to the gate of the second sensing transistor 232 and the second terminal of the low-voltage identification submodule, respectively. The drain of the first sensing transistor is connected to the fourth terminal of the shunt submodule, so as to control the on / off state of the fourth terminal of the shunt submodule by the drain voltage of the first transistor.

[0091] Here, the first sensing transistor and the second sensing transistor can be through... Figure 4 The implementation of transistors NM7 and NM8 in (b).

[0092] The source of the first sensing transistor and the source of the second sensing transistor are both grounded; the drain of the second sensing transistor is connected to the enable terminal so as to control the enable signal of the enable terminal by the drain voltage of the second sensing transistor.

[0093] Here, if the detected voltage is high, then the first and second sensing transistors are turned on; that is, if at least one of the medium-voltage and low-voltage power supplies has not been fully powered on, the first and second sensing transistors are turned on. If the detected voltage is low, then the first and second sensing transistors are turned off; that is, if both the medium-voltage and low-voltage power supplies have been fully powered on, the first and second sensing transistors are turned off. Thus, a voltage change sensing submodule is implemented using two transistors. By sensing changes in the high-voltage and low-voltage power supplies, the high and low levels of the enable signal output from the enable terminal can be easily and accurately controlled, thereby indicating whether both the high-voltage and low-voltage power supplies have been fully powered on.

[0094] In some possible implementations, the on / off state of the low-voltage identification submodule 21 can be determined by the detected low-voltage power supply level. Specifically, the low-voltage identification submodule 21 is further configured to enter a disconnected state when the detected low-voltage power supply level is low, and to enter a conducting state when the detected low-voltage power supply level is high. Thus, the low-voltage power supply level can be reflected in the on / off state of the low-voltage identification submodule. This facilitates further control of the on / off states of the shunt submodule and the voltage change sensing submodule based on the low-voltage identification submodule's level, thereby affecting the level of the enable signal. Consequently, the low-voltage power supply level is indirectly reflected in the enable signal, allowing the determination of whether the low-voltage power supply has been powered on.

[0095] In some embodiments, both the low-voltage identification submodule and the medium-voltage identification submodule can be implemented using multiple transistors, so as to control the on / off state of the multiple transistors in the low-voltage identification submodule 21 and the medium-voltage identification submodule 22 respectively by the level state of the low-voltage power supply and the output level of the first detection module. That is, the low-voltage identification submodule 21 includes: multiple first transistors; the medium-voltage identification submodule 22 includes: multiple second transistors.

[0096] Here, the sources of the plurality of first transistors are connected one-to-one with the drains of the plurality of second transistors; the gates of the plurality of first transistors are connected to the low-voltage power supply, and their drains are respectively connected to the multiple terminals of the shunt submodule; the gates of the plurality of second transistors are connected to the output level of the first detection module, and their sources are grounded.

[0097] In this way, a low-voltage identification submodule is implemented by multiple first transistors, and a medium-voltage identification submodule is implemented by the same number of second transistors. The sources of the multiple first transistors are connected one-to-one with the sources of the multiple second transistors. If the multiple first transistors and / or the multiple second transistors are not turned on, the second terminal of the shunt submodule connected to the multiple first transistors will not be grounded, so that the detection voltage output from the second terminal of the low-voltage identification submodule (i.e., the output voltage from the first terminal of the shunt submodule) is high. This provides a high-level gate voltage for the two sensing transistors in the voltage change sensing submodule 23 to turn on the two sensing transistors. Since the sources of the two sensing transistors are grounded, the enable signal of the enable terminal is low. Thus, it can be determined that at least one of the medium-voltage power supply and the low-voltage power supply has not been powered on. When multiple first transistors or multiple second transistors are all turned on, the second terminal of the low-voltage identification submodule connected to the multiple first transistors is grounded, resulting in a low-level detection voltage output from the second terminal of the low-voltage identification submodule. This provides a low-level gate voltage to the two sensing transistors in the voltage change sensing submodule 23, causing these two sensing transistors to turn off. Consequently, the enable signal at the enable terminal becomes high, thus confirming that both the medium-voltage and low-voltage power supplies have been powered on. In this way, by setting multiple transistors in the low-voltage and high-voltage identification submodules, the enable signal at the enable terminal can be indirectly controlled, facilitating accurate determination of whether both the medium-voltage and low-voltage power supplies have been powered on.

[0098] This application provides a control method for a power-on reset circuit, applied to the power-on reset circuit in the above embodiments, such as... Figure 3 As shown, combined with Figure 3 The steps shown are explained below:

[0099] Step S301: The first detection module in the power-on reset circuit determines the output level characterizing whether the medium-voltage power supply has been powered on, based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply of the driver chip.

[0100] In some embodiments, in the power-on reset circuit, the current voltage value of the low-voltage power supply of the driver chip and the current voltage value of the medium-voltage power supply are compared by controlling the first detection module, and the power-on status of the medium-voltage power supply can be determined according to the comparison result.

[0101] Step S302: The power supply judgment logic module of the power-on reset circuit determines an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

[0102] In some embodiments, by inputting the current voltage value of the low-voltage power supply and the output level of the first detection module into the power supply judgment logic module, the on / off state of each component in the power supply judgment logic module can be controlled, thereby affecting the level state of the enable signal. Then, the level state of the enable signal can be used to determine whether both the medium-voltage power supply and the low-voltage power supply have been powered on.

[0103] In this embodiment, a first detection module compares the current voltage values ​​of the low-voltage power supply and the medium-voltage power supply to accurately and quickly determine whether the medium-voltage power supply has been fully powered on. Furthermore, the output of the first detection module is connected to the first input of the power supply judgment logic module, and the second input of the power supply judgment logic module is connected to the low-voltage power supply. Thus, the power supply judgment logic module can accurately analyze whether both the medium-voltage and low-voltage power supplies have been fully powered on by comparing the detected current voltage value of the low-voltage power supply with the output level of the first detection module. This allows for the detection of whether each power supply in the driver chip has been fully powered on, thereby reducing abnormal display caused by incomplete power supply power-on.

[0104] The following describes the application of the power-on reset circuit provided in the embodiments of this application in a real-world scenario, taking the multi-power-supply power-on reset circuit applied to an LCD source driver chip as an example.

[0105] The purpose of Power-On Reset (POR) is to initialize the digital logic circuit, thereby enabling the chip to perform the designed actions. The LCD driver circuit is a mixed-signal chip with multiple power supplies, and the LCD's power supply is provided by an external power management integrated circuit. Related technologies lack circuits for detecting the power-on of multiple power supplies, only detecting the power-on actions of DVDD and AVDD, while ignoring the power-on detection of HVDD. However, in some LCD applications, after DVDD and AVDD are powered on, HVDD is still in a floating state. At this time, POR considers the power-on complete and exits control. However, at this time, HVDD generates an additional voltage through the chip's internal AVDD, affecting the external PMIC's power-on action on HVDD, which may cause the chip to malfunction. Based on this, this application provides a power-on reset circuit with multiple power supply detection. This detection circuit has a simple structure and can simultaneously monitor three power supplies, supporting different power-on sequences, thereby protecting the stable and reliable operation of the LCD driver circuit. Figure 4 As shown, Figure 4 This is a schematic diagram of the power-on reset circuit provided in an embodiment of this application. The power-on reset circuit includes an HVDD detection circuit 401 and a power supply judgment logic circuit 402. The circuit structure of the HVDD detection circuit 401 is as follows: Figure 4 As shown in (a), the HVDD detection circuit is used to detect whether the HVDD voltage has been successfully applied. The detection principle relies on... Figure 4 The comparator shown in (a) uses DVDD as its reference voltage. When the voltage of HVDD is less than that of DVDD, HVDD_DET outputs a low level, and there is no voltage on HVDD. As the voltage of HVDD gradually increases and becomes greater than that of DVDD, HVDD_DET changes from a low level to a high level, thus indicating that HVDD has been powered on.

[0106] The circuit structure of the power supply detection logic circuit 402 is as follows: Figure 4 As shown in (b), the power supply judgment logic circuit 402 is used to determine whether all power supplies have been powered on. If either HVDD or DVDD has not been powered on, the detection voltage PWR_DET output by the logic detection signal is high, and Enable outputs a low level. The POR circuit determines that power-on is not yet complete. If both HVDD and DVDD have been powered on, the logic judgment circuit PWR_DET outputs a low level, and Enable outputs a high level, indicating that all power supplies have been powered on. Under these conditions, the LCD driver circuit can begin transmitting data.

[0107] For PMIC, the HVDD voltage is also generated by AVDD as the power supply. Therefore, when the PMIC is powered on, the power-on time of HVDD always follows or delays AVDD. However, for DVDD, the power-on time is random. Therefore, the power-on sequence of the LCD can be determined by... Figure 5 , Figure 6 and Figure 7 The three timing sequences shown have essentially the same on / off state of the POR circuit when the power is off as when it is on. In this embodiment, the power supply is analyzed in detail under different timing sequences when it is on.

[0108] Figure 5 The timing diagram for the power-up of the PMIC provided in this embodiment shows that DVDD is powered on first, followed by AVDD, and finally HVDD. After DVDD is powered on, it serves as the reference voltage for the HVDD detection circuit, and the logic detection signal indicates that DVDD power-up is complete. The HVDD detection circuit can determine the HVDD power-up status; when HVDD is greater than the DVDD voltage, the Enable output goes high, and the chip enters normal operation.

[0109] Figure 6 Another timing diagram of the PMIC power-on situation provided in this application embodiment shows that the DVDD power-on time is between AVDD and HVDD, and the DVDD power-on is earlier than HVDD. In this case, the DVDD can still be used as a reference voltage and can be compared with HVDD. Figure 5 The principle is basically the same. When HVDD is greater than DVDD voltage, Enable outputs a high level, and POR ends its operation.

[0110] Scenario 1: If the PMIC's power-on status is as follows... Figure 5 Or as shown in Figure 6, that is, both DVDD and AVDD have completed power-on, but HVDD has not. At this time, the second detection module has already detected that DVDD has completed power-on. Figure 4 In (a), the HVDD detection circuit uses DVDD as the reference voltage and compares DVDD and HVDD. When HVDD is greater than the DVDD voltage, the HVDD_DET output of the HVDD detection circuit is high.

[0111] exist Figure 4In (b), since DVDD is powered on, the gates of transistors NM1, NM2, and NM3 are at a high level, and the gate-source voltage difference is greater than the conduction threshold, so transistors NM1, NM2, and NM3 are turned on. However, since HVDD is not powered on, the gates of transistors NM4, NM5, and NM6 are at a low level, and the gate-source voltage difference is less than the conduction threshold, so transistors NM4, NM5, and NM6 are turned off. The gate and drain of transistor PM1 are shorted to form a shunt resistor, which shunts the current generated under the AVDD voltage in the power-on reset circuit, so that the current flowing through transistors PM2 and PM3 in this circuit is not too large. The input of the logic detection signal PER_DET is connected between the drains of transistors PM1 and NM1. When transistors PM1 and NM1 are on and transistor NM4 is off, since the source of transistor PM1 is connected to AVDD, PER_DET outputs a high level, which is then supplied to the gates of transistors NM7 and NM8, turning them on. Since the gates of transistors PM2 and PM5 are connected to the drain of transistor NM7, the drain voltage of transistor NM7 is equal to its source voltage, and the source of transistor NM7 is grounded, causing the gates of transistors PM2 and PM5 to be low, meaning transistors PM2 and PM5 are on. Because the drain of transistor NM3 provides the gate voltage for transistors PM3 and PM4, when transistor NM3 is on and transistor NM6 is off, the drain of transistor NM3 is high, turning off transistors PM3 and PM4.

[0112] The enable pin is connected to the drain of transistor PM3 and the source of transistor PM5. Since transistor PM5 is turned on and transistor PM3 is turned off, a low level is provided to enable. At the same time, the drain of transistor NM8 also provides a low level to enable, so enable outputs a low level. Conversely, when the driver chip receives a low level output from enable, it can determine that at least one of the medium-voltage power supply and the low-voltage power supply has not been powered on.

[0113] Figure 7 This is another timing diagram of the PMIC power-on status provided in the embodiments of this application. The DVDD is powered on last, and HVDD is powered on earlier than the DVDD. The HVDD voltage is always greater than that of the DVDD. The output of the HVDD detection circuit follows the high level of HVDD. The HVDD power-on is complete, but it is impossible to determine whether the DVDD power-on is complete. At this time, the state of the POR circuit is determined by the power supply judgment logic circuit. When the DVDD is powered on, the Enable circuit will output a high voltage only after reaching the turn-on voltage of transistors NM1, NM2, and NM3. At this time, all power supplies are fully powered on.

[0114] Scenario 2: If the PMIC's power-on status is as follows... Figure 7 As shown, AVDD and HVDD have both completed power-on, while DVDD has not. Therefore, in... Figure 4 In (a), HVDD is compared with DVDD. Since HVDD powers on earlier than DVDD, the HVDD voltage is always greater than that of DVDD. Therefore, the output of the HVDD detection circuit follows the high level of HVDD and can determine whether HVDD has completed power-on, but it cannot determine whether DVDD has completed power-on. And through... Figure 4 (b) Determine whether the DVDD has been powered on.

[0115] exist Figure 4 In (b), since DVDD is not fully powered on, the gates of transistors NM1, NM2, and NM3 are at a low level, so transistors NM1, NM2, and NM3 are off. However, since HVDD is fully powered on, the gates of transistors NM4, NM5, and NM6 are at a high level, so transistors NM4, NM5, and NM6 are on. The gate and drain of transistor PM1 are shorted to form a shunt resistor, which shunts the current generated under the AVDD voltage in the power-on reset circuit, preventing the current flowing through transistors PM2 and PM3 from becoming excessive. The input of the logic detection signal PER_DET is connected between the drain of transistor PM1 and the drain of transistor NM1. When transistors PM1 and NM4 are on and transistor NM1 is off, since the source of transistor PM1 is connected to AVDD, PER_DET outputs a high level. Transistors NM7 and NM8 are in the same state as in case one, entering the on state. Based on scenario one, transistors PM2 and PM5 are turned on, while transistors PM3 and 4 are turned off. The Enable output is low, indicating that the low-voltage power supply has not been fully powered on.

[0116] Scenario 3: If AVDD, HVDD, and DVDD are all powered on, transistors NM1, NM2, NM3, NM4, NM5, and NM6 are all turned on. Transistor PM1 is turned on, shunting the current generated by the AVDD voltage in the power-on reset circuit to prevent excessive current flowing through transistors PM2 and PM3 in this circuit. The input of the logic detection signal PER_DET is connected between the drain of transistor PM1 and the drain of transistor NM1. When transistors PM1 and NM1 are turned on, and transistor NM4 is also turned on, since the source of transistor NM4 is grounded, it pulls the drain voltage of transistor NM1 low, causing PER_DET to output a low level. This low level is then provided to the gates of transistors NM7 and NM8, causing them to turn off. Since the gates of transistors PM2 and PM5 are connected to the drain of transistor NM7, transistor NM7 is turned off, causing transistors PM2 and PM5 to turn off. Since the drain of transistor NM3 provides the gate voltage for transistors PM3 and 4, when transistor NM3 is on and transistor NM6 is on, the drain of transistor NM3 is at a low level, causing transistors PM3 and 4 to be on.

[0117] The enable pin is connected to the drain of transistor PM3 and the source of transistor PM5. Since transistor PM5 is off and transistor PM3 is on, and the source of transistor PM3 is connected to AVDD, it provides a high level to enable. At the same time, the drain of transistor NM8 also provides a high level to enable, so enable outputs a high level. Conversely, when the driver chip receives a high level output from enable, it can determine that both the medium voltage power supply and the low voltage power supply have been powered on.

[0118] In other embodiments, the power supply detected by the logic detection signal PER_DET is two (DVDD & HVDD). If there are other power supplies in the circuit, this can be extended to multiple power supply detections to achieve power-on detection and reset functions for more power supplies.

[0119] In this embodiment, by simultaneously detecting the power-on reset circuit of multiple power supplies, power-on completion detection can be performed according to the different power-on sequences of the power supplies in the LCD application.

[0120] Based on the foregoing embodiments, this application provides an electrostatic discharge protection device, which includes various units and modules included in each unit, and can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0121] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. In some embodiments, the functions or modules included in the device provided in this disclosure can be used to perform the methods described in the above method embodiments. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0122] It should be noted that, in the embodiments of this application, if the above-described backlight control method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0123] This application provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0124] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0125] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0126] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0127] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0128] It should be noted that, Figure 8 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this application, such as... Figure 8 As shown, the hardware entity of the computer device 800 includes: a processor 801, a communication interface 802, and a memory 803, wherein:

[0129] Processor 801 typically controls the overall operation of computer device 800.

[0130] The communication interface 802 enables computer devices to communicate with other terminals or servers over a network.

[0131] The memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 801 and various modules in the computer device 800. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 801, the communication interface 802, and the memory 803 can be performed via bus 804.

[0132] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0135] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0136] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0137] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0138] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0139] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A power-on reset circuit, characterized in that, The power-on reset circuit includes: a first detection module and a power supply judgment logic module; The first input terminal of the first detection module is connected to the medium-voltage power supply of the driver chip, the second input terminal is connected to the low-voltage power supply of the driver chip, and the output terminal is connected to the first input terminal of the power judgment logic module; the second input terminal of the power judgment logic module is connected to the low-voltage power supply. The first detection module is used to determine, based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply, the output level that characterizes whether the medium-voltage power supply has been powered on. The power supply judgment logic module is used to determine an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

2. The power-on reset circuit according to claim 1, characterized in that, The first detection module also includes a third input terminal, which is connected to the high-voltage power supply of the driver chip. The first detection module is further configured to, when the high-voltage power supply is powered on, compare the current voltage value of the low-voltage power supply with the current voltage value of the medium-voltage power supply to obtain a comparison result; and determine the output level based on the comparison result.

3. The power-on reset circuit according to claim 1 or 2, characterized in that, The first detection module is further configured to determine that the output level is high when the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply; wherein the high level indicates that the medium-voltage power supply has been powered on. The power supply judgment logic module is further configured to determine, based on the high level and the current voltage value of the low-voltage power supply, the enable signal that can characterize whether the low-voltage power supply has been powered on.

4. The power-on reset circuit according to claim 1 or 2, characterized in that, The first detection module is further configured to, when the current voltage value of the medium-voltage power supply is less than the current voltage value of the low-voltage power supply, continue to compare the current voltage value of the low-voltage power supply with the current voltage value of the medium-voltage power supply until the current voltage value of the medium-voltage power supply is greater than the current voltage value of the low-voltage power supply, and generate and output a high level. The power supply judgment logic module is further configured to determine and output an enable signal with a high level based on the low-voltage standard value and the high level when the current voltage value of the low-voltage power supply is the low-voltage standard value; wherein the high-level enable signal indicates that both the medium-voltage power supply and the low-voltage power supply have been powered on.

5. The power-on reset circuit according to claim 4, characterized in that, The power-on reset circuit further includes: a second detection module, the input of which is connected to the low-voltage power supply and the output of which is connected to the driver chip; The second detection module is used to determine and output an output signal to the driver chip, based on a preset voltage value and the current voltage value of the low-voltage power supply, whether the low-voltage power supply has been powered on.

6. The power-on reset circuit according to claim 2, characterized in that, The power supply judgment logic module includes: a low voltage identification submodule, a medium voltage identification submodule, a voltage change sensing submodule, a shunt submodule, and an enable terminal; The first terminal of the low-voltage identification submodule is connected to the low-voltage power supply; the second terminal of the low-voltage identification submodule is connected to the first terminal of the shunt submodule; the third terminal of the low-voltage identification submodule is connected to the second terminal of the shunt submodule; the third terminal of the shunt submodule is connected to the first terminal of the voltage change sensing submodule and the enable terminal, respectively; the fourth terminal of the shunt submodule is connected to the second terminal of the voltage change sensing submodule; the third terminal of the voltage change sensing submodule is connected to the third terminal of the medium-voltage identification submodule and grounded; the fourth terminal of the voltage change sensing submodule is connected to the second terminal of the low-voltage identification submodule; the second terminal of the medium-voltage identification submodule is connected to the fourth terminal of the low-voltage identification submodule; and the first terminal of the medium-voltage identification submodule is connected to the output level of the first detection module. The low-voltage identification submodule is used to identify the level state of the low-voltage power supply and determine the on / off state of the low-voltage identification submodule based on the level state of the low-voltage power supply. The medium-voltage identification submodule is used to identify the output level of the first detection module and determine the on / off state of the medium-voltage identification submodule based on the output level of the first detection module. The current shunt submodule is used to shunt the current generated under the high voltage power supply; and based on the on / off state of the low voltage identification submodule and the on / off state of the medium voltage identification submodule, to determine the detection voltage at the first terminal of the current shunt submodule, and to output the detection voltage to the voltage change sensing submodule. The voltage change sensing submodule is used to determine the on / off state based on the detected voltage; The enable terminal is used to determine the enable signal based on the on / off state of the voltage change sensing submodule and the level state of the third terminal of the shunt submodule.

7. The power-on reset circuit according to claim 6, characterized in that, The voltage change sensing submodule includes: a first sensing transistor and a second sensing transistor; wherein: The gate of the first sensing transistor is connected to the gate of the second sensing transistor, the first terminal of the shunt submodule, and the second terminal of the low-voltage identification submodule, respectively, and the drain of the first sensing transistor is connected to the fourth terminal of the shunt submodule. The source of the first sensing transistor and the source of the second sensing transistor are both grounded; the drain of the second sensing transistor is connected to the enable terminal so as to control the enable signal of the enable terminal by the drain voltage of the second sensing transistor.

8. The power-on reset circuit according to claim 6, characterized in that, The low-voltage identification submodule is further configured to enter a disconnect state when the low-voltage power supply level is detected to be low, and to enter a conduction state when the low-voltage power supply level is detected to be high.

9. The power-on reset circuit according to claim 6, characterized in that, The low-voltage identification submodule includes: a plurality of first transistors; the medium-voltage identification submodule includes: a plurality of second transistors; wherein, the sources of the plurality of first transistors are connected to the drains of the plurality of second transistors in a one-to-one correspondence; the gates of the plurality of first transistors are connected to the low-voltage power supply, and the drains are respectively connected to the multiple terminals of the shunt submodule; the gates of the plurality of second transistors are connected to the output level of the first detection module, and the sources are grounded.

10. A control method for a power-on reset circuit, characterized in that, The method, applied to the power-on reset circuit of any one of claims 1 to 9, comprises: The first detection module in the power-on reset circuit determines the output level characterizing whether the medium-voltage power supply has completed power-on based on the current voltage value of the low-voltage power supply and the current voltage value of the medium-voltage power supply. The power supply judgment logic module of the power-on reset circuit determines an enable signal that indicates whether both the medium-voltage power supply and the low-voltage power supply have been powered on, based on the current voltage value of the low-voltage power supply and the output level of the first detection module.

11. A driver chip, characterized in that, The driver chip includes: a power supply for the driver chip and a power-on reset circuit as described in any one of claims 1 to 9.

12. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method of claim 10.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 10.

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