A circuit for controlling MCU reset and intelligent door lock

Abstract

The application aims at the technical problem of reset failure of low-power MCU caused by incomplete power discharge, and provides a circuit for controlling MCU reset and an intelligent door lock. The circuit is applied to a system comprising a microcontroller, a watchdog unit, a first and a second power conversion unit and a fast discharge unit. The first power conversion unit supplies power to the microcontroller, and the second power conversion unit independently supplies power to the watchdog unit. When the microcontroller is abnormal, the watchdog unit outputs a reset signal, turns off the first power conversion unit to cut off the power supply of the microcontroller, and controls the fast discharge unit to be turned on, so that the residual charge of the microcontroller power supply is consumed through a low-resistance channel composed of a discharge switch tube and a discharge resistor. During the discharging period, the second power conversion unit continuously supplies power to the watchdog unit to ensure that the reset signal maintains an effective state. It can be seen that the circuit realizes fast and complete discharge of the residual charge of the microcontroller power supply, eliminates residual voltage interference, and ensures the effectiveness of the subsequent power-on reset pulse.

Description

Technical Field

[0001] This invention relates to the field of electronic devices containing MCUs, and more specifically to a circuit for controlling MCU reset and a smart door lock. Background Technology

[0002] Traditional reset circuits control the MCU's reset pin to reset the MCU. Some low-power MCUs (such as microcontrollers used in smart door locks) often lack a fast discharge path in their design to reduce power consumption. When the reset pin is activated, voltage still exists inside the chip or in connected peripherals, and there is no dedicated low-impedance path to release this voltage. If power is applied again before the voltage has been completely discharged, the voltage detection module of the reset circuit will start operating from an incorrect level, resulting in the inability to generate a clean and effective reset pulse, thus preventing the chip from starting.

[0003] Therefore, how to provide a circuit and device that can completely release the residual voltage of the MCU power supply to ensure successful reset has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0004] This invention provides a control circuit for controlling MCU reset, applied to a system including a microcontroller. The control circuit includes a watchdog unit, a first power conversion unit, a second power conversion unit, and a fast discharge unit. The first power conversion unit provides a first power supply to the microcontroller, and the second power conversion unit provides a second power supply to the watchdog unit; the first and second power supplies are independently powered. The reset output terminal of the watchdog unit is connected to the enable terminal of the first power conversion unit and the control terminal of the fast discharge unit, respectively, and the input terminal of the fast discharge unit is connected to the first power supply. The watchdog unit outputs a reset signal when the microcontroller malfunctions. The first power conversion unit stops outputting the first power supply in response to the reset signal. The fast discharge unit is activated in response to the reset signal to release the residual voltage of the first power supply. The second power conversion unit continuously provides power to the watchdog unit during the release of the residual voltage of the first power supply to maintain the valid state of the reset signal.

[0005] It is evident that by combining the independent power supply of the dual power supplies with the reset and discharge logic, the control logic of the watchdog unit remains effective throughout the entire discharge cycle when the main power supply of the microcontroller is cut off, preventing the reset action from being prematurely interrupted due to power failure, thereby reliably discharging the residual charge of the first power supply.

[0006] Furthermore, the fast discharge unit includes a discharge switch transistor and a bleed resistor; the reset output terminal of the watchdog unit is connected to the gate of the discharge switch transistor, the source of the discharge switch transistor is connected to the first power supply, and the drain of the discharge switch transistor is grounded through the bleed resistor.

[0007] It is evident that a dedicated low-impedance discharge channel was constructed using the discharge switch and the bleed resistor, which improved the efficiency of discharging residual charge to ground.

[0008] Furthermore, the reset signal is used to drive the discharge switch to turn on, so that the charge of the first power supply is discharged to the ground through the discharge switch and the discharge resistor.

[0009] As can be seen, by directly driving the discharge switch to conduct through the reset signal, the synchronous linkage between the first power supply de-energization and the charge discharge action is achieved, ensuring the stable discharge of charge.

[0010] Furthermore, the microcontroller is used to periodically output a feed signal to the watchdog unit during normal operation; the watchdog unit is used to maintain a state of not outputting a reset signal when it receives the feed signal, the first power conversion unit maintains the output of the first power supply, and the fast discharge unit remains off.

[0011] It is evident that during normal operation of the microcontroller, the periodic dog-feeding mechanism maintains the stable output of the first power supply and the cut-off state of the fast discharge unit, ensuring the stability of the system's daily operation and preventing accidental triggering of discharge actions.

[0012] Furthermore, the watchdog unit includes a timer; specifically, the watchdog unit is used to generate a low-level reset signal when the timer does not receive a feed signal from the microcontroller within a preset time and overflows.

[0013] It is evident that the timer-based watchdog signal timeout mechanism for generating a low-level reset signal can accurately identify abnormal crash states of the microcontroller and improve the reliability of anomaly detection.

[0014] Furthermore, the discharge switch is a P-channel metal-oxide-semiconductor field-effect transistor.

[0015] As can be seen, using a P-channel metal-oxide-semiconductor field-effect transistor as the discharge switch allows its gate low-level conduction physical characteristic to match the low-level reset signal output by the watchdog unit, simplifying the design of the peripheral drive circuit.

[0016] Furthermore, the reset output terminal of the watchdog unit is connected to the gate of the discharge switch transistor through a gate resistor; a pull-up resistor is connected between the second power supply and the enable terminal of the first power conversion unit.

[0017] As can be seen, by setting the gate resistor and pull-up resistor, the drive current is effectively limited and the port level is stabilized, preventing the first power conversion unit from being turned off erroneously and the discharge switch from being turned on erroneously.

[0018] Furthermore, the control circuit also includes a reset circuit, which includes a reset resistor and a reset capacitor; one end of the reset resistor is connected to the first power supply, and the other end of the reset resistor is connected to the reset pin of the microcontroller; one end of the reset capacitor is connected to the reset pin of the microcontroller, and the other end of the reset capacitor is grounded.

[0019] It is evident that the RC network composed of the reset resistor and reset capacitor provides a stable hardware reset pin level environment for the microcontroller.

[0020] Furthermore, the watchdog unit is also used to cancel the reset signal after the residual voltage of the first power supply has been released; the first power supply conversion unit is used to restore the output of the first power supply after the reset signal is canceled; the reset resistor is used to transfer the voltage of the first power supply to the reset capacitor for charging, so as to generate a delayed reset pulse on the reset pin of the microcontroller.

[0021] It is evident that the hardware delay created by the RC charging process after the reset is canceled ensures that the microcontroller performs power-on startup only after the first power supply voltage has completely stabilized, thereby improving the success rate of system reset and restart.

[0022] A smart door lock includes a microcontroller and a control circuit of any one of the above, wherein the control circuit is used to control the reset of the microcontroller.

[0023] It is evident that applying the aforementioned control circuit to smart door locks can effectively solve the problem of hardware reset failure caused by residual voltage after a system crash in low-power devices, thereby improving the safety and reliability of smart door lock operation. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0025] Figure 1 This is a system schematic diagram according to an embodiment of the present invention.

[0026] Explanation of reference numerals in the attached diagram: 1. First power conversion unit; 2. Second power conversion unit; 3. Watchdog unit; 4. Microcontroller; R1. Reset resistor; R2. Pull-up resistor; R3. Gate resistor; R4. Bleeding resistor; Q2. Discharge switch transistor; C1. Reset capacitor. Detailed Implementation

[0027] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0030] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0031] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0032] The following is in conjunction with the appendix Figure 1 The circuit for controlling MCU reset and the smart door lock are described in detail.

[0033] This embodiment can be applied to terminal devices such as smart door locks that have extremely high power consumption requirements and are prone to residual voltage during dormancy.

[0034] System hardware structure layout reference appendix Figure 1 The entire system comprises a microcontroller 4, a watchdog unit 3, a first power conversion unit 1, a second power conversion unit 2, and a fast discharge unit. In the front-end power supply path, the input terminals of the first power conversion unit 1 and the second power conversion unit 2 are connected to the input power supply VIN node to receive the front-end DC voltage. In the buck and power distribution path, the output terminal of the first power conversion unit 1 (such as a DC-DC buck chip or an LDO linear regulator) outputs the first power supply VCC. The trace of this first power supply VCC is directly connected to the power pin of the microcontroller 4, supplying power to the microcontroller 4 and its internal logic modules. The output terminal of the second power conversion unit 2 outputs an independent second power supply VDD. The trace of this second power supply VDD is connected to the power pin of the watchdog unit 3, supplying power to the watchdog unit 3. In the physical circuit, the first power supply VCC and the second power supply VDD are mutually isolated at the output terminals, except that they share VIN at the front end.

[0035] In the control signal and discharge network connection relationship, microcontroller 4 is configured with IO pins, which are connected to the input terminal WDI of watchdog unit 3 via printed circuit board traces. Watchdog unit 3 has a reset output terminal RSTN. This reset output terminal RSTN is configured as two parallel control branches. The first control branch connects the reset output terminal RSTN to the enable terminal EN of the first power conversion unit 1. A pull-up resistor R2 is connected between the second power supply VDD trace and the enable terminal EN. The second control branch connects to the fast discharge unit. The fast discharge unit is mainly constructed by the discharge switch Q2 and the bleed resistor R4. The discharge switch Q2 is a P-channel metal-oxide-semiconductor field-effect transistor. The reset output terminal RSTN of watchdog unit 3 is connected to the gate of discharge switch Q2 through a series gate resistor R3. The source of discharge switch Q2 is directly connected to the first power supply VCC node, and the drain is connected to one end of bleed resistor R4. The other end of bleed resistor R4 is connected to the system ground GND.

[0036] The system also includes a reset circuit with an RC structure, comprising a reset resistor R1 and a reset capacitor C1. One end of the reset resistor R1 is connected to the first power supply VCC, and the other end is connected to the RESET pin of the microcontroller 4. One end of the reset capacitor C1 is connected to the RESET pin, and the other end is connected to ground GND.

[0037] During normal system operation, when microcontroller 4 is in normal working condition, its internal program control IO pins toggle levels according to a preset time period, continuously sending pulse signals (i.e., feed the watchdog signal) to the input terminal WDI of watchdog unit 3. Upon receiving this pulse signal, the timer inside watchdog unit 3 is reset, and the timer count will not reach the overflow threshold. In this state, the reset output terminal RSTN of watchdog unit 3 is open-drain. Due to the pull-up effect of pull-up resistor R2, the enable terminal EN of the first power conversion unit 1 remains high, and the first power conversion unit 1 is in the on state, continuously and stably outputting the first power supply VCC. Simultaneously, the high level of the reset output terminal RSTN is applied to the gate of discharge switch Q2 via gate resistor R3. At this time, the gate level of discharge switch Q2 is basically the same as the first power supply VCC level connected to its source, the gate-source voltage difference is close to zero, discharge switch Q2 is in the off state, and the fast discharge unit does not consume the power of the first power supply VCC.

[0038] When the microcontroller 4 malfunctions due to interference or a program entering an infinite loop, the IO pins stop outputting pulse signals. If the watchdog unit 3's input WDI does not detect a level transition within a preset time window, the internal timer continues to accumulate until it overflows. The timer overflow event triggers a logic transition within the watchdog unit 3, and its reset output RSTN actively outputs a low level (reset signal). This low-level signal pulls down the enable terminal EN of the first power conversion unit 1 through the first control branch, forcing the first power conversion unit 1 to shut down and stop outputting new power to the VCC network. Simultaneously, this low-level signal is transmitted to the gate of the discharge switch Q2 through the second control branch. At this time, the source of the discharge switch Q2 still maintains a residual voltage of the first power supply VCC, while the gate is forcibly pulled low. The watchdog unit 3 outputs a low-level reset signal to the gate of the discharge switch Q2, and the source of the discharge switch Q2 is connected to the voltage of the first power supply VCC, so that a voltage difference higher than the MOSFET's turn-on threshold is formed between the source and gate of the discharge switch Q2. The source and drain of the discharge switch Q2 are connected, creating a low-impedance discharge path from the first power supply node VCC, through the discharge switch Q2, and then through the discharge resistor R4 to ground GND. The residual charge stored in the internal capacitors of microcontroller 4 and on the VCC trace begins to rapidly discharge along this path. In this discharge control logic, a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used as the discharge switch Q2. Its low-level gate conduction characteristic perfectly matches the low-level reset signal output by the watchdog unit 3. Direct driving can be achieved without adding additional level shifting or inverting driver devices, thus effectively simplifying the design of the external drive circuit.

[0039] The physical mechanism by which an independent power supply sustains the discharge operation involves the following: If the watchdog unit 3 is also powered by the first power supply VCC, its ability to output a low level will be rapidly lost as the first power supply VCC voltage continuously decreases with charge discharge. This causes the discharge switch Q2 to turn off prematurely before VCC reaches 0V. In this embodiment, the second power conversion unit 2 obtains power through VIN and continuously and stably outputs the second power supply VDD throughout the entire VCC drop. The second power supply VDD provides uninterrupted power to the watchdog unit 3. Relying on the support of the second power supply VDD, the watchdog unit 3 can still drive the reset output RSTN to maintain a firm low level even when VCC drops to an extremely low level. This ensures that the gate potential of the discharge switch Q2 is always clamped near GND, keeping the discharge path unobstructed until the residual voltage in the first power supply VCC network is completely released.

[0040] The system reset and restart process, after the watchdog unit 3's preset reset hold period, completely drains the residual voltage of the first power supply VCC. Subsequently, the watchdog unit 3 releases the reset output RSTN. RSTN returns to a high-impedance state. The enable terminal EN of the first power conversion unit 1 returns to a high level under the action of the external pull-up resistor R2, restarting and outputting the first power supply VCC. Simultaneously, the discharge switch Q2 is turned off due to the disappearance of the gate-source voltage difference, breaking the discharge path. As the first power supply VCC voltage is re-established, current flows through the reset resistor R1 to charge the reset capacitor C1. Since the voltage across the capacitor cannot change abruptly, the RESET pin level of the microcontroller 4 exhibits a curve that slowly rises from low to high. In the initial stage of VCC stabilization, the RESET pin remains low (reset state). When the reset capacitor C1 is charged to the high-level threshold recognized by the microcontroller 4, the RESET pin jumps to a high level, the microcontroller 4 completes the reset, and restarts execution of internal code.

[0041] In summary, the circuit and smart door lock for controlling MCU reset provided in this embodiment utilize a physically isolated dual power supply architecture to ensure the power supply of the reset signal drive source. By coordinating the main power enable and bypass switch operation through the watchdog unit, a continuous charge discharge channel is established, eliminating the interference of residual voltage on the reset circuit state, thereby realizing reliable reset and startup of the microcontroller under complex operating conditions.

[0042] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A control circuit for controlling MCU reset, characterized in that, Applied to systems including microcontrollers, the control circuit includes a watchdog unit, a first power conversion unit, a second power conversion unit, and a fast discharge unit; Wherein, the first power conversion unit provides a first power supply to the microcontroller, and the second power conversion unit provides a second power supply to the watchdog unit, with the first power supply and the second power supply being powered independently; The reset output terminal of the watchdog unit is connected to the enable terminal of the first power conversion unit and the control terminal of the fast discharge unit, respectively, and the input terminal of the fast discharge unit is connected to the first power supply. The watchdog unit is used to output a reset signal when the microcontroller malfunctions. The first power conversion unit is used to stop outputting the first power supply in response to the reset signal; The fast discharge unit is used to conduct in response to the reset signal to release the residual voltage of the first power supply; The second power conversion unit is used to continuously provide power support to the watchdog unit during the residual voltage release of the first power supply, so as to maintain the valid state of the reset signal.

2. The control circuit according to claim 1, characterized in that, The fast discharge unit includes a discharge switch transistor and a bleed resistor; the reset output terminal of the watchdog unit is connected to the gate of the discharge switch transistor, the source of the discharge switch transistor is connected to the first power supply, and the drain of the discharge switch transistor is grounded through the bleed resistor.

3. The control circuit according to claim 2, characterized in that, The reset signal is used to drive the discharge switch to turn on, so that the charge of the first power supply is discharged to the ground through the discharge switch and the discharge resistor.

4. The control circuit according to claim 1, characterized in that, The microcontroller is used to periodically output a feed signal to the watchdog unit during normal operation; the watchdog unit is used to maintain a state of not outputting the reset signal when it receives the feed signal, the first power conversion unit continues to output the first power supply, and the fast discharge unit remains off.

5. The control circuit according to claim 4, characterized in that, The watchdog unit includes a timer; specifically, the watchdog unit is used to generate a low-level reset signal when the timer does not receive the feed signal output by the microcontroller within a preset time and overflows.

6. The control circuit according to claim 2, characterized in that, The discharge switch is a P-channel metal-oxide-semiconductor field-effect transistor.

7. The control circuit according to claim 2, characterized in that, The reset output terminal of the watchdog unit is connected to the gate of the discharge switch transistor through a gate resistor; a pull-up resistor is connected between the second power supply and the enable terminal of the first power conversion unit.

8. The control circuit according to claim 1, characterized in that, The control circuit further includes a reset circuit, which includes a reset resistor and a reset capacitor. One end of the reset resistor is connected to the first power supply, and the other end of the reset resistor is connected to the reset pin of the microcontroller. One end of the reset capacitor is connected to the reset pin of the microcontroller, and the other end of the reset capacitor is grounded.

9. The control circuit according to claim 8, characterized in that, The watchdog unit is further configured to cancel the reset signal after the residual voltage of the first power supply has been released; the first power conversion unit is configured to resume outputting the first power supply after the reset signal is canceled; the reset resistor is configured to transfer the voltage of the first power supply to the reset capacitor for charging, so as to generate a delayed reset pulse on the reset pin of the microcontroller.

10. A smart door lock, characterized in that, It includes a microcontroller and a control circuit as described in any one of claims 1 to 9, the control circuit being used to control the reset of the microcontroller.

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