power-on reset circuit

Abstract

The application discloses a power-on reset circuit which comprises a power-on reset main circuit module, a second power voltage generating circuit and a level conversion logic circuit. The power supply end of the power-on reset main circuit module is connected with the first power voltage and outputs a first reset signal. The power supply end of the second power voltage generating circuit is connected with the first power voltage and the output end outputs a second power voltage. The second power voltage is not equal to the first power voltage. The power supply end of the level conversion logic circuit is connected with the second power voltage, the input end is connected with the first reset signal, the output end outputs a second reset signal which is used as a reset signal of a voltage domain circuit of the second power voltage. The application can provide the reset signal and convert the level of the reset signal at the same time, can output the reset signal of the voltage domain circuit of the second power voltage in the voltage domain of the first power voltage without changing the voltage detection point, and can adjust the range of the second power voltage to expand the application range of the circuit.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a power-on-reset (POR) circuit. Background Technology

[0002] Power-on reset (POR) circuits are commonly used in microcontrollers (MCUs) for power-on detection. When power is supplied, POR provides a reset signal (RESET) to the chip's internal digital modules to ensure that the chip always starts operating in a defined state.

[0003] like Figure 1 The diagram shown is of an existing power-on reset circuit. The existing power-on reset circuit includes: a hysteresis circuit 101, a reset signal generation circuit 102, and a sampling delay and discharge circuit 103.

[0004] The hysteresis circuit 101 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a fifth PMOS transistor PM5, a first resistor R1, and a second resistor R2.

[0005] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the power supply voltage VDD.

[0006] The drain of the first PMOS transistor PM1, the first terminal of the first resistor R1, and the drain of the fifth PMOS transistor are all connected to the first node, and the voltage of the first node is voltage VN.

[0007] The gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the second end of the first resistor R1, and the first end of the second resistor R2 are all connected to the second node, and the voltage of the second node is voltage VP.

[0008] The drain of the second PMOS transistor PM2 is connected to the source of the fifth PMOS transistor PM5.

[0009] The gate of the fifth PMOS transistor PM5 is connected to the initial reset signal V2.

[0010] When the initial reset signal V2 is high, the fifth PMOS transistor PM5 is turned off, and the current flowing through the first resistor R1 and the second resistor R2 is the first branch current provided by the first PMOS transistor PM1.

[0011] When the initial reset signal V2 is low, the fifth PMOS transistor PM5 is turned on, and the current flowing through the first resistor R1 and the second resistor R2 is the sum of the first branch current provided by the first PMOS transistor PM1 and the second branch current provided by the second PMOS transistor PM2.

[0012] The reset signal generation circuit 102 includes a third PMOS transistor PM3, a first NMOS transistor NM1, and a buffer 104.

[0013] The source of the third PMOS transistor PM3 is connected to the power supply voltage VDD.

[0014] The gate of the third PMOS transistor PM3 is connected to the second node.

[0015] The source of the first NMOS transistor NM1 is grounded to GND25.

[0016] The gate of the first NMOS transistor NM1 is connected to the first node.

[0017] The drain of the third PMOS transistor PM3, the drain of the first NMOS transistor NM1, and the input of the buffer 104 are all connected to the third node, and the voltage of the third node is voltage V1.

[0018] The initial reset signal V2 is output from the output terminal of the buffer 104.

[0019] The sampling delay and discharge circuit 103 includes: a fourth PMOS transistor PM4, a sixth PMOS transistor PM6, a second NMOS transistor NM2, a first capacitor CAP, and an inverter 105. Figure 1 In this context, the inverter is also represented by INV.

[0020] The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD.

[0021] The gate of the fourth PMOS transistor PM4 is connected to the second node.

[0022] The source of the sixth PMOS transistor PM6 is connected to the drain of the fourth PMOS transistor PM4.

[0023] The source of the second NMOS transistor NM2 is grounded to GND25.

[0024] The gate of the sixth PMOS transistor PM6 and the gate of the second NMOS transistor NM2 are both connected to the initial reset signal V2.

[0025] The drain of the sixth PMOS transistor PM6, the drain of the second NMOS transistor NM2, the first terminal of the first capacitor CAP, and the input terminal of the inverter 105 are all connected to the fourth node, and the voltage of the fourth node is voltage V0.

[0026] The inverter 105 outputs the reset signal RESET.

[0027] The hysteresis circuit 101 is used to form a hysteresis window between the upper detection point and the lower detection point.

[0028] The reset signal generation circuit 102 is used to generate the initial reset signal V2.

[0029] The sampling delay and discharge circuit 103 is used to perform charging or discharging control under the initial reset signal V2 and to generate the reset signal RESET.

[0030] Figure 1 When the power supply voltage VDD is applied, the gate voltage VN of the first NMOS transistor NM1 rises, and NMOS transistor NM1 gradually turns on, pulling voltage V1 down. Simultaneously, voltage V2 also decreases, causing the sixth PMOS transistor PM6 to turn on. The fourth PMOS transistor PM4 mirrors the current from the branch of the first PMOS transistor PM1, charging capacitor CAP. The voltage V0 on the upper plate of capacitor CAP gradually increases. The reset signal RESET initially rises with the power supply voltage VDD. When voltage V0 increases sufficiently, INV105 flips, and the reset signal RESET goes from high to low. The power supply voltage VDD corresponding to the RESET flip is the voltage rise detection point (Vrise). The width of the high segment of the reset signal RESET is the pulse width of the reset signal RESET.

[0031] When the power supply voltage VDD drops (i.e., power is off), the voltage VN also drops. Since the fifth PMOS transistor PM5 turns on when the aforementioned voltage V2 decreases, the current in the branch of the second PMOS transistor PM2 also flows to resistors R1 and R2, increasing voltage VN. Simultaneously, voltage VP also increases, causing the current in the third PMOS transistor PM3 to decrease. Therefore, voltage VN will drop to an even lower value before voltage V1 can return to its high value. When voltage V1 increases, causing voltage V2 to flip to high, the second NMOS transistor NM2 can turn on. Voltage V0 discharges through the second NMOS transistor NM2, causing the reset signal RESET to flip back to the power supply voltage VDD. The corresponding power supply voltage VDD at this point is the voltage fall detection point (Vfall). The difference between the upper and lower voltage detection points is the voltage hysteresis voltage.

[0032] In practical MCU applications, the main power-on reset (POR) circuit, as the first module to start in the system, typically has its voltage detection point set above 1.6V. Once the supply voltage exceeds this value, subsequent digital modules begin the reset process, ensuring operation in a deterministic state. This 1.6V voltage detection requirement necessitates the use of CMOS transistors in the input / output (I / O) voltage domain during the design phase. Figure 1 In this structure, the amplitude of the RESET signal output is the same as the power supply voltage VDD, serving as the I / O voltage. The internal digital modules receiving this reset signal in the system often require a core voltage. However, when the system is first powered on, there is no accurate core voltage generated, making it impossible to introduce a core voltage domain into the POR circuit. Therefore, the voltage compatibility issue of the output signal limits the application of this circuit structure in the system. Summary of the Invention

[0033] The technical problem to be solved by the present invention is to provide a power-on reset circuit that can provide a reset signal and convert the level of the reset signal at the same time, output the reset signal of the second power supply voltage voltage domain circuit under the voltage domain of the first power supply voltage, and does not change the voltage detection point; and can adjust the range of the second power supply voltage to expand the application range of the circuit.

[0034] To solve the above-mentioned technical problems, the power-on reset circuit provided by the present invention includes: a power-on reset main circuit module, a second power supply voltage generation circuit, and a level-down logic circuit.

[0035] The power supply terminal of the power-on reset main circuit module is connected to the first power supply voltage, and the power-on reset main circuit module outputs a first reset signal; when the power is on, the first reset signal flips when the first power supply voltage rises to the upper detection point; when the power is off, the first reset signal flips when the first power supply voltage drops to the lower detection point.

[0036] The power supply terminal of the second power supply voltage generating circuit is connected to the first power supply voltage, and the output terminal of the second power supply voltage generating circuit outputs the second power supply voltage.

[0037] The second power supply voltage is not equal to the first power supply voltage.

[0038] The power supply terminal of the level conversion logic circuit is connected to the second power supply voltage output by the output terminal of the second power supply voltage generation circuit. The input terminal of the level conversion logic circuit is connected to the first reset signal. The output terminal of the level conversion logic circuit outputs a second reset signal, which serves as the reset signal for the voltage domain circuit of the second power supply voltage.

[0039] A further improvement is that the power-on reset main circuit module includes: a hysteresis circuit, a reset signal generation circuit, and a sampling delay and discharge circuit.

[0040] The hysteresis circuit is used to form a hysteresis window between the upper detection point and the lower detection point.

[0041] The reset signal generation circuit is used to generate an initial reset signal.

[0042] The sampling delay and discharge circuit is used to perform charging or discharging control under the initial reset signal and to generate the first reset signal.

[0043] A further improvement is that the hysteresis circuit includes: a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a first resistor, and a second resistor.

[0044] The source of both the first PMOS transistor and the source of the second PMOS transistor are connected to the first power supply voltage.

[0045] The drain of the first PMOS transistor, the first terminal of the first resistor, and the drain of the fifth PMOS transistor are all connected to the first node.

[0046] The gates of the first PMOS transistor, the second PMOS transistor, the second terminal of the first resistor, and the first terminal of the second resistor are all connected to the second node.

[0047] The drain of the second PMOS transistor is connected to the source of the fifth PMOS transistor.

[0048] The gate of the fifth PMOS transistor is connected to the initial reset signal.

[0049] When the initial reset signal is high, the fifth PMOS transistor is turned off, and the current flowing through the first resistor and the second resistor is the first branch current provided by the first PMOS transistor.

[0050] When the initial reset signal is low, the fifth PMOS transistor is turned on, and the current flowing through the first resistor and the second resistor is the sum of the first branch current provided by the first PMOS transistor and the second branch current provided by the second PMOS transistor.

[0051] A further improvement is that the reset signal generation circuit includes a third PMOS transistor, a first NMOS transistor, and a buffer.

[0052] The source of the third PMOS transistor is connected to the first power supply voltage.

[0053] The gate of the third PMOS transistor is connected to the second node.

[0054] The source of the first NMOS transistor is grounded.

[0055] The gate of the first NMOS transistor is connected to the first node.

[0056] The drain of the third PMOS transistor, the drain of the first NMOS transistor, and the input of the buffer are all connected to the third node.

[0057] The buffer outputs the initial reset signal.

[0058] A further improvement is that the sampling delay and discharge circuit includes: a fourth PMOS transistor, a sixth PMOS transistor, a second NMOS transistor, a first capacitor, and a first inverter.

[0059] The source of the fourth PMOS transistor is connected to the first power supply voltage.

[0060] The gate of the fourth PMOS transistor is connected to the second node.

[0061] The source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor.

[0062] The source of the second NMOS transistor is grounded.

[0063] The gate of the sixth PMOS transistor and the gate of the second NMOS transistor are both connected to the initial reset signal.

[0064] The drain of the sixth PMOS transistor, the drain of the second NMOS transistor, the first terminal of the first capacitor, and the input terminal of the first inverter are all connected to the fourth node.

[0065] The first inverter outputs the first reset signal.

[0066] A further improvement is that the second power supply voltage is lower than the first power supply voltage.

[0067] A further improvement is that the first power supply voltage is the voltage domain voltage of the input / output (IO) device.

[0068] The second power supply voltage is the voltage domain voltage of the core device.

[0069] A further improvement is that the second power supply voltage generation circuit includes: a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor.

[0070] The source of the seventh PMOS transistor and the drain of the fifth NMOS transistor are both connected to the first power supply voltage.

[0071] The gate of the seventh PMOS transistor is connected to the second node.

[0072] The gate of the fifth NMOS transistor, the drain of the seventh PMOS transistor, and the drain of the third NMOS transistor are connected together.

[0073] The drain and gate of the fourth NMOS transistor are connected, and the drain and gate of the eighth PMOS transistor are connected.

[0074] The gates of the third NMOS transistor, the fourth NMOS transistor, and the eighth PMOS transistor are connected together.

[0075] The source of the third NMOS transistor and the source of the fourth NMOS transistor are both grounded.

[0076] The source of the fifth NMOS transistor and the source of the eighth PMOS transistor are both connected to the fifth node, which serves as the output terminal of the second power supply voltage generation circuit.

[0077] A further improvement is that the second capacitor is connected between the drain and gate of the third NMOS transistor, and the fifth NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the eighth PMOS transistor form a negative feedback loop, with the second capacitor serving as a Miller capacitor.

[0078] A further improvement is that the second capacitor is less than 1pF.

[0079] A further improvement is that the substrate electrode and source electrode of the eighth PMOS transistor are connected.

[0080] A further improvement is that the level-shifting logic circuit includes a second inverter and a third inverter.

[0081] The input terminal of the second inverter serves as the input terminal of the level conversion logic circuit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter serves as the output terminal of the level conversion logic circuit.

[0082] The power supply terminals of the level conversion logic circuit include the power supply terminals of the second inverter and the third inverter.

[0083] A further improvement is that the magnitude of the second power supply voltage is determined by the sum of the turn-on voltages of the fourth NMOS transistor and the eighth PMOS transistor.

[0084] A further improvement is that the second power supply voltage generation circuit has a regulating structure for the second power supply voltage, the regulating structure including the branch current of the seventh PMOS transistor, the width-to-length ratio of the fourth NMOS transistor, and the width-to-length ratio of the eighth PMOS transistor.

[0085] Based on the power-on reset main circuit module, this invention adds a second power supply voltage generation circuit and a level conversion logic circuit. The second power supply voltage generation circuit and the level conversion logic circuit can perform level conversion on the first reset signal output by the power-on reset main circuit module to obtain a second reset signal that does not change the detection point and is suitable for voltage domain circuit reset of the second power supply voltage.

[0086] This invention can adjust the second power supply voltage generating circuit, thereby adjusting the range of the second power supply voltage and expanding the application range of the circuit.

[0087] This invention can be applied to situations where the first power supply voltage is greater than the second power supply voltage, thereby enabling the reset signal to be compatible across different voltage domains. For example, in this invention, the first power supply voltage is the IO voltage, and the second power supply voltage is the Core voltage. Thus, this invention can achieve the function of outputting a Core voltage reset signal in the IO voltage domain. The voltage detection point does not change during level transitions, which aligns with the practical application requirements of microcontroller units (MCUs). Furthermore, the adjustable circuitry can meet the Core voltage requirements of different platforms, further broadening the application range of existing circuits. Attached Figure Description

[0088] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0089] Figure 1 This is an existing power-on reset circuit diagram;

[0090] Figure 2 This is a power-on reset circuit diagram according to an embodiment of the present invention;

[0091] Figure 3 This is a waveform diagram of the power-on reset signal of the power-on reset circuit in an embodiment of the present invention. Detailed Implementation

[0092] like Figure 2 The diagram shown is a power-on reset circuit diagram according to an embodiment of the present invention. The power-on reset circuit according to an embodiment of the present invention includes: a power-on reset main circuit module 201, a second power supply voltage generation circuit 203, and a level conversion logic circuit 204.

[0093] The power supply terminal of the power-on reset main circuit module 201 is connected to the first power supply voltage VDD25, and the power-on reset main circuit module 201 outputs a first reset signal RESET25. When the power is on, the first reset signal RESET25 flips when the first power supply voltage VDD25 rises to the upper detection point; when the power is off, the first reset signal RESET25 flips when the first power supply voltage VDD25 falls to the lower detection point.

[0094] The power supply terminal of the second power supply voltage generating circuit 203 is connected to the first power supply voltage VDD25, and the output terminal of the second power supply voltage generating circuit 203 outputs the second power supply voltage VDD.

[0095] The second power supply voltage VDD is not equal to the first power supply voltage VDD25.

[0096] The power supply terminal of the level conversion logic circuit 204 is connected to the second power supply voltage VDD output by the output terminal of the second power supply voltage generation circuit 203. The input terminal of the level conversion logic circuit 204 is connected to the first reset signal RESET25. The output terminal of the level conversion logic circuit 204 outputs the second reset signal RESET. The second reset signal RESET serves as the reset signal for the voltage domain circuit of the second power supply voltage VDD.

[0097] In this embodiment of the invention, the power-on reset main circuit module 201 includes: a hysteresis circuit 101, a reset signal generation circuit 102, and a sampling delay and discharge circuit 103.

[0098] The hysteresis circuit 101 is used to form a hysteresis window between the upper detection point and the lower detection point.

[0099] The reset signal generation circuit 102 is used to generate the initial reset signal V2.

[0100] The sampling delay and discharge circuit 103 is used to perform charging or discharging control under the initial reset signal V2 and form the first reset signal RESET25.

[0101] In this embodiment of the invention, the power-on reset main circuit module 201 and Figure 1 The existing structure is the same. The circuit of this embodiment is based on the power-on reset main circuit module 201, with the addition of module 202, which consists of the second power supply voltage generation circuit 203 and the level conversion logic circuit 204. The hysteresis circuit 101 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a fifth PMOS transistor PM5, a first resistor R1, and a second resistor R2.

[0102] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both connected to the first power supply voltage VDD25.

[0103] The drain of the first PMOS transistor PM1, the first terminal of the first resistor R1, and the drain of the fifth PMOS transistor are all connected to the first node, and the voltage of the first node is voltage VN.

[0104] The gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, the second end of the first resistor R1, and the first end of the second resistor R2 are all connected to the second node, and the voltage of the second node is voltage VP.

[0105] The drain of the second PMOS transistor PM2 is connected to the source of the fifth PMOS transistor PM5.

[0106] The gate of the fifth PMOS transistor PM5 is connected to the initial reset signal V2.

[0107] When the initial reset signal V2 is high, the fifth PMOS transistor PM5 is turned off, and the current flowing through the first resistor R1 and the second resistor R2 is the first branch current provided by the first PMOS transistor PM1.

[0108] When the initial reset signal V2 is low, the fifth PMOS transistor PM5 is turned on, and the current flowing through the first resistor R1 and the second resistor R2 is the sum of the first branch current provided by the first PMOS transistor PM1 and the second branch current provided by the second PMOS transistor PM2.

[0109] The reset signal generation circuit 102 includes: a third PMOS transistor PM3, a first NMOS transistor NM1, and a buffer 104. Figure 2 The buffer 104 described herein is also represented by BUFF.

[0110] The source of the third PMOS transistor PM3 is connected to the first power supply voltage VDD25.

[0111] The gate of the third PMOS transistor PM3 is connected to the second node.

[0112] The source of the first NMOS transistor NM1 is grounded to GND25.

[0113] The gate of the first NMOS transistor NM1 is connected to the first node.

[0114] The drain of the third PMOS transistor PM3, the drain of the first NMOS transistor NM1, and the input of the buffer 104 are all connected to the third node, and the voltage of the third node is voltage V1.

[0115] The initial reset signal V2 is output from the output terminal of the buffer 104.

[0116] The sampling delay and discharge circuit 103 includes: a fourth PMOS transistor PM4, a sixth PMOS transistor PM6, a second NMOS transistor NM2, a first capacitor CAP, and a first inverter 105. Figure 2 In this context, the inverter is also represented by INV.

[0117] The source of the fourth PMOS transistor PM4 is connected to the first power supply voltage VDD25.

[0118] The gate of the fourth PMOS transistor PM4 is connected to the second node.

[0119] The source of the sixth PMOS transistor PM6 is connected to the drain of the fourth PMOS transistor PM4.

[0120] The source of the second NMOS transistor NM2 is grounded to GND25.

[0121] The gate of the sixth PMOS transistor PM6 and the gate of the second NMOS transistor NM2 are both connected to the initial reset signal V2.

[0122] The drain of the sixth PMOS transistor PM6, the drain of the second NMOS transistor NM2, the first terminal of the first capacitor CAP, and the input terminal of the first inverter 105 are all connected to the fourth node, and the voltage of the fourth node is voltage V0.

[0123] The first inverter 105 outputs the first reset signal RESET25.

[0124] In this embodiment of the invention, the second power supply voltage VDD is less than the first power supply voltage VDD25. The first power supply voltage VDD25 is the voltage domain voltage of the input / output devices. The second power supply voltage VDD is the voltage domain voltage of the core devices.

[0125] The second power supply voltage generation circuit 203 includes: a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5.

[0126] The source of the seventh PMOS transistor PM7 and the drain of the fifth NMOS transistor NM5 are both connected to the first power supply voltage VDD25.

[0127] The gate of the seventh PMOS transistor PM7 is connected to the second node.

[0128] The gate of the fifth NMOS transistor NM5, the drain of the seventh PMOS transistor PM7, and the drain of the third NMOS transistor NM3 are connected together.

[0129] The drain and gate of the fourth NMOS transistor NM4 are connected, and the drain and gate of the eighth PMOS transistor PM8 are connected.

[0130] The gates of the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the eighth PMOS transistor PM8 are connected together.

[0131] The source of the third NMOS transistor NM3 and the source of the fourth NMOS transistor NM4 are both grounded to GND25.

[0132] The source of the fifth NMOS transistor NM5 and the source of the eighth PMOS transistor PM8 are both connected to the fifth node. The fifth node serves as the output terminal of the second power supply voltage generation circuit 203, that is, the fifth node outputs the second power supply voltage VDD.

[0133] In this embodiment of the invention, the magnitude of the second power supply voltage VDD is determined by the sum of the turn-on voltages of the fourth NMOS transistor NM4 and the eighth PMOS transistor PM8 connected by a diode. In some embodiments, the second power supply voltage generation circuit 203 further includes an adjustment structure for the second power supply voltage VDD, the adjustment structure including the branch current of the seventh PMOS transistor PM7, the width-to-length ratio of the fourth NMOS transistor NM4, and the width-to-length ratio of the eighth PMOS transistor PM8.

[0134] The second capacitor, Miller Cap, is connected between the drain and gate of the third NMOS transistor NM3. The fifth NMOS transistor NM5, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the eighth PMOS transistor PM8 form a negative feedback loop. The second capacitor, Miller Cap, serves as a Miller capacitor. In some preferred embodiments, the second capacitor, Miller Cap, is less than 1 pF.

[0135] The substrate electrode and source electrode of the eighth PMOS transistor PM8 are connected.

[0136] The level conversion logic circuit 204 includes a second inverter 106 and a third inverter 107.

[0137] The input terminal of the second inverter 106 serves as the input terminal of the level conversion logic circuit 204, the output terminal of the second inverter 106 is connected to the input terminal of the third inverter 107, and the output terminal of the third inverter 107 serves as the output terminal of the level conversion logic circuit 204.

[0138] The power supply terminals of the level conversion logic circuit 204 include the power supply terminals of the second inverter 106 and the third inverter 107.

[0139] Based on the power-on reset main circuit module 201, this embodiment of the invention adds a second power supply voltage generation circuit 203 and a level conversion logic circuit 204. The second power supply voltage generation circuit 203 and the level conversion logic circuit 204 can perform level conversion on the first reset signal RESET25 output by the power-on reset main circuit module 201 and obtain a second reset signal RESET that does not change the detection point and is suitable for voltage domain circuit reset of the second power supply voltage VDD.

[0140] The embodiments of the present invention can adjust the second power supply voltage generating circuit 203 so that the range of the second power supply voltage VDD can be adjusted, thereby expanding the application range of the circuit.

[0141] This invention can be applied to situations where the first power supply voltage VDD25 is greater than the second power supply voltage VDD, thus enabling the reset signal to be compatible across different voltage domains. For example, in this embodiment, the first power supply voltage VDD25 is the IO voltage, and the second power supply voltage VDD is the Core voltage. This allows the invention to output a Core voltage reset signal in the IO voltage domain, without changing the voltage detection point during level transitions, which aligns with the practical application requirements of microcontroller units (MCUs). Furthermore, the adjustable circuitry meets the Core voltage requirements of different platforms, further expanding the application scope of existing circuits.

[0142] To address the issue that existing circuit structures only generate I / O voltage output signals when powered in the I / O voltage domain, this invention updates the circuit based on the existing structure. Figure 1 The structure introduces a circuit 202 to implement the level conversion function, which generates a Core voltage with relatively limited accuracy, such as ±20% at the full process corner, in the I / O voltage domain. This Core voltage is used to power the level conversion logic circuit 204 (Level-Down), thereby converting the first reset signal RESET25 of the I / O voltage into the second reset signal RESET of the Core voltage.

[0143] In circuit 203, the gate of the seventh PMOS transistor PM7 is connected to the gate of the first PMOS transistor PM1, forming a current mirror that reflects the current of the PM1-R1-R2 branch. The third NMOS transistor NM3 mirrors the current of the fourth NMOS transistor NM4. Both the fourth NMOS transistor NM4 and the eighth PMOS transistor PM8 are MOS diodes. The output second power supply voltage VDD is approximately the sum of the turn-on voltages of the two MOS diodes, which is approximately 0.7V. The output voltage VDD can be adjusted by regulating the branch current of the seventh PMOS transistor PM7 and the dimensions of the fourth NMOS transistor NM4 and the eighth PMOS transistor PM8.

[0144] The substrate of the eighth PMOS transistor, PM8, is connected to its own source, which avoids the substrate bias effect on its threshold voltage V. TH This reduces the impact of dynamic changes in the first power supply voltage VDD25 on the performance of the eighth PMOS transistor PM8, ensuring that the output voltage VDD is as stable as possible at the target core voltage.

[0145] The NM5-NM3-NM4-PM8 transistors form a negative feedback loop. When the VDD output changes, it can be adjusted through the negative feedback loop to stabilize the output. To address this negative feedback loop, this embodiment of the invention also introduces a Miller capacitor of less than 1pF connected between the gate and drain of the third NMOS transistor, NM3, to improve loop stability.

[0146] Circuit 203 can achieve the function of stable output of Core voltage. The generated second power supply voltage VDD supplies power to the inverter (INV) logic of the core device. The first reset signal RESET25 generated by the combination of circuits 101, 102 and 103 is transformed into the second reset signal RESET in the Core voltage domain through the INV logic of circuit 204 to achieve the Level-Down function, and then directly output to the digital module in the MCU.

[0147] This invention introduces a level conversion circuit 202 into the existing circuit 201, realizing the function of outputting a second reset signal RESET for the Core voltage in the I / O voltage domain. The voltage detection point remains unchanged during the level conversion process, which aligns with the actual application requirements of the MCU. Furthermore, the adjustable circuit meets the Core voltage requirements of different platforms, further broadening the application range of the existing circuit.

[0148] The circuit of this embodiment of the invention was simulated under normal temperature and pressure conditions, such as 25℃@2.5V, with slow power-on and power-off at the three process corners TT, FF, and SS, for example, power-on at 10ms. The simulation waveform is shown below. Figure 3 As shown.

[0149] Figure 3 In the figure, curve 301 is the curve of the first power supply voltage VDD25 changing with time, curve 302 is the curve of the second power supply voltage VDD changing with time, curve 303 is the curve of the first reset signal RESET25 changing with time, and curve 304 is the curve of the second reset signal RESET changing with time.

[0150] It can be seen that after the second power supply voltage VDD is powered on by the first power supply voltage VDD25, if it is >1.1V, it can be basically stabilized at around 1.1V.

[0151] The second reset signal RESET, output from the first reset signal RESET25 after level conversion, has the same voltage as the second power supply voltage VDD when it is high. Furthermore, the circuit's own voltage detection point remains unchanged. Therefore, the Core voltage signal output can be achieved.

[0152] The power-on reset circuit structure of this invention has been applied in the design of a 40nm embedded flash memory (EF) platform. Verified by Virtuoso simulation, the circuit can achieve a reset signal output of Core voltage such as 1.1V, and the introduction of a level conversion circuit does not change its voltage detection points.

[0153] The power-on reset circuit of this invention allows for flexible adjustment of voltage detection points and RESET pulse width, and can recognize power-on and power-off behavior within a short period, such as 2μs, with the second reset signal RESET responding correctly. Furthermore, the power-on reset circuit of this invention is scalable, capable of generating different Core voltage values, and can be extended to multiple existing platforms in the future.

[0154] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A power-on reset circuit, characterized in that, include: The power-on reset main circuit module, the second power supply voltage generation circuit, and the level conversion logic circuit; The power supply terminal of the power-on reset main circuit module is connected to the first power supply voltage, and the power-on reset main circuit module outputs a first reset signal; when powered on, the first reset signal flips when the first power supply voltage rises to the upper detection point; when powered off, the first reset signal flips when the first power supply voltage drops to the lower detection point. The power supply terminal of the second power supply voltage generating circuit is connected to the first power supply voltage, and the output terminal of the second power supply voltage generating circuit outputs the second power supply voltage. The second power supply voltage is not equal to the first power supply voltage; The power supply terminal of the level conversion logic circuit is connected to the second power supply voltage output by the output terminal of the second power supply voltage generation circuit. The input terminal of the level conversion logic circuit is connected to the first reset signal. The output terminal of the level conversion logic circuit outputs a second reset signal, which serves as the reset signal for the voltage domain circuit of the second power supply voltage. The power-on reset main circuit module includes: a hysteresis circuit, a reset signal generation circuit, and a sampling delay and discharge circuit; The hysteresis circuit is used to form a hysteresis window between the upper detection point and the lower detection point; The reset signal generation circuit is used to generate an initial reset signal; The sampling delay and discharge circuit is used to perform charging or discharging control under the initial reset signal and to generate the first reset signal. The hysteresis circuit includes: a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a first resistor, and a second resistor; The source of the first PMOS transistor and the source of the second PMOS transistor are both connected to the first power supply voltage. The drain of the first PMOS transistor, the first terminal of the first resistor, and the drain of the fifth PMOS transistor are all connected to the first node. The gate of the first PMOS transistor, the gate of the second PMOS transistor, the second end of the first resistor, and the first end of the second resistor are all connected to the second node; The drain of the second PMOS transistor is connected to the source of the fifth PMOS transistor; The gate of the fifth PMOS transistor is connected to the initial reset signal; When the initial reset signal is high, the fifth PMOS transistor is turned off, and the current flowing through the first resistor and the second resistor is the first branch current provided by the first PMOS transistor. When the initial reset signal is low, the fifth PMOS transistor is turned on, and the current flowing through the first resistor and the second resistor is the sum of the first branch current provided by the first PMOS transistor and the second branch current provided by the second PMOS transistor. The second power supply voltage generation circuit includes: a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The source of the seventh PMOS transistor and the drain of the fifth NMOS transistor are both connected to the first power supply voltage. The gate of the seventh PMOS transistor is connected to the second node; The gate of the fifth NMOS transistor, the drain of the seventh PMOS transistor, and the drain of the third NMOS transistor are connected together. The drain and gate of the fourth NMOS transistor are connected, and the drain and gate of the eighth PMOS transistor are connected. The gates of the third NMOS transistor, the fourth NMOS transistor, and the eighth PMOS transistor are connected together. The source of the third NMOS transistor and the source of the fourth NMOS transistor are both grounded; The source of the fifth NMOS transistor and the source of the eighth PMOS transistor are both connected to the fifth node, which serves as the output terminal of the second power supply voltage generation circuit.

2. The power-on reset circuit as described in claim 1, characterized in that: The reset signal generation circuit includes: a third PMOS transistor, a first NMOS transistor, and a buffer; The source of the third PMOS transistor is connected to the first power supply voltage; The gate of the third PMOS transistor is connected to the second node; The source of the first NMOS transistor is grounded; The gate of the first NMOS transistor is connected to the first node; The drain of the third PMOS transistor, the drain of the first NMOS transistor, and the input of the buffer are all connected to the third node. The buffer outputs the initial reset signal.

3. The power-on reset circuit as described in claim 2, characterized in that: The sampling delay and discharge circuit includes: a fourth PMOS transistor, a sixth PMOS transistor, a second NMOS transistor, a first capacitor, and a first inverter; The source of the fourth PMOS transistor is connected to the first power supply voltage; The gate of the fourth PMOS transistor is connected to the second node; The source of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor; The source of the second NMOS transistor is grounded; The gate of the sixth PMOS transistor and the gate of the second NMOS transistor are both connected to the initial reset signal; The drain of the sixth PMOS transistor, the drain of the second NMOS transistor, the first terminal of the first capacitor, and the input terminal of the first inverter are all connected to the fourth node; The first inverter outputs the first reset signal.

4. The power-on reset circuit as described in claim 3, characterized in that: The second power supply voltage is less than the first power supply voltage.

5. The power-on reset circuit as described in claim 4, characterized in that: The first power supply voltage is the voltage in the voltage domain of the input / output devices; The second power supply voltage is the voltage domain voltage of the core device.

6. The power-on reset circuit as described in claim 5, characterized in that: The second capacitor is connected between the drain and gate of the third NMOS transistor. The fifth NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the eighth PMOS transistor form a negative feedback loop. The second capacitor serves as a Miller capacitor.

7. The power-on reset circuit as described in claim 6, characterized in that: The second capacitor is less than 1pF.

8. The power-on reset circuit as described in claim 1, characterized in that: The substrate electrode and source electrode of the eighth PMOS transistor are connected.

9. The power-on reset circuit as described in claim 1, characterized in that: The level conversion logic circuit includes a second inverter and a third inverter; The input terminal of the second inverter serves as the input terminal of the level conversion logic circuit, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter serves as the output terminal of the level conversion logic circuit. The power supply terminals of the level conversion logic circuit include the power supply terminals of the second inverter and the third inverter.

10. The power-on reset circuit as described in claim 1, characterized in that: The magnitude of the second power supply voltage is determined by the sum of the turn-on voltages of the fourth NMOS transistor and the eighth PMOS transistor.

11. The power-on reset circuit as described in claim 10, characterized in that: The second power supply voltage generation circuit has a regulating structure for the second power supply voltage, the regulating structure including the branch current of the seventh PMOS transistor, the width-to-length ratio of the fourth NMOS transistor, and the width-to-length ratio of the eighth PMOS transistor.

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