Power-on reset circuit with zero static current and parameter optimization method thereof

Abstract

This invention relates to the field of integrated circuit design, providing a zero quiescent current power-on reset circuit and its parameter optimization method. The power-on reset circuit includes a power-on detection module and a pulse latch module. The power-on detection module includes a resistor array, a capacitor array, and a semiconductor switching device. The control terminal of a first semiconductor switching device is connected to the output node of the capacitor array, a first terminal of the first semiconductor switching device is connected to a reference ground, and a second terminal of the first semiconductor switching device is connected to the input terminal of the pulse latch module. A second semiconductor switching device is connected in series between the input power supply and the resistor array. The pulse latch module includes a bootstrap capacitor. During the generation of the reset pulse, the bootstrap capacitor is charged. After the reset pulse is generated, the pulse latch module transfers the charge of the bootstrap capacitor to the control terminal of the second semiconductor switching device. This invention is used for power management of low-power electronic devices, eliminating quiescent power consumption and ensuring reset reliability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a power-on reset circuit with zero quiescent current and a method for optimizing its parameters. Background Technology

[0002] In power-on reset circuit design, the resistor divider network, as the core unit for power supply voltage detection, needs to be continuously connected between the power supply and reference ground to maintain the detection function. However, this structure has an inherent drawback: after the reset pulse is generated and released, the resistor divider network remains physically conductive, forming a permanent DC path from the power supply through the resistor array to the reference ground. This path continuously consumes static current after the system enters normal operation, and its power consumption is inversely proportional to the resistance value of the divider resistor. To ensure detection accuracy and response speed, the resistance value is usually limited, making it difficult to reduce the static current to below the microampere level. Some improvement schemes attempt to introduce external enable signals or independent shutdown circuits to actively cut off the voltage divider path after reset, but such designs significantly increase the complexity of control logic and chip area, and depend on the reliability of external timing signals; if the shutdown timing is mismatched, it may cause reset failure or deterioration of power supply noise sensitivity. In application scenarios such as battery-powered devices, wearable terminals, and IoT sensing nodes, which are extremely sensitive to long standby power consumption, this static current accumulation effect directly shortens the device's battery life and becomes a key bottleneck for improving power management efficiency. Existing technologies have consistently failed to achieve automatic disconnection of the voltage divider path after reset without sacrificing circuit autonomy, reliability, and area efficiency.

[0003] Therefore, there is an urgent need for a power-on reset circuit with zero quiescent current and a method for optimizing its parameters to improve the above problems. Summary of the Invention

[0004] This invention provides a zero quiescent current power-on reset circuit and its parameter optimization method. This invention is used for power management of low-power electronic devices, eliminating quiescent power consumption and ensuring reset reliability.

[0005] According to a first aspect of the present invention, a zero quiescent current power-on reset circuit is provided, applied to a power control system. The power-on reset circuit includes a power-on detection module and a pulse latch module connected to each other. The power-on detection module includes a resistor array, a capacitor array, a first semiconductor switch, and a second semiconductor switch. The control terminal of the first semiconductor switch is connected to the output node of the capacitor array, a first terminal of the first semiconductor switch is connected to a reference ground, and a second terminal of the first semiconductor switch is connected to the input terminal of the pulse latch module. The first semiconductor switch is used to turn on and output a power-on detection trigger signal when the detection signal reaches a power-on threshold. The second semiconductor switch is connected in series between the input power supply and the resistor array. The resistor array is used to divide the voltage of the input power supply to generate a voltage divider signal; the capacitor array is used to generate a detection signal based on the voltage divider signal; the pulse latch module integrates a bootstrap capacitor, the first end of which is connected to the control terminal of the second semiconductor switching device, and the second end of which is connected to an internal node of the pulse latch module; the pulse latch module is used to receive the power-on detection trigger signal and generate a reset pulse, during which the bootstrap capacitor is charged; after the reset pulse is generated, the pulse latch module is used to transfer the charge of the bootstrap capacitor to the control terminal of the second semiconductor switching device, raise the voltage of the control terminal, drive the second semiconductor switching device to turn off, and cut off the DC voltage divider path composed of the resistor array, power supply and reference ground.

[0006] In one embodiment, the pulse latch module includes a first latch node, a second latch node, a latch output node, a fast latch feedback loop, and a slow hold feedback loop; the first latch node is connected to the second terminal of a first semiconductor switching device; the latch output node is driven by the second latch node and serves as the output terminal of a reset pulse; the fast latch feedback loop is coupled between the first latch node, the second latch node, and the latch output node; the slow hold feedback loop is coupled between the first latch node and the second latch node; and the time constant of the slow hold feedback loop is greater than the time constant of the fast latch feedback loop.

[0007] In one embodiment, the fast latch feedback loop includes an inverter chain for accelerating the generation of a reset pulse; the slow hold feedback loop includes an inverter and a third semiconductor switch, the input of the inverter is coupled to a first latch node, the output of the inverter is coupled to a first terminal of the third semiconductor switch, the second terminal of the third semiconductor switch is coupled to a second latch node, and the control terminal of the third semiconductor switch is coupled to a latch output node; when the latch output node is active, the third semiconductor switch is turned on, causing the inverter to form a weak feedback path between the first latch node and the second latch node.

[0008] In one embodiment, the power-on reset circuit further includes an undervoltage detection module and a reset management module. The undervoltage detection module is coupled to the voltage divider node and detection node of the power-on detection module. The undervoltage detection module reuses the resistor array voltage divider circuit and capacitor array charging and discharging circuit of the power-on detection module to generate an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold. The first input terminal of the reset management module is coupled to the output terminal of the pulse latch module to receive a reset pulse, and the second input terminal of the reset management module is coupled to the output terminal of the undervoltage detection module to receive an undervoltage detection signal. The reset management module is used to receive the reset pulse and the undervoltage detection signal, and generate a system reset signal based on the reset pulse and the undervoltage detection signal.

[0009] In one embodiment, the undervoltage detection module includes a fourth semiconductor switching device. The control terminal of the fourth semiconductor switching device is electrically connected to the voltage divider node of the power-on detection module, the first terminal is connected to a reference ground, and the second terminal is electrically connected to the input terminal of the reset management module. The fourth semiconductor switching device turns on and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold.

[0010] In one embodiment, the power-on reset circuit includes a multi-mode configuration interface connected to a resistor array and a capacitor array via a fifth semiconductor switching device to adjust the voltage division ratio of the resistor array and / or the charge / discharge time constant of the capacitor array.

[0011] In one embodiment, the power-on reset circuit includes a debounce circuit connected to the input terminal of the reset management module, used to debounce the reset pulse or undervoltage detection signal.

[0012] In one embodiment, the power-on reset circuit includes at least one feedback semiconductor switch. The control terminal of each feedback semiconductor switch is connected to the output terminal of the reset management module. The first terminal of each feedback semiconductor switch is connected to a first latch node, and the second terminal of each feedback semiconductor switch is connected to a positive power supply node. The feedback semiconductor switch is used to turn on after the system reset is released and apply a pull-up current to the first latch node to maintain a stable level.

[0013] In one embodiment, the resistor array of the power-on detection module includes multiple resistor branches, each resistor branch including a resistor and a sixth semiconductor switch, the sixth semiconductor switch being connected in series with the resistor.

[0014] In one embodiment, the capacitor array of the power-on detection module includes multiple capacitors, each capacitor being connected to the detection node of the undervoltage detection module via a corresponding seventh semiconductor switching device.

[0015] In one embodiment, the power-on detection module includes at least one feedback circuit, each feedback circuit including an eighth semiconductor switching device, the control terminal of the eighth semiconductor switching device being connected to the voltage divider node of the power-on detection module, the first terminal of the eighth semiconductor switching device being connected to the output node of the undervoltage detection module, and the second terminal of the eighth semiconductor switching device being connected to a second latch node.

[0016] According to a second aspect of the present invention, a parameter optimization method for a power-on reset circuit is provided. The power-on reset circuit includes a power-on detection module, a pulse latch module, a bootstrap capacitor, a first semiconductor switching device, and a second semiconductor switching device. The method includes: defining a design parameter space, which includes combinations of circuit parameters for the power-on reset circuit; setting multiple test scenarios, which cover variations in process corner, power supply voltage, and temperature; obtaining a performance dataset through circuit simulation based on the circuit parameter combinations in the design parameter space and the test scenarios; training an artificial intelligence prediction model based on the performance dataset, which predicts the performance indicators of a given combination of circuit parameters under the test scenarios; searching for a Pareto optimal solution that satisfies preset constraints in the design parameter space using a multi-objective optimization algorithm based on the artificial intelligence prediction model, where the Pareto optimal solution corresponds to at least one combination of circuit parameters; and generating layout data of the power-on reset circuit based on the target combination of circuit parameters.

[0017] In one embodiment, the design parameter space includes at least one of the following: the resistance value of each branch of the resistor array in the power-on detection module and the connection status of each branch; the capacitance value of each capacitor in the capacitor array in the power-on detection module and the connection status of each unit; the channel width to channel length ratio of the semiconductor switching device in the power-on reset circuit; the channel width to channel length ratio of the semiconductor switching device in the slow hold feedback loop in the pulse latch module; the enable status of the slow hold feedback loop; and the counting threshold and time constant of the debouncing circuit in the power-on reset circuit.

[0018] In one embodiment, the power-on reset circuit includes an undervoltage detection module; the undervoltage detection module reuses part of the resistor array and capacitor array of the power-on detection module, and the undervoltage detection module includes a fourth semiconductor switching device, which turns on and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold; the performance dataset includes: the power-on reset threshold voltage of the power-on detection module, the undervoltage detection threshold voltage of the undervoltage detection module, the reset release delay of the pulse latch module, the undervoltage response time of the undervoltage detection module, the quiescent current of the power-on reset circuit, and the internal node voltage margin of the pulse latch module.

[0019] In one implementation, the preset constraints include an upper limit on the layout area and a transient peak current threshold. The optimization objectives of the multi-objective optimization algorithm include at least two of the following: power-on reset threshold voltage, undervoltage detection threshold voltage, quiescent current, internal node voltage margin, reset release delay, and undervoltage response time.

[0020] In one implementation, the method includes: selecting at least one set of target circuit parameter combinations from Pareto optimal solutions; configuring configurable branches in a power-on reset circuit to default connection states corresponding to the target circuit parameter combinations; and defining a mapping relationship between mode identifiers and default connection states.

[0021] Compared with the prior art, the beneficial effects of this invention are as follows: After the reset pulse is generated, the pulse latch module directionally transfers the charge stored in the bootstrap capacitor to the control terminal of the second semiconductor switch to raise the control terminal voltage, thereby driving the second semiconductor switch to enter the off state. Since the second semiconductor switch is physically connected in series between the resistor array and the reference ground, its turn-off directly cuts off the DC voltage divider path composed of the resistor array, power supply, and reference ground. After the DC voltage divider path is cut off, there is no longer a continuously conducting current circuit in the resistor array. Therefore, after the system enters the normal operating state, the resistor voltage divider network of the power-on detection module no longer consumes any static current. This effect does not rely on external control signals or additional enable circuits, but is a structural self-locking mechanism naturally triggered by the internal timing event completed by the reset pulse. This fundamentally eliminates the static power consumption caused by the continuous conduction of the resistor voltage divider network in traditional power-on reset circuits, significantly improving power management efficiency, especially meeting the application requirements of battery-powered and IoT nodes that are sensitive to long standby power consumption. Attached Figure Description

[0022] Figure 1 This is a block diagram illustrating a power-on reset circuit with zero quiescent current, according to an exemplary embodiment.

[0023] Figure 2 This is a schematic diagram of a power-on reset circuit with zero quiescent current, according to an exemplary embodiment.

[0024] Figure 3 This is a schematic diagram of a top-level PSU_POR structure according to another exemplary embodiment.

[0025] Figure 4 This is a schematic diagram of a PSU_POR_DEGLITCH debouncing circuit structure according to an exemplary embodiment.

[0026] Figure 5 This is a schematic diagram of a PSU_POR top-level test platform according to another exemplary embodiment.

[0027] Figure 6 This is a timing waveform diagram illustrating a typical power-on process according to another exemplary embodiment.

[0028] Figure 7 This is a typical waveform diagram illustrating a hardware reset trigger according to an exemplary embodiment.

[0029] Figure 8 This is a flowchart illustrating a parameter optimization method for a power-on reset circuit according to another exemplary embodiment.

[0030] Explanation of the reference numerals in the figure: 1. Power-on detection module; 2. Pulse latch module; 3. Undervoltage detection module; 4. Reset management module. Detailed Implementation

[0031] Unless otherwise defined, the technical or scientific terms used in this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0032] like Figure 1As shown, the first embodiment of the present invention provides a zero quiescent current power-on reset circuit applied to a power control system. The power-on reset circuit includes a power-on detection module 1 and a pulse latch module 2 connected to each other. The power-on detection module 1 includes a resistor array, a capacitor array, a first semiconductor switch, and a second semiconductor switch. The control terminal of the first semiconductor switch is connected to the output node of the capacitor array, the first terminal of the first semiconductor switch is connected to a reference ground, and the second terminal of the first semiconductor switch is connected to the input terminal of the pulse latch module 2. The first semiconductor switch is used to conduct and output a power-on detection trigger signal when the detection signal reaches a power-on threshold. The second semiconductor switch is connected in series between the input power supply and the resistor array. The resistor array is used to divide the voltage of the input power supply to generate a voltage divider signal; the capacitor array is used to generate a detection signal based on the voltage divider signal; the pulse latch module 2 integrates a bootstrap capacitor, the first end of which is connected to the control terminal of the second semiconductor switching device, and the second end of which is connected to the internal node of the pulse latch module 2; the pulse latch module 2 is used to receive the power-on detection trigger signal and generate a reset pulse, during which the bootstrap capacitor is charged; after the reset pulse is generated, the pulse latch module 2 is used to transfer the charge of the bootstrap capacitor to the control terminal of the second semiconductor switching device, raise the voltage of the control terminal, drive the second semiconductor switching device to turn off, and cut off the DC voltage divider path composed of the resistor array, power supply and reference ground.

[0033] like Figure 2 As shown, in some specific embodiments, the resistor array includes a first resistor R1 and a second resistor R2 connected in series; the capacitor array includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first semiconductor switching device is a first transistor M1, and the second semiconductor switching device is a second transistor M2.

[0034] In some examples, the reference ground is the negative power supply VSS. In other examples, the reference ground is ground GND.

[0035] In other specific embodiments, the second transistor M2 has a four-terminal structure, including a gate, source, drain, and body. The gate serves as a control terminal, receiving the detection enable signal DET_EN. The drain is connected to a node in the resistor array. The source and body are connected to the positive power supply VDD in the circuit, forming a standard bias configuration for a P-channel metal-oxide-semiconductor (PMOS) device. The body and source are at the same potential to suppress the body effect. This connection method allows the second transistor M2 to regulate the path state between the resistor array and the power supply under the control of the detection enable signal DET_EN.

[0036] In some specific embodiments, the first resistor R1 and the second resistor R2 each have a first terminal and a second terminal opposite to each other; the first terminal of the second resistor R2 is connected to the reference ground, the second terminal of the second resistor R2 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the drain of the second transistor M2. The power-on detection module 1 also includes a twelfth transistor M12 and a thirteenth transistor M13. Both the twelfth transistor M12 and the thirteenth transistor M13 have a four-terminal structure, including a gate, a source, a drain, and a body terminal. The gates of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the third capacitor C0. The drains of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the gate of the second transistor M2 through two series-connected inverters. The source and body terminals of the twelfth transistor M12 are both connected to the positive power supply VDD, and the source and body terminals of the thirteenth transistor M13 are both connected to the negative power supply VSS.

[0037] In some specific embodiments, the first transistor M1 has a four-terminal structure, including a gate, source, drain, and body. Its gate serves as a control terminal, receiving the output signal of the twelfth transistor M12, which is buffered by two stages of inverters. The drain is connected to a resistor divider node driven by another two stages of inverters, located between the first resistor R1 and the second resistor R2. The source is connected to the first terminal of the second capacitor C2, the body is connected to the positive power supply VDD, and the second terminal of the second capacitor C2 is connected to the negative power supply VSS. This connection configuration allows the switching state of the first transistor M1 to be regulated by the signal chain of the twelfth transistor M12 and participates in the dynamic charging and discharging process of the detection node.

[0038] In some examples, the pulse latch module 2 further includes a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, and a seventeenth transistor M17. All four transistors M14, M15, M16, and M17 are four-terminal structures, each including a gate, source, drain, and body. The source and body of the fourteenth transistor M14 are connected to the positive power supply VDD, and the source and body of the fifteenth transistor M15 are connected to the negative power supply VSS. The gates of the fourteenth and fifteenth transistors are connected to the second capacitor C2 via the first node PL4. The drains of the fourteenth and fifteenth transistors are connected to the second node PL5. The source and body of the sixteenth transistor M16 are connected to the positive power supply VDD, and the source and body of the seventeenth transistor M17 are connected to the negative power supply VSS. The gates of the sixteenth and seventeenth transistors are connected to the second node PL5. The drain of the sixteenth transistor M16 and the drain of the seventeenth transistor M17 are connected together to the third node PL6.

[0039] In other examples, the pulse latch module 2 also includes a first buffer BUFX1 and a second buffer BUFX2. The input of the first buffer BUFX1 is connected to the third node PL6, and the output of the first buffer BUFX1 is connected to the input of the second buffer BUFX2 and the gate of the first transistor M1 to provide a detection enable signal DET_EN. The output of the second buffer BUFX2 is used to provide a power-on reset signal POR.

[0040] In one embodiment, the pulse latch module 2 includes a first latch node, a second latch node, a latch output node, a fast latch feedback loop, and a slow hold feedback loop; the first latch node is connected to the second terminal of a first semiconductor switching device; the latch output node is driven by the second latch node and serves as the output terminal of a reset pulse; the fast latch feedback loop is coupled between the first latch node, the second latch node, and the latch output node; the slow hold feedback loop is coupled between the first latch node and the second latch node; and the time constant of the slow hold feedback loop is greater than the time constant of the fast latch feedback loop.

[0041] In some specific embodiments, in one particular implementation, the pulse latch module 2 adopts a multi-level feedback architecture, including a fast latch feedback loop, a slow hold feedback loop, and a bootstrap hold feedback path. The fast latch feedback loop includes a strong drive inverter chain, which connects the first latch node PL4, the second latch node PL5, and the latch output node PL6. This strong drive inverter chain is composed of transistors M14–M17, numbered fourteenth to seventeenth. When the power-on detection signal is triggered, this loop quickly completes the state flip due to its high drive capability, significantly shortening the reset pulse generation delay and suppressing timing jitter. The slow hold feedback loop includes a weak drive inverter and a third semiconductor switching device, namely, a third transistor M3 connected between nodes PL4 and PL5. The input of the weak drive inverter is connected to PL6, and its output is connected to PL4. The source and drain of the third transistor M3 are connected to PL4 and PL5 respectively, and its gate receives the enable control signal. After the system enters steady state, the enable signal turns on the third transistor M3, activating the slow loop. Due to the weak drive current of the weak drive inverter and the relatively large on-resistance of the third transistor M3, the time constant of this loop is significantly larger than that of the fast latch feedback loop. This effectively suppresses node leakage and thermal noise during long-term standby, maintaining a stable latched state without drift. Furthermore, the bootstrap hold feedback path buffers the power-on reset signal POR output by the system and feeds it back to the latch node, such as PL4. When POR is released, this path applies a weak clamp to the node, keeping the level away from the inverter flip-flop threshold, significantly improving the resistance to power supply noise and process fluctuations. This three-stage feedback mechanism works together to achieve the design goal of "fast response - long-term hold - robust hardening," providing a highly reliable latching foundation for the zero quiescent current power-on reset circuit.

[0042] In some examples, the third transistor M3 has a four-terminal structure, including a gate, a source, a drain, and a body. The gate is connected to the third capacitor C0, the drain is connected to the first node PL4, and the source and body are both connected to the positive power supply VDD.

[0043] In one embodiment, the fast latch feedback loop includes an inverter chain for accelerating the generation of a reset pulse; the slow hold feedback loop includes an inverter and a third semiconductor switch, the input of the inverter is coupled to a first latch node, the output of the inverter is coupled to a first terminal of the third semiconductor switch, the second terminal of the third semiconductor switch is coupled to a second latch node, and the control terminal of the third semiconductor switch is coupled to a latch output node; when the latch output node is active, the third semiconductor switch is turned on, causing the inverter to form a weak feedback path between the first latch node and the second latch node.

[0044] In one embodiment, the power-on reset circuit further includes an undervoltage detection module 3 and a reset management module 4. The undervoltage detection module 3 is coupled to the voltage divider node and the detection node of the power-on detection module 1. The undervoltage detection module 3 reuses the resistor array voltage divider circuit and the capacitor array charging and discharging circuit of the power-on detection module 1 to generate an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold. The first input terminal of the reset management module 4 is coupled to the output terminal of the pulse latch module 2 to receive the reset pulse, and the second input terminal of the reset management module 4 is coupled to the output terminal of the undervoltage detection module 3 to receive the undervoltage detection signal. The reset management module 4 is used to receive the reset pulse and the undervoltage detection signal, and to generate a system reset signal based on the reset pulse and the undervoltage detection signal.

[0045] In one embodiment, the undervoltage detection module 3 includes a fourth semiconductor switching device. The control terminal of the fourth semiconductor switching device is electrically connected to the voltage divider node of the power-on detection module 1, the first terminal is connected to the reference ground, and the second terminal is electrically connected to the input terminal of the reset management module 4. The fourth semiconductor switching device turns on and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold.

[0046] In some specific embodiments, the undervoltage detection module 3 multiplexes the resistor divider signal and capacitor unit of the power-on detection module 1. The undervoltage divider signal EN_BO is input to the first inverter. The first inverter outputs the undervoltage detection signal PD_BO. The undervoltage detection signal PD_BO simultaneously drives the gate of the tenth transistor M10 and the gate of the eleventh transistor M11. The tenth transistor M10 is a PMOS transistor. The source of M10 is connected to the positive power supply. The body of M10 is connected to the positive power supply. The eleventh transistor M11 is an N-channel metal-oxide-semiconductor (NMOS) transistor. The source of M11 is connected to the reference ground. The body of M11 is connected to the reference ground. The drains of M10 and M11 are connected together to the bootstrap node CAP_VDD. The bootstrap node CAP_VDD is connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the reference ground. The bootstrap node CAP_VDD is connected to the gate of the fourth transistor M4. The fourth transistor M4 is a PMOS transistor. The source of transistor M4 is connected to the positive power supply. The body of transistor M4 is connected to the positive power supply. The drain of transistor M4 is connected to the bootstrap node CAP_VDD. The bootstrap node CAP_VDD is connected to the drain of the ninth transistor M9. The source of the ninth transistor M9 is connected to the input of the second inverter. This input is defined as the second latch node PL5. The output of the second inverter is defined as the latch output node PL6. Node PL6 is connected to the drain of the eighth transistor M8. The first latch node PL4 is connected to the drain of the seventh transistor M7. The gates of M7 and M8 are connected to the junction of the drains of the fifth transistor M5 and the sixth transistor M6. The fifth transistor M5 is a PMOS transistor. The source of M5 is connected to the positive power supply. The body of M5 is connected to the positive power supply. The gate of M5 is connected to the positive power supply. The sixth transistor M6 is an NMOS transistor. The source of M6 is connected to reference ground. The body of M6 is connected to reference ground. The gate of M6 is connected to the positive power supply. The seventh transistor M7 and the eighth transistor M8 are both NMOS transistors. Both the source and body terminals of the two buffers are connected to reference ground. Node PL6 is connected to the input of the first buffer. The output of the first buffer is connected to the input of the second buffer. The output of the second buffer generates the system reset signal POR. The eleventh transistor M11 acts as the fourth semiconductor switch. When the power supply voltage is below the undervoltage threshold, the undervoltage divider signal EN_BO decreases. The undervoltage detection signal PD_BO increases. M11 turns on. The bootstrap node CAP_VDD is pulled low to the reference ground potential. This low level is transmitted to node PL5 via M9. The second inverter flips the signal and outputs it to node PL6. Node PL6 maintains a valid reset state. The two-stage buffers shape this state and output a continuously valid POR signal. The system thus achieves reliable protection and state maintenance during power drop.

[0047] In one embodiment, the power-on reset circuit includes a multi-mode configuration interface connected to a resistor array and a capacitor array via a fifth semiconductor switching device to adjust the voltage division ratio of the resistor array and / or the charge / discharge time constant of the capacitor array.

[0048] In some specific embodiments, the multi-mode configuration interface outputs a configuration enable signal and a configuration data signal. The control terminal of the fifth semiconductor switch is connected to the configuration enable signal. The first terminal of the fifth semiconductor switch is connected to the configuration data signal. The second terminal of the fifth semiconductor switch is connected to the control terminal of the sixth semiconductor switch in the resistor array. When the configuration enable signal is high, the fifth semiconductor switch is turned on. The configuration data signal is transmitted to the control terminal of the sixth semiconductor switch through this path. The sixth semiconductor switch selects the corresponding resistor branch according to the configuration data signal. The voltage division ratio of the resistor array is dynamically adjusted. After configuration, the configuration enable signal is set to low. The fifth semiconductor switch is turned off. A high-impedance isolation is formed between the multi-mode configuration interface and the core detection circuit. This isolation effectively suppresses static leakage current and blocks external noise coupling. The second terminal of the fifth semiconductor switch can also be connected to the control terminal of the seventh semiconductor switch in the capacitor array. The configuration data signal controls the access state of the capacitor unit. The charging and discharging time constant of the capacitor array can be flexibly set. The system reset threshold and reset pulse width are adapted to different application scenarios. The fifth semiconductor switching device serves as a dedicated switch for configuring the path, ensuring reliable signal transmission during the configuration phase and achieving complete isolation during normal operation, while balancing multi-mode flexibility and zero quiescent current characteristics.

[0049] Specifically, such as Figure 3 As shown, the top-level structure of PSU_POR uses the battery-powered power rail VDDBAT as its operating voltage base and receives three key external signals: the undervoltage detection enable signal EN_BO, the hardware reset signal HWRESETN, and the I / O controller clock signal IOC_CLK. The main module PSU_POR_RMPDET_BO, which handles the power-on reset and undervoltage detection, processes EN_BO and HWRESETN to generate the initial power-on reset signal POR. This POR signal, along with EN_BO, is input to the first-stage two-input AND gate AN2X1, whose output is connected to the input of the reset signal debouncing module PSU_POR_DEGLITCH, enhancing the enable logic of the undervoltage trigger circuit. PSU_POR_DEGLITCH filters and shapes the signal, outputting a stable and reliable internal reset signal intRSTN, effectively suppressing transient glitches caused by power fluctuations.

[0050] The internal reset signal intRSTN, after being inverted by inverter INVX2, is fed into a three-input NAND gate ND3X1 along with the output signals C0 and C1 of the first two flip-flops in the synchronous release chain. The output of ND3X1, along with the IOC_CLK signal, is clock-gated by a second-stage two-input AND gate AN2X1. The generated clock pulse drives the first-stage D flip-flop FDS2X1 with asynchronous clear function. This synchronous release chain consists of three stages of FDS2X1 connected in series. The asynchronous clear input TJ of each stage of FDS2X1 is connected to intRSTN, ensuring that all flip-flop states are forcibly cleared when the reset command is issued. The output signals C0, C1, and C2 of the three stages of FDS2X1 are inverted by three inverters INVX1 and then participate in subsequent logic control. Among them, the C2 signal, along with intRSTN, is input to a two-input NAND gate ND2X8 to generate the I / O controller enable signal EN_IOC, which is only effectively activated after the reset is completed and the clock synchronization is stable. Meanwhile, the intRSTN signal is enhanced by the buffer BUFx4 and outputs the global reset signal RSTN_DIGITS in the digital logic domain, providing strong driving capability for subsequent high-load circuits.

[0051] This embodiment achieves precise generation of reset signals, noise suppression, clock synchronization release, and hierarchical enable control through multi-level logic collaboration. The hardware reset signal HWRESETN has the highest priority and can force the system into a reset state; the logical combination of EN_BO and POR ensures that undervoltage events are reliably captured; the three-level synchronization release chain advances the reset release process step by step based on the IOC_CLK clock edge, effectively avoiding metastability risks; the EN_IOC signal ensures that the I / O controller is enabled after the system is fully stable, and RSTN_DIGITS provides a highly reliable global reset for the digital logic domain. The entire design takes into account the monitoring requirements of multiple power domains and the rigor of system startup timing, significantly improving the robustness and startup reliability of the SoC or power management chip under power fluctuations and abnormal operating conditions.

[0052] like Figure 4 As shown, in one embodiment, the power-on reset circuit includes a debouncing circuit connected to the input terminal of the reset management module 4. This debouncing circuit debounces the reset pulse or undervoltage detection signal to eliminate glitches caused by power fluctuations, noise interference, or switching transients, ensuring the stability and reliability of the reset signal. The figure shows a schematic diagram of the PSU_POR_DEGLITCH debouncing circuit in one embodiment of the present invention. Its core function is to perform low-pass filtering and logic latching of the input reset signal IN to prevent erroneous resets triggered by brief glitches.

[0053] The input signal IN is first amplified by a buffer BUFx2 and then split into two paths, which are fed into two delay units DLY4 respectively. These two delay units have the same delay characteristics, but the circuits are independent of each other, forming a time-differential structure. One of the delayed signals is inverted by a NOT gate INVx2 and then input together with the other delayed signal to the first-stage two-input NAND gate ND2x8, achieving smoothing of the rising and falling edges of the input signal. At the same time, the two delayed signals are also connected to a two-input OR gate OR2x8, whose output serves as a feedback signal, which is used to maintain the state through a latch structure composed of two subsequent NAND gates ND2x8. This latch structure uses a positive feedback mechanism, allowing only pulses of a certain width to pass through when the input signal changes, while brief glitches cannot be sustained for a sufficient time to trigger the latching action, thus being effectively suppressed. Finally, the signal after multi-stage logic combination and latching is output as OUT by an inverter INVx2, forming a stable and jitter-free reset signal. This debouncing circuit is built using standard logic units and features high noise immunity, low power consumption, and good process compatibility. It is suitable for applications in battery-powered systems where the stability of the reset signal is extremely important.

[0054] like Figure 5 As shown in the diagram, in one specific embodiment, this invention provides a simulation and verification environment schematic of a top-level test platform for a power management unit power-on reset module (PSU_POR), used to comprehensively evaluate the functional integrity and robustness of the power-on reset (POR) circuit under different power conditions and external interference. The test platform is centered on the PSU_POR module, with its input connected to multiple controlled excitation sources and its output connected to a load network and monitoring nodes, forming a complete closed-loop verification system. In the test platform, the main power supply VDDBAT simulates the impedance characteristics of the actual power supply circuit through resistor R0 and applies an AC voltage source V0 to simulate transient fluctuations or ripple interference during power-on. Simultaneously, three DC voltage sources are independently configured: V1 generates an undervoltage divider signal EN_BO to simulate the undervoltage detection enable state; V2 generates an HWRESETN signal, representing the hardware reset input; and V3 provides an IOC_CLK clock signal to achieve synchronous control of the reset release. These excitation sources are connected to the corresponding input pins of the PSU_POR module, and their levels, rise times, and delays can be adjusted independently to cover various typical working scenarios and boundary conditions.

[0055] The PSU_POR module outputs RSTN_DIGITS and EN_IOC signals, both coupled to GND via capacitors C0 and C1. These are used to capture signal edge characteristics and filter out high-speed noise, facilitating observation of the reset pulse width, glitches, and stability during simulation. Additionally, the EN_IOC signal, driven by buffer BUFx1, is fed into the PSU_IOC module, a typical I / O controller interface unit containing a transmission gate structure composed of M1 to M4, used to simulate the response behavior of I / O enable logic. M1 and M2 form a PMOS transmission pair, and transistors M3 and M4 form an NMOS transmission pair, jointly implementing bidirectional signal path control. Finally, the PSU_IOC output is grounded via capacitor C2, used to observe the setup time and hold characteristics of the output signal. This test platform achieves dynamic simulation of the entire process of the PSU_POR module from power-on startup, undervoltage response to reset release by accurately modeling the power rail, reset signal source and downstream load. It can effectively verify its debouncing capability, multi-level synchronization mechanism and performance in handling abnormal events, providing complete technical support for functional verification and reliability analysis in the chip design stage.

[0056] In one embodiment, the power-on reset circuit includes at least one feedback semiconductor switch. The control terminal of each feedback semiconductor switch is connected to the output terminal of the reset management module 4. The first terminal of each feedback semiconductor switch is connected to the first latch node, and the second terminal of each feedback semiconductor switch is connected to the positive power supply node. The feedback semiconductor switch is used to turn on after the system reset is released and apply a pull-up current to the first latch node to maintain a stable level.

[0057] In one specific embodiment, the feedback semiconductor switching device is a weakly driven PMOS transistor. Its control terminal (gate) is connected to the power-on reset signal RSTN_DIGITS output by the reset management module 4, its first terminal (drain) is connected to the first latch node PL4 of the pulse latch module 2, and its second terminal (source) is connected to the positive power supply VDD. When the system reset is released, the RSTN_DIGITS signal changes from low to high, the PMOS transistor turns on, and a controllable weak pull-up current is applied to the PL4 node, so that the node level is stably maintained in the high-level region, far away from the inverter switching threshold. The weak pull-up strength is precisely set by the transistor channel size to ensure complete turn-off during the reset period (when RSTN_DIGITS is low), without affecting the normal switching of the latch; it only provides anti-interference reinforcement during the stable operation phase of the system, effectively suppressing level drift caused by node leakage, thermal noise, and process fluctuations. This design directly implements the POR signal feedback to the latch node in the bootstrap holding feedback path to achieve a weak clamping effect, which enhances the state holding capability of the pulse latch module 2 under long-term standby, while avoiding the introduction of additional static power consumption, in line with the zero static current design goal.

[0058] In one embodiment, the resistor array of the power-on detection module 1 includes multiple resistor branches, each resistor branch including a resistor device and a sixth semiconductor switch device, the sixth semiconductor switch device being connected in series with the resistor device.

[0059] In one specific embodiment, the resistor array of the power-on detection module 1 consists of multiple parallel resistor branches. Each branch includes a resistor and a sixth semiconductor switch, which are connected in series between the power supply and the voltage divider node. The sixth semiconductor switch is an NMOS transistor, and its control terminal receives the configuration data signal transmitted by the fifth semiconductor switch. When the configuration data signal is valid, the corresponding branch is turned on and participates in voltage division; when invalid, the branch is isolated. By programming the on / off combination of the sixth semiconductor switch in each branch, the equivalent resistance value of the resistor array can be dynamically adjusted, thereby accurately setting the power-on detection threshold voltage. After configuration, the state of the sixth semiconductor switch remains locked, ensuring a stable voltage division ratio during detection, and no additional static current is generated because the switch is completely turned off, meeting the zero static current design goal. This structure is also reused by the undervoltage detection module 3, realizing flexible configuration of dual thresholds for power-on reset and undervoltage protection.

[0060] In one embodiment, the capacitor array of the power-on detection module 1 includes multiple capacitors, each capacitor being connected to the detection node of the undervoltage detection module 3 via a corresponding seventh semiconductor switching device.

[0061] In some specific embodiments, the capacitor array of the power-on detection module 1 consists of multiple capacitors. One end of each capacitor is connected to a reference ground, and the other end is selectively connected to the detection node of the undervoltage detection module 3 (i.e., the voltage divider node EN_BO of the multiplexed resistor array) via a corresponding seventh semiconductor switch. The seventh semiconductor switch is an NMOS transistor, and its control terminal receives the configuration data signal transmitted by the fifth semiconductor switch. When the configuration data signal is valid, the seventh semiconductor switch is turned on, and the corresponding capacitor is connected to the EN_BO node, increasing the node's equivalent capacitance and extending the charging and discharging time constant, thus enabling the detection circuit to resist power transient drops or glitches. When the configuration data signal is invalid, the capacitor is isolated, and the node response speed is improved. This structure is reused collaboratively by the power-on detection module 1 and the undervoltage detection module 3: adjusting the reset pulse generation timing during power-on and optimizing detection sensitivity and response delay during undervoltage events. After configuration, the seventh semiconductor switch is locked, with no static current circuit, meeting the zero static current design goal; at the same time, by programming different capacitor combinations, it can independently adapt to the differentiated requirements of reset reliability and system robustness in multiple application scenarios.

[0062] In one embodiment, the power-on detection module 1 includes at least one feedback circuit, each feedback circuit including an eighth semiconductor switching device, the control terminal of the eighth semiconductor switching device being connected to the voltage divider node of the power-on detection module 1, the first terminal of the eighth semiconductor switching device being connected to the output node of the undervoltage detection module 3, and the second terminal of the eighth semiconductor switching device being connected to the second latch node.

[0063] In one specific implementation, the eighth semiconductor switch in the feedback circuit is an NMOS transistor. Its control terminal receives the undervoltage detection enable signal EN_BO. Its first terminal (drain) is connected to the core output node CAP_VDD of the undervoltage detection module 3, and its second terminal (source) is connected to the second latch node PL5 of the pulse latch module 2. When the power supply voltage is lower than the undervoltage threshold, the bootstrap node CAP_VDD is pulled low. At this time, the undervoltage divider signal EN_BO is valid, the eighth semiconductor switch is turned on, and the low-level state of CAP_VDD is quickly transmitted to the PL5 node, directly triggering the state flip of the pulse latch module 2, accelerating the generation and maintenance of the reset pulse. This circuit, as a feedback circuit for undervoltage events, significantly shortens the transmission delay of the detection signal to the latch, improving the system's response speed to power drops. Under normal operating conditions, the undervoltage divider signal EN_BO is invalid, causing the eighth semiconductor switch to turn off, completely isolating CAP_VDD from the PL5 node, avoiding noise coupling and static leakage, strictly adhering to the zero quiescent current design goal.

[0064] It is worth noting that the PMOS transistors include M2, M4, M5, M10, M12, M14 and M16, all of which have their body terminals connected to the positive power supply VDD; the NMOS transistors include M1, M3, M6, M7, M8, M9, M11, M13, M15, M17 and M18, all of which have their body terminals connected to the reference ground VSS.

[0065] like Figure 6 As shown in some examples, the timing waveform diagram of a typical power-on process in one embodiment of the present invention illustrates the dynamic response relationship between the power supply voltage VDD_MAIN and the system reset signal RSTN_DIGITS during the power-on phase. The horizontal axis represents time, and the vertical axis represents voltage values.

[0066] During the initial power-on phase, VDD_MAIN rises linearly from 0V. When it reaches the preset power-on detection threshold voltage (approximately 0.7V), the circuit triggers the reset pulse generation mechanism, and the RSTN_DIGITS signal transitions from high to low, entering a valid reset state. As VDD_MAIN continues to rise and stabilizes at the target operating voltage (e.g., 1.8V), RSTN_DIGITS remains low for a period to ensure sufficient initialization of the system's internal logic. Once VDD_MAIN is fully stable and the release condition is met, the RSTN_DIGITS signal returns to high after a predetermined delay, signifying the completion of the reset process and the system entering normal operating mode. This waveform clearly demonstrates the power-on reset circuit's precise monitoring of the power supply rising edge, reliable generation of the reset pulse, and orderly control of the reset release, verifying the functional integrity and timing stability of the zero quiescent current power-on reset circuit of this invention in practical applications.

[0067] like Figure 7 As shown, a typical waveform diagram of a hardware reset triggered in one embodiment of the present invention illustrates the timing response relationship of key system nodes under the action of an external hard reset signal. The diagram contains four signal curves, from top to bottom: VDD_MAIN power supply voltage, HWRESETN hardware reset signal, RSTN_DIGITS digital reset signal, and IOC_CLK I / O controller clock signal.

[0068] At t=201.0μs, the HWRESETN signal transitions from high to low, triggering a hardware reset event. At this time, VDD_MAIN remains stable, indicating that the reset is an external control signal independent of the power supply state. The RSTN_DIGITS signal is then pulled low, entering a valid reset state for the same duration as HWRESETN, ensuring synchronous reset of system logic units. Simultaneously, the EN_IOC signal is also set low, disabling I / O controller operation and preventing erroneous outputs during the reset. When HWRESETN returns to high at t=201.6μs, RSTN_DIGITS remains low for a period to complete the internal debouncing and synchronization release process, then returns to high at the next rising edge of IOC_CLK, achieving clock synchronization for the reset release. IOC_CLK continuously provides a stable clock pulse throughout the process, with a period of approximately 0.1μs, used to drive the D flip-flops in the reset release chain, ensuring precise timing of the reset signal release. The waveform verifies the fast response capability, multi-level synchronization mechanism, and reliable enable control of the I / O controller of the power-on reset circuit of the present invention under external hard reset scenarios, fully demonstrating the robustness and stability of the system under abnormal operating conditions.

[0069] like Figure 8As shown, according to a second embodiment of the present invention, a parameter optimization method for a power-on reset circuit is provided. The power-on reset circuit includes a power-on detection module, a pulse latch module, a bootstrap capacitor, a first semiconductor switching device, and a second semiconductor switching device. The method includes the following steps S1-S6: S1 defines the design parameter space, which includes the combination of circuit parameters for the power-on reset circuit.

[0070] S2 allows you to set multiple test scenarios, covering the range of changes in process corners, power supply voltage, and temperature.

[0071] S3 obtains performance datasets through circuit simulation based on the combination of circuit parameters and test scenarios in the design parameter space.

[0072] S4 trains an AI prediction model based on a performance dataset. The AI ​​prediction model is used to predict the performance metrics of a given combination of circuit parameters in a test scenario.

[0073] S5, based on an artificial intelligence prediction model, uses a multi-objective optimization algorithm to search for Pareto optimal solutions that satisfy preset constraints in the design parameter space. The Pareto optimal solution corresponds to at least one set of circuit parameter combinations.

[0074] S6 generates the layout data of the power-on reset circuit based on the target circuit parameter combination.

[0075] In one embodiment, the design parameter space includes at least one of the following: the resistance value of each branch of the resistor array in the power-on detection module 1 and the connection status of each branch; the capacitance value of each capacitor in the capacitor array in the power-on detection module 1 and the connection status of each unit; the channel width to channel length ratio of the semiconductor switching device in the power-on reset circuit; the channel width to channel length ratio of the semiconductor switching device in the slow hold feedback loop in the pulse latch module 2; the enable status of the slow hold feedback loop; and the counting threshold and time constant of the debouncing circuit in the power-on reset circuit.

[0076] In some specific embodiments, the design parameter space encompasses the key configurable physical and electrical parameters in the power-on reset circuit. Specifically, this includes: the nominal resistance values ​​of each branch in the resistor array of the power-on detection module and their access states controlled by the sixth semiconductor switching device, used to dynamically set the reset trigger threshold and adapt to different power supply slopes; the nominal capacitance values ​​of each unit in the capacitor array and their access states controlled by the seventh semiconductor switching device, used to adjust the charging and discharging time constants of the detection nodes, balancing response speed and glitches; the channel width to length ratio (W / L) of each semiconductor switching device in the circuit (including the first to fourth semiconductor switching devices and the switching devices in the feedback circuit), directly affecting on-resistance, switching speed, and subthreshold leakage characteristics; the W / L ratio and activation state of the semiconductor switching devices (such as the third semiconductor switching device) in the slow-hold feedback loop of the pulse latch module, used to achieve an optimized balance between fast latching and long-term static holding; and the counting threshold and time constant in the debouncing circuit, determining the glitches suppression depth and reset release delay. The above parameters can be flexibly combined through a multi-mode configuration interface to form a high-dimensional design variable set, providing sufficient training dimensions for artificial intelligence prediction models. This ensures that the multi-objective optimization algorithm can accurately find the Pareto optimal solution that balances reset accuracy, static power consumption, timing margin, and robustness under full PVT conditions. Finally, the optimized parameters are solidified into the layout, significantly improving the performance consistency and reliability of mass-produced chips under complex operating conditions.

[0077] In one embodiment, the power-on reset circuit includes an undervoltage detection module 3; the undervoltage detection module 3 reuses part of the resistor array and capacitor array of the power-on detection module 1, and the undervoltage detection module 3 includes a fourth semiconductor switching device, which turns on and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold; the performance dataset includes: the power-on reset threshold voltage of the power-on detection module 1, the undervoltage detection threshold voltage of the undervoltage detection module 3, the reset release delay of the pulse latch module 2, the undervoltage response time of the undervoltage detection module 3, the quiescent current of the power-on reset circuit, and the internal node voltage margin of the pulse latch module 2.

[0078] In one specific implementation, the power-on reset circuit integrates an undervoltage detection module. This module reuses the resistor array voltage divider node EN_BO of the power-on detection module and the first capacitor C1 in the capacitor array to achieve efficient resource sharing. The core of the undervoltage detection module is the fourth semiconductor switching device (eleventh transistor M11, NMOS), whose gate receives the undervoltage detection signal PD_BO processed by the inverter. Its source and body are connected to the reference ground, and its drain is connected to the bootstrap node CAP_VDD. When the power supply voltage is lower than the undervoltage threshold, the PD_BO potential rises, driving M11 to conduct and pulling CAP_VDD down to the reference ground potential, generating an effective undervoltage detection signal. Based on this structure, the performance dataset accurately covers six key indicators: the power-on reset threshold voltage of the power-on detection module, the undervoltage detection threshold voltage of the undervoltage detection module, the reset release delay of the pulse latch module, the undervoltage response time of the undervoltage detection module, the quiescent current of the power-on reset circuit, and the voltage margin of the internal latch nodes (PL4 / PL5 / PL6) of the pulse latch module relative to the inverter flip-flop threshold. This dataset comprehensively characterizes the overall performance of circuits in four dimensions: reset accuracy, timing characteristics, power consumption level, and robustness. It provides high-fidelity training samples for artificial intelligence prediction models, ensuring that multi-objective optimization algorithms accurately select the Pareto optimal parameter combination that balances threshold stability, ultra-low static power consumption, sufficient timing margin, and strong anti-interference capability across the entire PVT domain. Ultimately, it achieves high consistency in reset behavior and system reliability of mass-produced chips under complex operating conditions.

[0079] In one implementation, the preset constraints include an upper limit on the layout area and a transient peak current threshold. The optimization objectives of the multi-objective optimization algorithm include at least two of the following: power-on reset threshold voltage, undervoltage detection threshold voltage, quiescent current, internal node voltage margin, reset release delay, and undervoltage response time.

[0080] In one specific implementation, the multi-objective optimization process strictly sets engineering constraint boundaries: the upper limit of the layout area is used to control the chip's physical size and integration cost, and the transient peak current threshold is used to suppress power network voltage drop, avoid electromigration risks, and electromagnetic interference. The optimization objectives are dynamically selected from the performance dataset for synergistic trade-offs. For example, for high reliability scenarios, the focus is on optimizing the process-temperature drift coefficients of the power-on reset threshold voltage and undervoltage detection threshold voltage, as well as the internal node voltage margin of the pulse latch module; for ultra-low power scenarios, the focus is on minimizing static current and precisely controlling the reset release delay; for fast response scenarios, the focus is on optimizing the undervoltage response time and reset release delay. Through Pareto front analysis, the algorithm generates a non-dominated solution set within the constraint boundaries, allowing designers to flexibly select the optimal parameter combination based on product positioning (e.g., IoT devices prioritize power consumption, while automotive electronics prioritize robustness). This strategy ensures that the final layout satisfies both physical and electrical hard constraints and achieves engineering optimization in the selected performance dimensions, significantly improving the consistency of reset behavior, anti-interference capability, and system-level reliability of mass-produced chips under complex PVT conditions.

[0081] In one implementation, the method includes: selecting at least one set of target circuit parameter combinations from Pareto optimal solutions; configuring configurable branches in a power-on reset circuit to default connection states corresponding to the target circuit parameter combinations; and defining a mapping relationship between mode identifiers and default connection states.

[0082] In one specific implementation, designers select one or more sets of target circuit parameter combinations from the Pareto optimal solution set based on product positioning and process constraints. The selected parameter combinations directly correspond to the default connection states of configurable branches in the power-on reset circuit, including the access states of each branch of the resistor array, the enable states of each unit of the capacitor array, and the size configuration and enable states of the semiconductor switching devices in the slow hold feedback loop. Through a multi-mode configuration interface, the control logic of the fifth semiconductor switching device is embedded in a non-volatile memory cell, enabling the sixth and seventh semiconductor switching devices to be automatically configured to preset connection states during the initial stage of system power-on, achieving optimal electrical characteristics without external intervention. Simultaneously, the mapping relationship between mode identifier signals and each default connection state is explicitly defined in the chip register mapping; for example, mode zero corresponds to high-precision reset threshold configuration, mode one corresponds to ultra-low static power consumption configuration, and mode two corresponds to fast undervoltage response configuration. When the system powers on, the configuration logic automatically loads the corresponding connection states based on the preset mode identifiers, ensuring that the reset threshold, response timing, and power consumption characteristics strictly match the application scenario requirements. This method seamlessly transforms AI optimization results into hardware configuration strategies, significantly reducing user complexity, avoiding on-site configuration errors, and ensuring that mass-produced chips can stably perform at their optimal, simulation-verified performance under different application modes, thereby enhancing product adaptability and market competitiveness.

[0083] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0084] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. A zero-static-current power-on reset circuit, applied to a power control system, characterized in that, The power-on reset circuit includes a power-on detection module and a pulse latch module that are interconnected. The power-on detection module includes a resistor array, a capacitor array, a first semiconductor switch, and a second semiconductor switch. The control terminal of the first semiconductor switch is connected to the output node of the capacitor array. A first terminal of the first semiconductor switch is connected to a reference ground, and a second terminal of the first semiconductor switch is connected to the input terminal of the pulse latch module. The first semiconductor switch is used to turn on and output a power-on detection trigger signal when the detection signal reaches a power-on threshold. The second semiconductor switch is connected in series between the input power supply and the resistor array. The resistor array is used to divide the voltage of the input power supply to generate a voltage divider signal. The capacitor array is used to generate a detection signal based on the voltage divider signal. The pulse latch module integrates a bootstrap capacitor. The first end of the bootstrap capacitor is connected to the control terminal of the second semiconductor switching device, and the second end of the bootstrap capacitor is connected to the internal node of the pulse latch module. The pulse latch module is used to receive the power-on detection trigger signal and generate a reset pulse. During the generation of the reset pulse, the bootstrap capacitor is charged. After the reset pulse is generated, the pulse latch module is used to transfer the charge of the bootstrap capacitor to the control terminal of the second semiconductor switch, raise the voltage of the control terminal, drive the second semiconductor switch to turn off, and cut off the DC voltage divider path composed of the resistor array, power supply and reference ground.

2. The power-on reset circuit according to claim 1, characterized in that, The pulse latch module includes a first latch node, a second latch node, a latch output node, a fast latch feedback loop, and a slow hold feedback loop; the first latch node is connected to the second terminal of the first semiconductor switching device; the latch output node is driven by the second latch node and serves as the output terminal of the reset pulse; the fast latch feedback loop is coupled between the first latch node, the second latch node, and the latch output node; the slow hold feedback loop is coupled between the first latch node and the second latch node; and the time constant of the slow hold feedback loop is greater than the time constant of the fast latch feedback loop.

3. The power-on reset circuit according to claim 2, characterized in that, The fast latch feedback loop includes an inverter chain used to accelerate the generation of the reset pulse; the slow hold feedback loop includes an inverter and a third semiconductor switch. The input of the inverter is coupled to the first latch node, the output of the inverter is coupled to the first terminal of the third semiconductor switch, the second terminal of the third semiconductor switch is coupled to the second latch node, and the control terminal of the third semiconductor switch is coupled to the latch output node. When the latch output node is at an active level, the third semiconductor switch is turned on, causing the inverter to form a weak feedback path between the first latch node and the second latch node.

4. The power-on reset circuit according to claim 2, characterized in that, The power-on reset circuit also includes an undervoltage detection module and a reset management module; the undervoltage detection module is coupled to the voltage divider node and detection node of the power-on detection module, and the undervoltage detection module reuses the resistor array voltage divider circuit and capacitor array charging and discharging circuit of the power-on detection module to generate an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold. The first input terminal of the reset management module is coupled to the output terminal of the pulse latch module to receive the reset pulse, and the second input terminal of the reset management module is coupled to the output terminal of the undervoltage detection module to receive the undervoltage detection signal. The reset management module is used to receive the reset pulse and the undervoltage detection signal, and generate a system reset signal based on the reset pulse and the undervoltage detection signal.

5. The power-on reset circuit according to claim 4, characterized in that, The undervoltage detection module includes a fourth semiconductor switching device. The control terminal of the fourth semiconductor switching device is electrically connected to the voltage divider node of the power-on detection module, the first terminal is connected to the reference ground, and the second terminal is electrically connected to the input terminal of the reset management module. The fourth semiconductor switching device turns on and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold.

6. The power-on reset circuit according to claim 1, characterized in that, The power-on reset circuit includes a multi-mode configuration interface, which is connected to the resistor array and capacitor array via a fifth semiconductor switching device to adjust the voltage division ratio of the resistor array and / or the charge / discharge time constant of the capacitor array.

7. The power-on reset circuit according to claim 4, characterized in that, The power-on reset circuit includes a debounce circuit, which is connected to the input terminal of the reset management module and is used to debounce the reset pulse or the undervoltage detection signal.

8. The power-on reset circuit according to claim 2, characterized in that, The power-on reset circuit includes at least one feedback semiconductor switching device. The control terminal of each feedback semiconductor switching device is connected to the output terminal of the reset management module. The first terminal of each feedback semiconductor switching device is connected to the first latch node, and the second terminal of each feedback semiconductor switching device is connected to the positive power supply node. The feedback semiconductor switching device is used to turn on after the system is reset and applied to the first latch node to maintain a stable level.

9. The power-on reset circuit according to claim 1, characterized in that, The power-on detection module has a resistor array comprising multiple resistor branches, each of which includes a resistor and a sixth semiconductor switch, wherein the sixth semiconductor switch is connected in series with the resistor.

10. The power-on reset circuit according to claim 4, characterized in that, The capacitor array of the power-on detection module includes multiple capacitors, each of which is connected to the detection node of the undervoltage detection module via a corresponding seventh semiconductor switching device.

11. The power-on reset circuit according to claim 4, characterized in that, The power-on detection module includes at least one feedback circuit, and each feedback circuit includes an eighth semiconductor switching device. The control terminal of the eighth semiconductor switching device is connected to the voltage divider node of the power-on detection module, the first terminal of the eighth semiconductor switching device is connected to the output node of the undervoltage detection module, and the second terminal of the eighth semiconductor switching device is connected to the second latch node.

12. A method for optimizing the parameters of a power-on reset circuit, characterized in that, The power-on reset circuit includes a power-on detection module, a pulse latch module, a bootstrap capacitor, a first semiconductor switching device, and a second semiconductor switching device. The method includes: Define a design parameter space, which includes the combination of circuit parameters of the power-on reset circuit; Multiple test scenarios are set up, covering the range of changes in process corner, power supply voltage, and temperature. Based on the circuit parameter combinations in the design parameter space and the test scenario, a performance dataset is obtained through circuit simulation. An artificial intelligence prediction model is trained based on the performance dataset, and the artificial intelligence prediction model is used to predict the performance index of a given combination of circuit parameters in the test scenario. Based on the artificial intelligence prediction model, a multi-objective optimization algorithm is used to search for Pareto optimal solutions that satisfy preset constraints in the design parameter space. The Pareto optimal solution corresponds to at least one set of circuit parameter combinations. Based on the target circuit parameter combination, the layout data of the power-on reset circuit is generated.

13. The parameter optimization method according to claim 12, characterized in that, The design parameter space includes at least one of the following: The power-on detection module includes the resistance values ​​of each branch of the resistor array and the connection status of each branch; the capacitor values ​​of each capacitor in the capacitor array and the connection status of each unit; the channel width to channel length ratio of the semiconductor switching device in the power-on reset circuit; the channel width to channel length ratio of the semiconductor switching device in the slow hold feedback loop of the pulse latch module; the activation status of the slow hold feedback loop; and the counting threshold and time constant of the debouncing circuit in the power-on reset circuit.

14. The parameter optimization method according to claim 12, characterized in that, The power-on reset circuit includes an undervoltage detection module; the undervoltage detection module reuses part of the resistor array and capacitor array of the power-on detection module, and the undervoltage detection module includes a fourth semiconductor switching device, which conducts and outputs an undervoltage detection signal when the power supply voltage is lower than the undervoltage threshold; the performance dataset includes: the power-on reset threshold voltage of the power-on detection module, the undervoltage detection threshold voltage of the undervoltage detection module, the reset release delay of the pulse latch module, the undervoltage response time of the undervoltage detection module, the quiescent current of the power-on reset circuit, and the internal node voltage margin of the pulse latch module.

15. The parameter optimization method according to claim 14, characterized in that, The preset constraints include an upper limit for the layout area and a transient peak current threshold. The optimization objectives of the multi-objective optimization algorithm include at least two of the power-on reset threshold voltage, the undervoltage detection threshold voltage, the quiescent current, the internal node voltage margin, the reset release delay, and the undervoltage response time.

16. The parameter optimization method according to claim 13, characterized in that, The method includes: Select at least one set of target circuit parameter combinations from the Pareto optimal solution; Configure the configurable branch in the power-on reset circuit to a default connection state corresponding to the target circuit parameter combination, and define the mapping relationship between the mode identifier and the default connection state.

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